1*27b72179Sskrll /* $NetBSD: dino.c,v 1.16 2022/09/29 06:39:58 skrll Exp $ */
2fdfdea60Sskrll
3fdfdea60Sskrll /* $OpenBSD: dino.c,v 1.5 2004/02/13 20:39:31 mickey Exp $ */
4fdfdea60Sskrll
5fdfdea60Sskrll /*
6fdfdea60Sskrll * Copyright (c) 2003 Michael Shalayeff
7fdfdea60Sskrll * All rights reserved.
8fdfdea60Sskrll *
9fdfdea60Sskrll * Redistribution and use in source and binary forms, with or without
10fdfdea60Sskrll * modification, are permitted provided that the following conditions
11fdfdea60Sskrll * are met:
12fdfdea60Sskrll * 1. Redistributions of source code must retain the above copyright
13fdfdea60Sskrll * notice, this list of conditions and the following disclaimer.
14fdfdea60Sskrll * 2. Redistributions in binary form must reproduce the above copyright
15fdfdea60Sskrll * notice, this list of conditions and the following disclaimer in the
16fdfdea60Sskrll * documentation and/or other materials provided with the distribution.
17fdfdea60Sskrll *
18fdfdea60Sskrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19fdfdea60Sskrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20fdfdea60Sskrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21fdfdea60Sskrll * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
22fdfdea60Sskrll * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23fdfdea60Sskrll * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24fdfdea60Sskrll * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25fdfdea60Sskrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26fdfdea60Sskrll * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
27fdfdea60Sskrll * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28fdfdea60Sskrll * THE POSSIBILITY OF SUCH DAMAGE.
29fdfdea60Sskrll */
30fdfdea60Sskrll
31fdfdea60Sskrll #include <sys/cdefs.h>
32*27b72179Sskrll __KERNEL_RCSID(0, "$NetBSD: dino.c,v 1.16 2022/09/29 06:39:58 skrll Exp $");
33fdfdea60Sskrll
34fdfdea60Sskrll /* #include "cardbus.h" */
35fdfdea60Sskrll
36fdfdea60Sskrll #include <sys/param.h>
37fdfdea60Sskrll #include <sys/systm.h>
38fdfdea60Sskrll #include <sys/device.h>
39fdfdea60Sskrll #include <sys/reboot.h>
40fdfdea60Sskrll #include <sys/extent.h>
41fdfdea60Sskrll
42fdfdea60Sskrll #include <machine/iomod.h>
43fdfdea60Sskrll #include <machine/autoconf.h>
44fdfdea60Sskrll #include <machine/intr.h>
45fdfdea60Sskrll
46fdfdea60Sskrll #include <hppa/include/vmparam.h>
47fdfdea60Sskrll #include <hppa/dev/cpudevs.h>
48fdfdea60Sskrll
49fdfdea60Sskrll #if NCARDBUS > 0
50fdfdea60Sskrll #include <dev/cardbus/rbus.h>
51fdfdea60Sskrll #endif
52fdfdea60Sskrll
53fdfdea60Sskrll #include <dev/pci/pcireg.h>
54fdfdea60Sskrll #include <dev/pci/pcivar.h>
55fdfdea60Sskrll #include <dev/pci/pcidevs.h>
56fdfdea60Sskrll
57fdfdea60Sskrll #define DINO_MEM_CHUNK 0x800000
58fdfdea60Sskrll
59fdfdea60Sskrll /* from machdep.c */
60fdfdea60Sskrll extern struct extent *hppa_io_extent;
61fdfdea60Sskrll
62fdfdea60Sskrll struct dino_regs {
63fdfdea60Sskrll /* HPA Supervisory Register Set */
64fdfdea60Sskrll uint32_t pad0; /* 0x000 */
65fdfdea60Sskrll uint32_t iar0; /* 0x004 rw intr addr reg 0 */
66fdfdea60Sskrll uint32_t iodc; /* 0x008 rw iodc data/addr */
67fdfdea60Sskrll uint32_t irr0; /* 0x00c r intr req reg 0 */
68fdfdea60Sskrll uint32_t iar1; /* 0x010 rw intr addr reg 1 */
69fdfdea60Sskrll uint32_t irr1; /* 0x014 r intr req reg 1 */
70fdfdea60Sskrll uint32_t imr; /* 0x018 rw intr mask reg */
71fdfdea60Sskrll uint32_t ipr; /* 0x01c rw intr pending reg */
72fdfdea60Sskrll uint32_t toc_addr; /* 0x020 rw TOC addr reg */
73fdfdea60Sskrll uint32_t icr; /* 0x024 rw intr control reg */
74fdfdea60Sskrll uint32_t ilr; /* 0x028 r intr level reg */
75fdfdea60Sskrll uint32_t pad1; /* 0x02c */
76fdfdea60Sskrll uint32_t io_command; /* 0x030 w command register */
77fdfdea60Sskrll uint32_t io_status; /* 0x034 r status register */
78fdfdea60Sskrll uint32_t io_control; /* 0x038 rw control register */
79fdfdea60Sskrll uint32_t pad2; /* 0x03c AUX registers follow */
80fdfdea60Sskrll
81fdfdea60Sskrll /* HPA Auxiliary Register Set */
82fdfdea60Sskrll uint32_t io_gsc_err_addr;/* 0x040 GSC error address */
83fdfdea60Sskrll uint32_t io_err_info; /* 0x044 error info register */
84fdfdea60Sskrll uint32_t io_pci_err_addr;/* 0x048 PCI error address */
85fdfdea60Sskrll uint32_t pad3[4]; /* 0x04c */
86fdfdea60Sskrll uint32_t io_fbb_en; /* 0x05c fast back2back enable reg */
87fdfdea60Sskrll uint32_t io_addr_en; /* 0x060 address enable reg */
88fdfdea60Sskrll uint32_t pci_addr; /* 0x064 PCI conf/io/mem addr reg */
89fdfdea60Sskrll uint32_t pci_conf_data; /* 0x068 PCI conf data reg */
90fdfdea60Sskrll uint32_t pci_io_data; /* 0x06c PCI io data reg */
91fdfdea60Sskrll uint32_t pci_mem_data; /* 0x070 PCI memory data reg */
92fdfdea60Sskrll uint32_t pad4[0x740/4]; /* 0x074 */
93fdfdea60Sskrll
94fdfdea60Sskrll /* HPA Bus (GSC) Specific-Dependent Register Set */
95fdfdea60Sskrll uint32_t gsc2x_config; /* 0x7b4 GSC2X config reg */
96fdfdea60Sskrll uint32_t pad5[0x48/4]; /* 0x7b8: BSRS registers follow */
97fdfdea60Sskrll
98fdfdea60Sskrll /* HPA HVERSION (Dino)-Dependent Register Set */
99fdfdea60Sskrll uint32_t gmask; /* 0x800 GSC arbitration mask */
100fdfdea60Sskrll uint32_t pamr; /* 0x804 PCI arbitration mask */
101fdfdea60Sskrll uint32_t papr; /* 0x808 PCI arbitration priority */
102fdfdea60Sskrll uint32_t damode; /* 0x80c PCI arbitration mode */
103fdfdea60Sskrll uint32_t pcicmd; /* 0x810 PCI command register */
104fdfdea60Sskrll uint32_t pcists; /* 0x814 PCI status register */
105fdfdea60Sskrll uint32_t pad6; /* 0x818 */
106fdfdea60Sskrll uint32_t mltim; /* 0x81c PCI master latency timer */
107fdfdea60Sskrll uint32_t brdg_feat; /* 0x820 PCI bridge feature enable */
108fdfdea60Sskrll uint32_t pciror; /* 0x824 PCI read optimization reg */
109fdfdea60Sskrll uint32_t pciwor; /* 0x828 PCI write optimization reg */
110fdfdea60Sskrll uint32_t pad7; /* 0x82c */
111fdfdea60Sskrll uint32_t tltim; /* 0x830 PCI target latency reg */
112fdfdea60Sskrll };
113fdfdea60Sskrll
114fdfdea60Sskrll struct dino_softc {
115fdfdea60Sskrll device_t sc_dv;
116fdfdea60Sskrll
117fdfdea60Sskrll int sc_ver;
118fdfdea60Sskrll void *sc_ih;
119fdfdea60Sskrll struct hppa_interrupt_register sc_ir;
120fdfdea60Sskrll bus_space_tag_t sc_bt;
121fdfdea60Sskrll bus_space_handle_t sc_bh;
122fdfdea60Sskrll bus_dma_tag_t sc_dmat;
123e827d593Sskrll
124e827d593Sskrll struct hppa_bus_dma_tag sc_dmatag;
125e827d593Sskrll struct hppa_bus_space_tag sc_memt;
126e827d593Sskrll
127fdfdea60Sskrll volatile struct dino_regs *sc_regs;
128fdfdea60Sskrll
129fdfdea60Sskrll struct hppa_pci_chipset_tag sc_pc;
130fdfdea60Sskrll struct hppa_bus_space_tag sc_iot;
131e827d593Sskrll
132fdfdea60Sskrll struct extent *sc_ioex;
133fdfdea60Sskrll int sc_memrefcount[30];
134e827d593Sskrll
135e827d593Sskrll char sc_ioexname[20];
136fdfdea60Sskrll };
137fdfdea60Sskrll
138fdfdea60Sskrll int dinomatch(device_t, struct cfdata *, void *);
139fdfdea60Sskrll void dinoattach(device_t, device_t, void *);
140fdfdea60Sskrll static device_t dino_callback(device_t, struct confargs *);
141fdfdea60Sskrll
142fdfdea60Sskrll CFATTACH_DECL_NEW(dino, sizeof(struct dino_softc), dinomatch, dinoattach, NULL,
143fdfdea60Sskrll NULL);
144fdfdea60Sskrll
145fdfdea60Sskrll void dino_attach_hook(device_t, device_t,
146fdfdea60Sskrll struct pcibus_attach_args *);
147fdfdea60Sskrll void dino_enable_bus(struct dino_softc *, int);
148fdfdea60Sskrll int dino_maxdevs(void *, int);
149fdfdea60Sskrll pcitag_t dino_make_tag(void *, int, int, int);
150fdfdea60Sskrll void dino_decompose_tag(void *, pcitag_t, int *, int *, int *);
151fdfdea60Sskrll pcireg_t dino_conf_read(void *, pcitag_t, int);
152fdfdea60Sskrll void dino_conf_write(void *, pcitag_t, int, pcireg_t);
153fdfdea60Sskrll
154fdfdea60Sskrll int dino_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
15541f223f1Schristos const char *dino_intr_string(void *, pci_intr_handle_t, char *, size_t);
156fdfdea60Sskrll void *dino_intr_establish(void *, pci_intr_handle_t, int,
157fdfdea60Sskrll int (*)(void *), void *);
158fdfdea60Sskrll void dino_intr_disestablish(void *, void *);
159fdfdea60Sskrll
160fdfdea60Sskrll void *dino_alloc_parent(device_t, struct pci_attach_args *, int);
161fdfdea60Sskrll
162fdfdea60Sskrll int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *);
163fdfdea60Sskrll int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *);
164fdfdea60Sskrll int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t,
165fdfdea60Sskrll bus_space_handle_t *);
166fdfdea60Sskrll int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t,
167fdfdea60Sskrll bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *);
168fdfdea60Sskrll int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t,
169fdfdea60Sskrll bus_size_t, int, bus_addr_t *, bus_space_handle_t *);
170fdfdea60Sskrll void dino_unmap(void *, bus_space_handle_t, bus_size_t);
171fdfdea60Sskrll void dino_free(void *, bus_space_handle_t, bus_size_t);
172fdfdea60Sskrll void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int);
173fdfdea60Sskrll void *dino_vaddr(void *, bus_space_handle_t);
174fdfdea60Sskrll paddr_t dino_mmap(void *, bus_addr_t, off_t, int, int);
175fdfdea60Sskrll
176fdfdea60Sskrll uint8_t dino_r1(void *, bus_space_handle_t, bus_size_t);
177fdfdea60Sskrll uint16_t dino_r2(void *, bus_space_handle_t, bus_size_t);
178fdfdea60Sskrll uint32_t dino_r4(void *, bus_space_handle_t, bus_size_t);
179fdfdea60Sskrll uint64_t dino_r8(void *, bus_space_handle_t, bus_size_t);
180fdfdea60Sskrll void dino_w1(void *, bus_space_handle_t, bus_size_t, uint8_t);
181fdfdea60Sskrll void dino_w2(void *, bus_space_handle_t, bus_size_t, uint16_t);
182fdfdea60Sskrll void dino_w4(void *, bus_space_handle_t, bus_size_t, uint32_t);
183fdfdea60Sskrll void dino_w8(void *, bus_space_handle_t, bus_size_t, uint64_t);
184fdfdea60Sskrll void dino_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t);
185fdfdea60Sskrll void dino_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t);
186fdfdea60Sskrll void dino_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t);
187fdfdea60Sskrll void dino_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t);
188fdfdea60Sskrll void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
189fdfdea60Sskrll bus_size_t);
190fdfdea60Sskrll void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
191fdfdea60Sskrll bus_size_t);
192fdfdea60Sskrll void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
193fdfdea60Sskrll bus_size_t);
194fdfdea60Sskrll void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
195fdfdea60Sskrll bus_size_t);
196fdfdea60Sskrll void dino_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t);
197fdfdea60Sskrll void dino_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t);
198fdfdea60Sskrll void dino_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t);
199fdfdea60Sskrll void dino_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t);
200fdfdea60Sskrll void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
201fdfdea60Sskrll bus_size_t);
202fdfdea60Sskrll void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
203fdfdea60Sskrll bus_size_t);
204fdfdea60Sskrll void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
205fdfdea60Sskrll bus_size_t);
206fdfdea60Sskrll void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
207fdfdea60Sskrll bus_size_t);
208fdfdea60Sskrll void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
209fdfdea60Sskrll bus_size_t);
210fdfdea60Sskrll void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
211fdfdea60Sskrll bus_size_t);
212fdfdea60Sskrll void dino_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t);
213fdfdea60Sskrll void dino_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t);
214fdfdea60Sskrll void dino_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t);
215fdfdea60Sskrll void dino_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t);
216fdfdea60Sskrll void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
217fdfdea60Sskrll bus_size_t);
218fdfdea60Sskrll void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
219fdfdea60Sskrll bus_size_t);
220fdfdea60Sskrll void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
221fdfdea60Sskrll bus_size_t);
222fdfdea60Sskrll void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
223fdfdea60Sskrll bus_size_t);
224fdfdea60Sskrll void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
225fdfdea60Sskrll bus_size_t);
226fdfdea60Sskrll void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
227fdfdea60Sskrll bus_size_t);
228fdfdea60Sskrll void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
229fdfdea60Sskrll bus_size_t);
230fdfdea60Sskrll void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
231fdfdea60Sskrll bus_size_t);
232fdfdea60Sskrll void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
233fdfdea60Sskrll bus_size_t);
234fdfdea60Sskrll void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
235fdfdea60Sskrll bus_size_t);
236fdfdea60Sskrll void dino_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t);
237fdfdea60Sskrll void dino_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t);
238fdfdea60Sskrll void dino_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t);
239fdfdea60Sskrll void dino_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t);
240fdfdea60Sskrll void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
241fdfdea60Sskrll bus_size_t, bus_size_t);
242fdfdea60Sskrll void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
243fdfdea60Sskrll bus_size_t, bus_size_t);
244fdfdea60Sskrll void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
245fdfdea60Sskrll bus_size_t, bus_size_t);
246fdfdea60Sskrll void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
247fdfdea60Sskrll bus_size_t, bus_size_t);
248fdfdea60Sskrll int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int,
249fdfdea60Sskrll bus_dmamap_t *);
250fdfdea60Sskrll void dino_dmamap_destroy(void *, bus_dmamap_t);
251fdfdea60Sskrll int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, struct proc *,
252fdfdea60Sskrll int);
253fdfdea60Sskrll int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int);
254fdfdea60Sskrll int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int);
255fdfdea60Sskrll int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int,
256fdfdea60Sskrll bus_size_t, int);
257fdfdea60Sskrll void dino_dmamap_unload(void *, bus_dmamap_t);
258fdfdea60Sskrll void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int);
259fdfdea60Sskrll int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t,
260fdfdea60Sskrll bus_dma_segment_t *, int, int *, int);
261fdfdea60Sskrll void dino_dmamem_free(void *, bus_dma_segment_t *, int);
262fdfdea60Sskrll int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, void **, int);
263fdfdea60Sskrll void dino_dmamem_unmap(void *, void *, size_t);
264fdfdea60Sskrll paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int);
265fdfdea60Sskrll
266fdfdea60Sskrll
267fdfdea60Sskrll void
dino_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)268fdfdea60Sskrll dino_attach_hook(device_t parent, device_t self,
269fdfdea60Sskrll struct pcibus_attach_args *pba)
270fdfdea60Sskrll {
271fdfdea60Sskrll struct dino_softc *sc = pba->pba_pc->_cookie;
272fdfdea60Sskrll
273fdfdea60Sskrll /*
274fdfdea60Sskrll * The firmware enables only devices that are needed for booting.
275fdfdea60Sskrll * So other devices will fail to map PCI MEM / IO when they attach.
276fdfdea60Sskrll * Therefore we recursively walk all buses to simply enable everything.
277fdfdea60Sskrll */
278fdfdea60Sskrll dino_enable_bus(sc, 0);
279fdfdea60Sskrll }
280fdfdea60Sskrll
281fdfdea60Sskrll void
dino_enable_bus(struct dino_softc * sc,int bus)282fdfdea60Sskrll dino_enable_bus(struct dino_softc *sc, int bus)
283fdfdea60Sskrll {
284fdfdea60Sskrll int func;
285fdfdea60Sskrll int dev;
286fdfdea60Sskrll pcitag_t tag;
287fdfdea60Sskrll pcireg_t data;
288fdfdea60Sskrll pcireg_t class;
289fdfdea60Sskrll
290fdfdea60Sskrll for (dev = 0; dev < 32; dev++) {
291fdfdea60Sskrll tag = dino_make_tag(sc, bus, dev, 0);
292fdfdea60Sskrll if (tag != -1 && dino_conf_read(sc, tag, 0) != 0xffffffff) {
293fdfdea60Sskrll for (func = 0; func < 8; func++) {
294fdfdea60Sskrll tag = dino_make_tag(sc, bus, dev, func);
295fdfdea60Sskrll if (dino_conf_read(sc, tag, 0) != 0xffffffff) {
296fdfdea60Sskrll data = dino_conf_read(sc, tag,
297fdfdea60Sskrll PCI_COMMAND_STATUS_REG);
298fdfdea60Sskrll dino_conf_write(sc, tag,
299fdfdea60Sskrll PCI_COMMAND_STATUS_REG,
300fdfdea60Sskrll PCI_COMMAND_IO_ENABLE |
301fdfdea60Sskrll PCI_COMMAND_MEM_ENABLE |
302fdfdea60Sskrll PCI_COMMAND_MASTER_ENABLE | data);
303fdfdea60Sskrll }
304fdfdea60Sskrll }
305fdfdea60Sskrll class = dino_conf_read(sc, tag, PCI_CLASS_REG);
306fdfdea60Sskrll if (PCI_CLASS(class) == PCI_CLASS_BRIDGE &&
307fdfdea60Sskrll PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)
308fdfdea60Sskrll dino_enable_bus(sc, bus + 1);
309fdfdea60Sskrll }
310fdfdea60Sskrll }
311fdfdea60Sskrll }
312fdfdea60Sskrll
313fdfdea60Sskrll int
dino_maxdevs(void * v,int bus)314fdfdea60Sskrll dino_maxdevs(void *v, int bus)
315fdfdea60Sskrll {
316fdfdea60Sskrll return 32;
317fdfdea60Sskrll }
318fdfdea60Sskrll
319fdfdea60Sskrll pcitag_t
dino_make_tag(void * v,int bus,int dev,int func)320fdfdea60Sskrll dino_make_tag(void *v, int bus, int dev, int func)
321fdfdea60Sskrll {
322fdfdea60Sskrll if (bus > 255 || dev > 31 || func > 7)
323fdfdea60Sskrll panic("dino_make_tag: bad request");
324fdfdea60Sskrll
325fdfdea60Sskrll return (bus << 16) | (dev << 11) | (func << 8);
326fdfdea60Sskrll }
327fdfdea60Sskrll
328fdfdea60Sskrll void
dino_decompose_tag(void * v,pcitag_t tag,int * bus,int * dev,int * func)329fdfdea60Sskrll dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func)
330fdfdea60Sskrll {
331fdfdea60Sskrll *bus = (tag >> 16) & 0xff;
332fdfdea60Sskrll *dev = (tag >> 11) & 0x1f;
333fdfdea60Sskrll *func= (tag >> 8) & 0x07;
334fdfdea60Sskrll }
335fdfdea60Sskrll
336fdfdea60Sskrll pcireg_t
dino_conf_read(void * v,pcitag_t tag,int reg)337fdfdea60Sskrll dino_conf_read(void *v, pcitag_t tag, int reg)
338fdfdea60Sskrll {
339fdfdea60Sskrll struct dino_softc *sc = v;
340fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
341fdfdea60Sskrll pcireg_t data;
342fdfdea60Sskrll uint32_t pamr;
343fdfdea60Sskrll
34499886603Smsaitoh if ((unsigned int)reg >= PCI_CONF_SIZE)
34599886603Smsaitoh return (pcireg_t) -1;
34699886603Smsaitoh
34748cc7d4eSmacallan /*
34848cc7d4eSmacallan * XXX
3491fe4d70aSmacallan * thus sayeth the Dino manual:
3501fe4d70aSmacallan * 7.7.1 Generating PCI Special Cycles thru PA I/O Space
3511fe4d70aSmacallan * When the PCI_CONFIG_ADDR registers BUS_NUM is the equal to the
3521fe4d70aSmacallan * DINO’s bus number, 8’h00, DEV_NUM and Function fields are all ones,
3531fe4d70aSmacallan * and the REG_NUM field is all zeros the next write to PCI_CONFIG_DATA
3541fe4d70aSmacallan * register will generate a special cycle on DINO’s PCI bus. If the
3551fe4d70aSmacallan * BUS_NUM field does not equal DINO bus number then a type 1
3561fe4d70aSmacallan * transaction will be forwarded to PCI as described above.
3571fe4d70aSmacallan * Note: Dino is using a legal PCI configuration address to generate a
3581fe4d70aSmacallan * PCI special cycle. System firmware and software should not attempt
3591fe4d70aSmacallan * to read or write to this configuration address when walking the
3601fe4d70aSmacallan * PCI bus through configuration address space.
36148cc7d4eSmacallan */
3623255e09eSskrll if ((tag & 0xff00) == 0xff00)
3633255e09eSskrll return -1;
36448cc7d4eSmacallan
365fdfdea60Sskrll /* fix arbitration errata by disabling all pci devs on config read */
366fdfdea60Sskrll pamr = r->pamr;
367fdfdea60Sskrll r->pamr = 0;
368fdfdea60Sskrll
369fdfdea60Sskrll r->pci_addr = tag | reg;
370fdfdea60Sskrll data = r->pci_conf_data;
371fdfdea60Sskrll
372fdfdea60Sskrll /* restore arbitration */
373fdfdea60Sskrll r->pamr = pamr;
374fdfdea60Sskrll
375fdfdea60Sskrll return le32toh(data);
376fdfdea60Sskrll }
377fdfdea60Sskrll
378fdfdea60Sskrll void
dino_conf_write(void * v,pcitag_t tag,int reg,pcireg_t data)379fdfdea60Sskrll dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
380fdfdea60Sskrll {
381fdfdea60Sskrll struct dino_softc *sc = v;
382fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
383fdfdea60Sskrll uint32_t pamr;
384fdfdea60Sskrll
38599886603Smsaitoh if ((unsigned int)reg >= PCI_CONF_SIZE)
38699886603Smsaitoh return;
38799886603Smsaitoh
38848cc7d4eSmacallan /*
3891fe4d70aSmacallan * don't try to access dev 1f / func 7, see comment in dino_conf_read()
39048cc7d4eSmacallan */
39148cc7d4eSmacallan if ((tag & 0xff00) == 0xff00) return;
39248cc7d4eSmacallan
393fdfdea60Sskrll /* fix arbitration errata by disabling all pci devs on config read */
394fdfdea60Sskrll pamr = r->pamr;
395fdfdea60Sskrll r->pamr = 0;
396fdfdea60Sskrll
397fdfdea60Sskrll r->pci_addr = tag | reg;
398fdfdea60Sskrll r->pci_conf_data = htole32(data);
399fdfdea60Sskrll
400fdfdea60Sskrll /* fix coalescing config and io writes by interleaving w/ a read */
401fdfdea60Sskrll r->pci_addr = tag | PCI_ID_REG;
402fdfdea60Sskrll (void)r->pci_conf_data;
403fdfdea60Sskrll
404fdfdea60Sskrll /* restore arbitration */
405fdfdea60Sskrll r->pamr = pamr;
406fdfdea60Sskrll }
407fdfdea60Sskrll
408fdfdea60Sskrll int
dino_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)409fdfdea60Sskrll dino_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
410fdfdea60Sskrll {
411fdfdea60Sskrll int line = pa->pa_intrline;
412fdfdea60Sskrll
413fdfdea60Sskrll if (line == 0xff)
414fdfdea60Sskrll return 1;
415fdfdea60Sskrll
416fdfdea60Sskrll *ihp = line;
417fdfdea60Sskrll
418fdfdea60Sskrll return 0;
419fdfdea60Sskrll }
420fdfdea60Sskrll
421fdfdea60Sskrll const char *
dino_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)42241f223f1Schristos dino_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
423fdfdea60Sskrll {
42441f223f1Schristos snprintf(buf, len, "irq %ld", ih);
425fdfdea60Sskrll return buf;
426fdfdea60Sskrll }
427fdfdea60Sskrll
428fdfdea60Sskrll extern int cold;
429fdfdea60Sskrll
430fdfdea60Sskrll
431fdfdea60Sskrll void *
dino_intr_establish(void * v,pci_intr_handle_t ih,int pri,int (* handler)(void *),void * arg)432fdfdea60Sskrll dino_intr_establish(void *v, pci_intr_handle_t ih,
433fdfdea60Sskrll int pri, int (*handler)(void *), void *arg)
434fdfdea60Sskrll {
435fdfdea60Sskrll struct dino_softc *sc = v;
436fdfdea60Sskrll
437fdfdea60Sskrll return hppa_intr_establish(pri, handler, arg, &sc->sc_ir, ih);
438fdfdea60Sskrll }
439fdfdea60Sskrll
440fdfdea60Sskrll void
dino_intr_disestablish(void * v,void * cookie)441fdfdea60Sskrll dino_intr_disestablish(void *v, void *cookie)
442fdfdea60Sskrll {
443fdfdea60Sskrll /* XXX Implement me */
444fdfdea60Sskrll }
445fdfdea60Sskrll
446fdfdea60Sskrll
447fdfdea60Sskrll #if NCARDBUS > 0
448fdfdea60Sskrll void *
dino_alloc_parent(device_t self,struct pci_attach_args * pa,int io)449fdfdea60Sskrll dino_alloc_parent(device_t self, struct pci_attach_args *pa, int io)
450fdfdea60Sskrll {
451fdfdea60Sskrll struct dino_softc *sc = pa->pa_pc->_cookie;
452fdfdea60Sskrll struct extent *ex;
453fdfdea60Sskrll bus_space_tag_t tag;
454fdfdea60Sskrll bus_addr_t start;
455fdfdea60Sskrll bus_size_t size;
456fdfdea60Sskrll
457fdfdea60Sskrll if (io) {
458fdfdea60Sskrll ex = sc->sc_ioex;
459fdfdea60Sskrll tag = pa->pa_iot;
460fdfdea60Sskrll start = 0xa000;
461fdfdea60Sskrll size = 0x1000;
462fdfdea60Sskrll } else {
463fdfdea60Sskrll ex = hppa_io_extent;
464fdfdea60Sskrll tag = pa->pa_memt;
465fdfdea60Sskrll start = ex->ex_start; /* XXX or 0xf0800000? */
466fdfdea60Sskrll size = DINO_MEM_CHUNK;
467fdfdea60Sskrll }
468fdfdea60Sskrll
469fdfdea60Sskrll if (extent_alloc_subregion(ex, start, ex->ex_end, size, size,
470fdfdea60Sskrll EX_NOBOUNDARY, EX_NOWAIT, &start))
471fdfdea60Sskrll return NULL;
472fdfdea60Sskrll extent_free(ex, start, size, EX_NOWAIT);
473fdfdea60Sskrll return rbus_new_root_share(tag, ex, start, size, start);
474fdfdea60Sskrll }
475fdfdea60Sskrll #endif
476fdfdea60Sskrll
477fdfdea60Sskrll int
dino_iomap(void * v,bus_addr_t bpa,bus_size_t size,int flags,bus_space_handle_t * bshp)478fdfdea60Sskrll dino_iomap(void *v, bus_addr_t bpa, bus_size_t size,
479fdfdea60Sskrll int flags, bus_space_handle_t *bshp)
480fdfdea60Sskrll {
481fdfdea60Sskrll struct dino_softc *sc = v;
482fdfdea60Sskrll int error;
483fdfdea60Sskrll
484fdfdea60Sskrll if (!(flags & BUS_SPACE_MAP_NOEXTENT) &&
485fdfdea60Sskrll (error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT)))
486fdfdea60Sskrll return error;
487fdfdea60Sskrll
488fdfdea60Sskrll if (bshp)
489fdfdea60Sskrll *bshp = bpa;
490fdfdea60Sskrll
491fdfdea60Sskrll return 0;
492fdfdea60Sskrll }
493fdfdea60Sskrll
494fdfdea60Sskrll int
dino_memmap(void * v,bus_addr_t bpa,bus_size_t size,int flags,bus_space_handle_t * bshp)495fdfdea60Sskrll dino_memmap(void *v, bus_addr_t bpa, bus_size_t size,
496fdfdea60Sskrll int flags, bus_space_handle_t *bshp)
497fdfdea60Sskrll {
498fdfdea60Sskrll struct dino_softc *sc = v;
499fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
500fdfdea60Sskrll uint32_t reg;
501fdfdea60Sskrll int error;
502fdfdea60Sskrll
503fdfdea60Sskrll reg = r->io_addr_en;
504fdfdea60Sskrll reg |= 1 << ((bpa >> 23) & 0x1f);
505fdfdea60Sskrll #ifdef DEBUG
506fdfdea60Sskrll if (reg & 0x80000001)
507fdfdea60Sskrll panic("mapping outside the mem extent range");
508fdfdea60Sskrll #endif
509fdfdea60Sskrll if ((error = bus_space_map(sc->sc_bt, bpa, size, flags, bshp)))
510fdfdea60Sskrll return error;
511fdfdea60Sskrll ++sc->sc_memrefcount[((bpa >> 23) & 0x1f)];
512fdfdea60Sskrll /* map into the upper bus space, if not yet mapped this 8M */
513fdfdea60Sskrll if (reg != r->io_addr_en)
514fdfdea60Sskrll r->io_addr_en = reg;
515fdfdea60Sskrll return 0;
516fdfdea60Sskrll }
517fdfdea60Sskrll
518fdfdea60Sskrll int
dino_subregion(void * v,bus_space_handle_t bsh,bus_size_t offset,bus_size_t size,bus_space_handle_t * nbshp)519fdfdea60Sskrll dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset,
520fdfdea60Sskrll bus_size_t size, bus_space_handle_t *nbshp)
521fdfdea60Sskrll {
522fdfdea60Sskrll *nbshp = bsh + offset;
523fdfdea60Sskrll return 0;
524fdfdea60Sskrll }
525fdfdea60Sskrll
526fdfdea60Sskrll int
dino_ioalloc(void * v,bus_addr_t rstart,bus_addr_t rend,bus_size_t size,bus_size_t align,bus_size_t boundary,int flags,bus_addr_t * addrp,bus_space_handle_t * bshp)527fdfdea60Sskrll dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
528fdfdea60Sskrll bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp,
529fdfdea60Sskrll bus_space_handle_t *bshp)
530fdfdea60Sskrll {
531fdfdea60Sskrll struct dino_softc *sc = v;
532fdfdea60Sskrll struct extent *ex = sc->sc_ioex;
533fdfdea60Sskrll bus_addr_t bpa;
534fdfdea60Sskrll int error;
535fdfdea60Sskrll
536fdfdea60Sskrll if (rstart < ex->ex_start || rend > ex->ex_end)
537fdfdea60Sskrll panic("dino_ioalloc: bad region start/end");
538fdfdea60Sskrll
539fdfdea60Sskrll if ((error = extent_alloc_subregion(ex, rstart, rend, size,
540fdfdea60Sskrll align, boundary, EX_NOWAIT, &bpa)))
541fdfdea60Sskrll return error;
542fdfdea60Sskrll
543fdfdea60Sskrll if (addrp)
544fdfdea60Sskrll *addrp = bpa;
545fdfdea60Sskrll if (bshp)
546fdfdea60Sskrll *bshp = bpa;
547fdfdea60Sskrll
548fdfdea60Sskrll return 0;
549fdfdea60Sskrll }
550fdfdea60Sskrll
551fdfdea60Sskrll int
dino_memalloc(void * v,bus_addr_t rstart,bus_addr_t rend,bus_size_t size,bus_size_t align,bus_size_t boundary,int flags,bus_addr_t * addrp,bus_space_handle_t * bshp)552fdfdea60Sskrll dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
553fdfdea60Sskrll bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp,
554fdfdea60Sskrll bus_space_handle_t *bshp)
555fdfdea60Sskrll {
556fdfdea60Sskrll struct dino_softc *sc = v;
557fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
558fdfdea60Sskrll uint32_t reg;
559fdfdea60Sskrll int i, error;
560fdfdea60Sskrll
561fdfdea60Sskrll /*
562fdfdea60Sskrll * Allow allocation only when PCI MEM is already mapped.
563fdfdea60Sskrll * Needed to avoid allocation of I/O space used by devices that
564fdfdea60Sskrll * have no driver in the current kernel.
565fdfdea60Sskrll * Dino can map PCI MEM in the range 0xf0800000..0xff800000 only.
566fdfdea60Sskrll */
567fdfdea60Sskrll reg = r->io_addr_en;
568fdfdea60Sskrll if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0)
569fdfdea60Sskrll return -1;
570fdfdea60Sskrll /* Find used PCI MEM and narrow allocateble region down to it. */
571fdfdea60Sskrll for (i = 1; i < 31; i++)
572fdfdea60Sskrll if ((reg & 1 << i) != 0) {
573fdfdea60Sskrll rstart = HPPA_IOSPACE | i << 23;
574fdfdea60Sskrll rend = (HPPA_IOSPACE | (i + 1) << 23) - 1;
575fdfdea60Sskrll break;
576fdfdea60Sskrll }
577fdfdea60Sskrll if ((error = bus_space_alloc(sc->sc_bt, rstart, rend, size, align,
578fdfdea60Sskrll boundary, flags, addrp, bshp)))
579fdfdea60Sskrll return error;
580fdfdea60Sskrll ++sc->sc_memrefcount[((*bshp >> 23) & 0x1f)];
581fdfdea60Sskrll return 0;
582fdfdea60Sskrll }
583fdfdea60Sskrll
584fdfdea60Sskrll void
dino_unmap(void * v,bus_space_handle_t bsh,bus_size_t size)585fdfdea60Sskrll dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size)
586fdfdea60Sskrll {
587fdfdea60Sskrll struct dino_softc *sc = v;
588fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
589fdfdea60Sskrll
590fdfdea60Sskrll if (bsh & HPPA_IOSPACE) {
591fdfdea60Sskrll bus_space_unmap(sc->sc_bt, bsh, size);
592fdfdea60Sskrll if (--sc->sc_memrefcount[((bsh >> 23) & 0x1f)] == 0)
593fdfdea60Sskrll /* Unmap the upper PCI MEM space. */
594fdfdea60Sskrll r->io_addr_en &= ~(1 << ((bsh >> 23) & 0x1f));
595fdfdea60Sskrll } else {
596fdfdea60Sskrll /* XXX gotta follow the BUS_SPACE_MAP_NOEXTENT flag */
597fdfdea60Sskrll if (extent_free(sc->sc_ioex, bsh, size, EX_NOWAIT))
598fdfdea60Sskrll printf("dino_unmap: ps 0x%lx, size 0x%lx\n"
599fdfdea60Sskrll "dino_unmap: can't free region\n", bsh, size);
600fdfdea60Sskrll }
601fdfdea60Sskrll }
602fdfdea60Sskrll
603fdfdea60Sskrll void
dino_free(void * v,bus_space_handle_t bh,bus_size_t size)604fdfdea60Sskrll dino_free(void *v, bus_space_handle_t bh, bus_size_t size)
605fdfdea60Sskrll {
606fdfdea60Sskrll /* should be enough */
607fdfdea60Sskrll dino_unmap(v, bh, size);
608fdfdea60Sskrll }
609fdfdea60Sskrll
610fdfdea60Sskrll void
dino_barrier(void * v,bus_space_handle_t h,bus_size_t o,bus_size_t l,int op)611fdfdea60Sskrll dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op)
612fdfdea60Sskrll {
613fdfdea60Sskrll sync_caches();
614fdfdea60Sskrll }
615fdfdea60Sskrll
616fdfdea60Sskrll void*
dino_vaddr(void * v,bus_space_handle_t h)617fdfdea60Sskrll dino_vaddr(void *v, bus_space_handle_t h)
618fdfdea60Sskrll {
619fdfdea60Sskrll struct dino_softc *sc = v;
620fdfdea60Sskrll
621fdfdea60Sskrll return bus_space_vaddr(sc->sc_bt, h);
622fdfdea60Sskrll }
623fdfdea60Sskrll
624fdfdea60Sskrll paddr_t
dino_mmap(void * v,bus_addr_t addr,off_t off,int prot,int flags)625fdfdea60Sskrll dino_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags)
626fdfdea60Sskrll {
6274ca7228cSmacallan return btop(addr + off);
628fdfdea60Sskrll }
629fdfdea60Sskrll
630fdfdea60Sskrll uint8_t
dino_r1(void * v,bus_space_handle_t h,bus_size_t o)631fdfdea60Sskrll dino_r1(void *v, bus_space_handle_t h, bus_size_t o)
632fdfdea60Sskrll {
633fdfdea60Sskrll h += o;
634fdfdea60Sskrll if (h & HPPA_IOSPACE)
635fdfdea60Sskrll return *(volatile uint8_t *)h;
636fdfdea60Sskrll else {
637fdfdea60Sskrll struct dino_softc *sc = v;
638fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
639fdfdea60Sskrll
640fdfdea60Sskrll r->pci_addr = h;
641fdfdea60Sskrll return *((volatile uint8_t *)&r->pci_io_data + (h & 3));
642fdfdea60Sskrll }
643fdfdea60Sskrll }
644fdfdea60Sskrll
645fdfdea60Sskrll uint16_t
dino_r2(void * v,bus_space_handle_t h,bus_size_t o)646fdfdea60Sskrll dino_r2(void *v, bus_space_handle_t h, bus_size_t o)
647fdfdea60Sskrll {
648fdfdea60Sskrll volatile uint16_t *p;
649fdfdea60Sskrll
650fdfdea60Sskrll h += o;
651fdfdea60Sskrll if (h & HPPA_IOSPACE)
652fdfdea60Sskrll p = (volatile uint16_t *)h;
653fdfdea60Sskrll else {
654fdfdea60Sskrll struct dino_softc *sc = v;
655fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
656fdfdea60Sskrll
657fdfdea60Sskrll r->pci_addr = h;
658fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
659fdfdea60Sskrll if (h & 2)
660fdfdea60Sskrll p++;
661fdfdea60Sskrll }
662fdfdea60Sskrll return le16toh(*p);
663fdfdea60Sskrll }
664fdfdea60Sskrll
665fdfdea60Sskrll uint32_t
dino_r4(void * v,bus_space_handle_t h,bus_size_t o)666fdfdea60Sskrll dino_r4(void *v, bus_space_handle_t h, bus_size_t o)
667fdfdea60Sskrll {
668fdfdea60Sskrll uint32_t data;
669fdfdea60Sskrll
670fdfdea60Sskrll h += o;
671fdfdea60Sskrll if (h & HPPA_IOSPACE)
672fdfdea60Sskrll data = *(volatile uint32_t *)h;
673fdfdea60Sskrll else {
674fdfdea60Sskrll struct dino_softc *sc = v;
675fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
676fdfdea60Sskrll
677fdfdea60Sskrll r->pci_addr = h;
678fdfdea60Sskrll data = r->pci_io_data;
679fdfdea60Sskrll }
680fdfdea60Sskrll
681fdfdea60Sskrll return le32toh(data);
682fdfdea60Sskrll }
683fdfdea60Sskrll
684fdfdea60Sskrll uint64_t
dino_r8(void * v,bus_space_handle_t h,bus_size_t o)685fdfdea60Sskrll dino_r8(void *v, bus_space_handle_t h, bus_size_t o)
686fdfdea60Sskrll {
687fdfdea60Sskrll uint64_t data;
688fdfdea60Sskrll
689fdfdea60Sskrll h += o;
690fdfdea60Sskrll if (h & HPPA_IOSPACE)
691fdfdea60Sskrll data = *(volatile uint64_t *)h;
692fdfdea60Sskrll else
693fdfdea60Sskrll panic("dino_r8: not implemented");
694fdfdea60Sskrll
695fdfdea60Sskrll return le64toh(data);
696fdfdea60Sskrll }
697fdfdea60Sskrll
698fdfdea60Sskrll void
dino_w1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t vv)699fdfdea60Sskrll dino_w1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv)
700fdfdea60Sskrll {
701fdfdea60Sskrll h += o;
702fdfdea60Sskrll if (h & HPPA_IOSPACE)
703fdfdea60Sskrll *(volatile uint8_t *)h = vv;
704fdfdea60Sskrll else {
705fdfdea60Sskrll struct dino_softc *sc = v;
706fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
707fdfdea60Sskrll
708fdfdea60Sskrll r->pci_addr = h;
709fdfdea60Sskrll *((volatile uint8_t *)&r->pci_io_data + (h & 3)) = vv;
710fdfdea60Sskrll }
711fdfdea60Sskrll }
712fdfdea60Sskrll
713fdfdea60Sskrll void
dino_w2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t vv)714fdfdea60Sskrll dino_w2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv)
715fdfdea60Sskrll {
716fdfdea60Sskrll volatile uint16_t *p;
717fdfdea60Sskrll
718fdfdea60Sskrll h += o;
719fdfdea60Sskrll if (h & HPPA_IOSPACE)
720fdfdea60Sskrll p = (volatile uint16_t *)h;
721fdfdea60Sskrll else {
722fdfdea60Sskrll struct dino_softc *sc = v;
723fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
724fdfdea60Sskrll
725fdfdea60Sskrll r->pci_addr = h;
726fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
727fdfdea60Sskrll if (h & 2)
728fdfdea60Sskrll p++;
729fdfdea60Sskrll }
730fdfdea60Sskrll
731fdfdea60Sskrll *p = htole16(vv);
732fdfdea60Sskrll }
733fdfdea60Sskrll
734fdfdea60Sskrll void
dino_w4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t vv)735fdfdea60Sskrll dino_w4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv)
736fdfdea60Sskrll {
737fdfdea60Sskrll h += o;
738fdfdea60Sskrll vv = htole32(vv);
739fdfdea60Sskrll if (h & HPPA_IOSPACE)
740fdfdea60Sskrll *(volatile uint32_t *)h = vv;
741fdfdea60Sskrll else {
742fdfdea60Sskrll struct dino_softc *sc = v;
743fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
744fdfdea60Sskrll
745fdfdea60Sskrll r->pci_addr = h;
746fdfdea60Sskrll r->pci_io_data = vv;
747fdfdea60Sskrll }
748fdfdea60Sskrll }
749fdfdea60Sskrll
750fdfdea60Sskrll void
dino_w8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t vv)751fdfdea60Sskrll dino_w8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv)
752fdfdea60Sskrll {
753fdfdea60Sskrll h += o;
754fdfdea60Sskrll if (h & HPPA_IOSPACE)
755fdfdea60Sskrll *(volatile uint64_t *)h = htole64(vv);
756fdfdea60Sskrll else
757fdfdea60Sskrll panic("dino_w8: not implemented");
758fdfdea60Sskrll }
759fdfdea60Sskrll
760fdfdea60Sskrll
761fdfdea60Sskrll void
dino_rm_1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t * a,bus_size_t c)762fdfdea60Sskrll dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c)
763fdfdea60Sskrll {
764fdfdea60Sskrll volatile uint8_t *p;
765fdfdea60Sskrll
766fdfdea60Sskrll h += o;
767fdfdea60Sskrll if (h & HPPA_IOSPACE)
768fdfdea60Sskrll p = (volatile uint8_t *)h;
769fdfdea60Sskrll else {
770fdfdea60Sskrll struct dino_softc *sc = v;
771fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
772fdfdea60Sskrll
773fdfdea60Sskrll r->pci_addr = h;
774fdfdea60Sskrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
775fdfdea60Sskrll }
776fdfdea60Sskrll
777fdfdea60Sskrll while (c--)
778fdfdea60Sskrll *a++ = *p;
779fdfdea60Sskrll }
780fdfdea60Sskrll
781fdfdea60Sskrll void
dino_rm_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t * a,bus_size_t c)782fdfdea60Sskrll dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c)
783fdfdea60Sskrll {
784fdfdea60Sskrll volatile uint16_t *p;
785fdfdea60Sskrll
786fdfdea60Sskrll h += o;
787fdfdea60Sskrll if (h & HPPA_IOSPACE)
788fdfdea60Sskrll p = (volatile uint16_t *)h;
789fdfdea60Sskrll else {
790fdfdea60Sskrll struct dino_softc *sc = v;
791fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
792fdfdea60Sskrll
793fdfdea60Sskrll r->pci_addr = h;
794fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
795fdfdea60Sskrll if (h & 2)
796fdfdea60Sskrll p++;
797fdfdea60Sskrll }
798fdfdea60Sskrll
799fdfdea60Sskrll while (c--)
800fdfdea60Sskrll *a++ = le16toh(*p);
801fdfdea60Sskrll }
802fdfdea60Sskrll
803fdfdea60Sskrll void
dino_rm_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t * a,bus_size_t c)804fdfdea60Sskrll dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c)
805fdfdea60Sskrll {
806fdfdea60Sskrll volatile uint32_t *p;
807fdfdea60Sskrll
808fdfdea60Sskrll h += o;
809fdfdea60Sskrll if (h & HPPA_IOSPACE)
810fdfdea60Sskrll p = (volatile uint32_t *)h;
811fdfdea60Sskrll else {
812fdfdea60Sskrll struct dino_softc *sc = v;
813fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
814fdfdea60Sskrll
815fdfdea60Sskrll r->pci_addr = h;
816fdfdea60Sskrll p = (volatile uint32_t *)&r->pci_io_data;
817fdfdea60Sskrll }
818fdfdea60Sskrll
819fdfdea60Sskrll while (c--)
820fdfdea60Sskrll *a++ = le32toh(*p);
821fdfdea60Sskrll }
822fdfdea60Sskrll
823fdfdea60Sskrll void
dino_rm_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t * a,bus_size_t c)824fdfdea60Sskrll dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c)
825fdfdea60Sskrll {
826fdfdea60Sskrll panic("dino_rm_8: not implemented");
827fdfdea60Sskrll }
828fdfdea60Sskrll
829fdfdea60Sskrll void
dino_wm_1(void * v,bus_space_handle_t h,bus_size_t o,const uint8_t * a,bus_size_t c)830fdfdea60Sskrll dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c)
831fdfdea60Sskrll {
832fdfdea60Sskrll volatile uint8_t *p;
833fdfdea60Sskrll
834fdfdea60Sskrll h += o;
835fdfdea60Sskrll if (h & HPPA_IOSPACE)
836fdfdea60Sskrll p = (volatile uint8_t *)h;
837fdfdea60Sskrll else {
838fdfdea60Sskrll struct dino_softc *sc = v;
839fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
840fdfdea60Sskrll
841fdfdea60Sskrll r->pci_addr = h;
842fdfdea60Sskrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
843fdfdea60Sskrll }
844fdfdea60Sskrll
845fdfdea60Sskrll while (c--)
846fdfdea60Sskrll *p = *a++;
847fdfdea60Sskrll }
848fdfdea60Sskrll
849fdfdea60Sskrll void
dino_wm_2(void * v,bus_space_handle_t h,bus_size_t o,const uint16_t * a,bus_size_t c)850fdfdea60Sskrll dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c)
851fdfdea60Sskrll {
852fdfdea60Sskrll volatile uint16_t *p;
853fdfdea60Sskrll
854fdfdea60Sskrll h += o;
855fdfdea60Sskrll if (h & HPPA_IOSPACE)
856fdfdea60Sskrll p = (volatile uint16_t *)h;
857fdfdea60Sskrll else {
858fdfdea60Sskrll struct dino_softc *sc = v;
859fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
860fdfdea60Sskrll
861fdfdea60Sskrll r->pci_addr = h;
862fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
863fdfdea60Sskrll if (h & 2)
864fdfdea60Sskrll p++;
865fdfdea60Sskrll }
866fdfdea60Sskrll
867fdfdea60Sskrll while (c--)
868fdfdea60Sskrll *p = htole16(*a++);
869fdfdea60Sskrll }
870fdfdea60Sskrll
871fdfdea60Sskrll void
dino_wm_4(void * v,bus_space_handle_t h,bus_size_t o,const uint32_t * a,bus_size_t c)872fdfdea60Sskrll dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c)
873fdfdea60Sskrll {
874fdfdea60Sskrll volatile uint32_t *p;
875fdfdea60Sskrll
876fdfdea60Sskrll h += o;
877fdfdea60Sskrll if (h & HPPA_IOSPACE)
878fdfdea60Sskrll p = (volatile uint32_t *)h;
879fdfdea60Sskrll else {
880fdfdea60Sskrll struct dino_softc *sc = v;
881fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
882fdfdea60Sskrll
883fdfdea60Sskrll r->pci_addr = h;
884fdfdea60Sskrll p = (volatile uint32_t *)&r->pci_io_data;
885fdfdea60Sskrll }
886fdfdea60Sskrll
887fdfdea60Sskrll while (c--)
888fdfdea60Sskrll *p = htole32(*a++);
889fdfdea60Sskrll }
890fdfdea60Sskrll
891fdfdea60Sskrll void
dino_wm_8(void * v,bus_space_handle_t h,bus_size_t o,const uint64_t * a,bus_size_t c)892fdfdea60Sskrll dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c)
893fdfdea60Sskrll {
894fdfdea60Sskrll panic("dino_wm_8: not implemented");
895fdfdea60Sskrll }
896fdfdea60Sskrll
897fdfdea60Sskrll void
dino_sm_1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t vv,bus_size_t c)898fdfdea60Sskrll dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c)
899fdfdea60Sskrll {
900fdfdea60Sskrll volatile uint8_t *p;
901fdfdea60Sskrll
902fdfdea60Sskrll h += o;
903fdfdea60Sskrll if (h & HPPA_IOSPACE)
904fdfdea60Sskrll p = (volatile uint8_t *)h;
905fdfdea60Sskrll else {
906fdfdea60Sskrll struct dino_softc *sc = v;
907fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
908fdfdea60Sskrll
909fdfdea60Sskrll r->pci_addr = h;
910fdfdea60Sskrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
911fdfdea60Sskrll }
912fdfdea60Sskrll
913fdfdea60Sskrll while (c--)
914fdfdea60Sskrll *p = vv;
915fdfdea60Sskrll }
916fdfdea60Sskrll
917fdfdea60Sskrll void
dino_sm_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t vv,bus_size_t c)918fdfdea60Sskrll dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c)
919fdfdea60Sskrll {
920fdfdea60Sskrll volatile uint16_t *p;
921fdfdea60Sskrll
922fdfdea60Sskrll h += o;
923fdfdea60Sskrll if (h & HPPA_IOSPACE)
924fdfdea60Sskrll p = (volatile uint16_t *)h;
925fdfdea60Sskrll else {
926fdfdea60Sskrll struct dino_softc *sc = v;
927fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
928fdfdea60Sskrll
929fdfdea60Sskrll r->pci_addr = h;
930fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
931fdfdea60Sskrll if (h & 2)
932fdfdea60Sskrll p++;
933fdfdea60Sskrll }
934fdfdea60Sskrll
935fdfdea60Sskrll while (c--)
936fdfdea60Sskrll *p = htole16(vv);
937fdfdea60Sskrll }
938fdfdea60Sskrll
939fdfdea60Sskrll void
dino_sm_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t vv,bus_size_t c)940fdfdea60Sskrll dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c)
941fdfdea60Sskrll {
942fdfdea60Sskrll volatile uint32_t *p;
943fdfdea60Sskrll
944fdfdea60Sskrll h += o;
945fdfdea60Sskrll if (h & HPPA_IOSPACE)
946fdfdea60Sskrll p = (volatile uint32_t *)h;
947fdfdea60Sskrll else {
948fdfdea60Sskrll struct dino_softc *sc = v;
949fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
950fdfdea60Sskrll
951fdfdea60Sskrll r->pci_addr = h;
952fdfdea60Sskrll p = (volatile uint32_t *)&r->pci_io_data;
953fdfdea60Sskrll }
954fdfdea60Sskrll
955fdfdea60Sskrll while (c--)
956fdfdea60Sskrll *p = htole32(vv);
957fdfdea60Sskrll }
958fdfdea60Sskrll
959fdfdea60Sskrll void
dino_sm_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t vv,bus_size_t c)960fdfdea60Sskrll dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c)
961fdfdea60Sskrll {
962fdfdea60Sskrll panic("dino_sm_8: not implemented");
963fdfdea60Sskrll }
964fdfdea60Sskrll
965fdfdea60Sskrll void
dino_rrm_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t * a,bus_size_t c)966fdfdea60Sskrll dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o,
967fdfdea60Sskrll uint16_t *a, bus_size_t c)
968fdfdea60Sskrll {
969fdfdea60Sskrll volatile uint16_t *p;
970fdfdea60Sskrll
971fdfdea60Sskrll h += o;
972fdfdea60Sskrll if (h & HPPA_IOSPACE)
973fdfdea60Sskrll p = (volatile uint16_t *)h;
974fdfdea60Sskrll else {
975fdfdea60Sskrll struct dino_softc *sc = v;
976fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
977fdfdea60Sskrll
978fdfdea60Sskrll r->pci_addr = h;
979fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
980fdfdea60Sskrll if (h & 2)
981fdfdea60Sskrll p++;
982fdfdea60Sskrll }
983fdfdea60Sskrll
984fdfdea60Sskrll while (c--)
985fdfdea60Sskrll *a++ = *p;
986fdfdea60Sskrll }
987fdfdea60Sskrll
988fdfdea60Sskrll void
dino_rrm_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t * a,bus_size_t c)989fdfdea60Sskrll dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o,
990fdfdea60Sskrll uint32_t *a, bus_size_t c)
991fdfdea60Sskrll {
992fdfdea60Sskrll volatile uint32_t *p;
993fdfdea60Sskrll
994fdfdea60Sskrll h += o;
995fdfdea60Sskrll if (h & HPPA_IOSPACE)
996fdfdea60Sskrll p = (volatile uint32_t *)h;
997fdfdea60Sskrll else {
998fdfdea60Sskrll struct dino_softc *sc = v;
999fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1000fdfdea60Sskrll
1001fdfdea60Sskrll r->pci_addr = h;
1002fdfdea60Sskrll p = (volatile uint32_t *)&r->pci_io_data;
1003fdfdea60Sskrll }
1004fdfdea60Sskrll
1005fdfdea60Sskrll while (c--)
1006fdfdea60Sskrll *a++ = *p;
1007fdfdea60Sskrll }
1008fdfdea60Sskrll
1009fdfdea60Sskrll void
dino_rrm_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t * a,bus_size_t c)1010fdfdea60Sskrll dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o,
1011fdfdea60Sskrll uint64_t *a, bus_size_t c)
1012fdfdea60Sskrll {
1013fdfdea60Sskrll panic("dino_rrm_8: not implemented");
1014fdfdea60Sskrll }
1015fdfdea60Sskrll
1016fdfdea60Sskrll void
dino_wrm_2(void * v,bus_space_handle_t h,bus_size_t o,const uint16_t * a,bus_size_t c)1017fdfdea60Sskrll dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o,
1018fdfdea60Sskrll const uint16_t *a, bus_size_t c)
1019fdfdea60Sskrll {
1020fdfdea60Sskrll volatile uint16_t *p;
1021fdfdea60Sskrll
1022fdfdea60Sskrll h += o;
1023fdfdea60Sskrll if (h & HPPA_IOSPACE)
1024fdfdea60Sskrll p = (volatile uint16_t *)h;
1025fdfdea60Sskrll else {
1026fdfdea60Sskrll struct dino_softc *sc = v;
1027fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1028fdfdea60Sskrll
1029fdfdea60Sskrll r->pci_addr = h;
1030fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
1031fdfdea60Sskrll if (h & 2)
1032fdfdea60Sskrll p++;
1033fdfdea60Sskrll }
1034fdfdea60Sskrll
1035fdfdea60Sskrll while (c--)
1036fdfdea60Sskrll *p = *a++;
1037fdfdea60Sskrll }
1038fdfdea60Sskrll
1039fdfdea60Sskrll void
dino_wrm_4(void * v,bus_space_handle_t h,bus_size_t o,const uint32_t * a,bus_size_t c)1040fdfdea60Sskrll dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o,
1041fdfdea60Sskrll const uint32_t *a, bus_size_t c)
1042fdfdea60Sskrll {
1043fdfdea60Sskrll volatile uint32_t *p;
1044fdfdea60Sskrll
1045fdfdea60Sskrll h += o;
1046fdfdea60Sskrll if (h & HPPA_IOSPACE)
1047fdfdea60Sskrll p = (volatile uint32_t *)h;
1048fdfdea60Sskrll else {
1049fdfdea60Sskrll struct dino_softc *sc = v;
1050fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1051fdfdea60Sskrll
1052fdfdea60Sskrll r->pci_addr = h;
1053fdfdea60Sskrll p = (volatile uint32_t *)&r->pci_io_data;
1054fdfdea60Sskrll }
1055fdfdea60Sskrll
1056fdfdea60Sskrll while (c--)
1057fdfdea60Sskrll *p = *a++;
1058fdfdea60Sskrll }
1059fdfdea60Sskrll
1060fdfdea60Sskrll void
dino_wrm_8(void * v,bus_space_handle_t h,bus_size_t o,const uint64_t * a,bus_size_t c)1061fdfdea60Sskrll dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o,
1062fdfdea60Sskrll const uint64_t *a, bus_size_t c)
1063fdfdea60Sskrll {
1064fdfdea60Sskrll panic("dino_wrm_8: not implemented");
1065fdfdea60Sskrll }
1066fdfdea60Sskrll
1067fdfdea60Sskrll void
dino_rr_1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t * a,bus_size_t c)1068fdfdea60Sskrll dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c)
1069fdfdea60Sskrll {
1070fdfdea60Sskrll volatile uint8_t *p;
1071fdfdea60Sskrll
1072fdfdea60Sskrll h += o;
1073fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1074fdfdea60Sskrll p = (volatile uint8_t *)h;
1075fdfdea60Sskrll while (c--)
1076fdfdea60Sskrll *a++ = *p++;
1077fdfdea60Sskrll } else {
1078fdfdea60Sskrll struct dino_softc *sc = v;
1079fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1080fdfdea60Sskrll
1081fdfdea60Sskrll for (; c--; h++) {
1082fdfdea60Sskrll r->pci_addr = h;
1083fdfdea60Sskrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
1084fdfdea60Sskrll *a++ = *p;
1085fdfdea60Sskrll }
1086fdfdea60Sskrll }
1087fdfdea60Sskrll }
1088fdfdea60Sskrll
1089fdfdea60Sskrll void
dino_rr_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t * a,bus_size_t c)1090fdfdea60Sskrll dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c)
1091fdfdea60Sskrll {
1092fdfdea60Sskrll volatile uint16_t *p, data;
1093fdfdea60Sskrll
1094fdfdea60Sskrll h += o;
1095fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1096fdfdea60Sskrll p = (volatile uint16_t *)h;
1097fdfdea60Sskrll while (c--) {
1098fdfdea60Sskrll data = *p++;
1099fdfdea60Sskrll *a++ = le16toh(data);
1100fdfdea60Sskrll }
1101fdfdea60Sskrll } else {
1102fdfdea60Sskrll struct dino_softc *sc = v;
1103fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1104fdfdea60Sskrll
1105fdfdea60Sskrll for (; c--; h += 2) {
1106fdfdea60Sskrll r->pci_addr = h;
1107fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
1108fdfdea60Sskrll if (h & 2)
1109fdfdea60Sskrll p++;
1110fdfdea60Sskrll data = *p;
1111fdfdea60Sskrll *a++ = le16toh(data);
1112fdfdea60Sskrll }
1113fdfdea60Sskrll }
1114fdfdea60Sskrll }
1115fdfdea60Sskrll
1116fdfdea60Sskrll void
dino_rr_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t * a,bus_size_t c)1117fdfdea60Sskrll dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c)
1118fdfdea60Sskrll {
1119fdfdea60Sskrll volatile uint32_t *p, data;
1120fdfdea60Sskrll
1121fdfdea60Sskrll h += o;
1122fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1123fdfdea60Sskrll p = (volatile uint32_t *)h;
1124fdfdea60Sskrll while (c--) {
1125fdfdea60Sskrll data = *p++;
1126fdfdea60Sskrll *a++ = le32toh(data);
1127fdfdea60Sskrll }
1128fdfdea60Sskrll } else {
1129fdfdea60Sskrll struct dino_softc *sc = v;
1130fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1131fdfdea60Sskrll
1132fdfdea60Sskrll for (; c--; h += 4) {
1133fdfdea60Sskrll r->pci_addr = h;
1134fdfdea60Sskrll data = r->pci_io_data;
1135fdfdea60Sskrll *a++ = le32toh(data);
1136fdfdea60Sskrll }
1137fdfdea60Sskrll }
1138fdfdea60Sskrll }
1139fdfdea60Sskrll
1140fdfdea60Sskrll void
dino_rr_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t * a,bus_size_t c)1141fdfdea60Sskrll dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c)
1142fdfdea60Sskrll {
1143fdfdea60Sskrll panic("dino_rr_8: not implemented");
1144fdfdea60Sskrll }
1145fdfdea60Sskrll
1146fdfdea60Sskrll void
dino_wr_1(void * v,bus_space_handle_t h,bus_size_t o,const uint8_t * a,bus_size_t c)1147fdfdea60Sskrll dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c)
1148fdfdea60Sskrll {
1149fdfdea60Sskrll volatile uint8_t *p;
1150fdfdea60Sskrll
1151fdfdea60Sskrll h += o;
1152fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1153fdfdea60Sskrll p = (volatile uint8_t *)h;
1154fdfdea60Sskrll while (c--)
1155fdfdea60Sskrll *p++ = *a++;
1156fdfdea60Sskrll } else {
1157fdfdea60Sskrll struct dino_softc *sc = v;
1158fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1159fdfdea60Sskrll
1160fdfdea60Sskrll for (; c--; h++) {
1161fdfdea60Sskrll r->pci_addr = h;
1162fdfdea60Sskrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
1163fdfdea60Sskrll *p = *a++;
1164fdfdea60Sskrll }
1165fdfdea60Sskrll }
1166fdfdea60Sskrll }
1167fdfdea60Sskrll
1168fdfdea60Sskrll void
dino_wr_2(void * v,bus_space_handle_t h,bus_size_t o,const uint16_t * a,bus_size_t c)1169fdfdea60Sskrll dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c)
1170fdfdea60Sskrll {
1171fdfdea60Sskrll volatile uint16_t *p, data;
1172fdfdea60Sskrll
1173fdfdea60Sskrll h += o;
1174fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1175fdfdea60Sskrll p = (volatile uint16_t *)h;
1176fdfdea60Sskrll while (c--) {
1177fdfdea60Sskrll data = *a++;
1178fdfdea60Sskrll *p++ = htole16(data);
1179fdfdea60Sskrll }
1180fdfdea60Sskrll } else {
1181fdfdea60Sskrll struct dino_softc *sc = v;
1182fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1183fdfdea60Sskrll
1184fdfdea60Sskrll for (; c--; h += 2) {
1185fdfdea60Sskrll r->pci_addr = h;
1186fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
1187fdfdea60Sskrll if (h & 2)
1188fdfdea60Sskrll p++;
1189fdfdea60Sskrll data = *a++;
1190fdfdea60Sskrll *p = htole16(data);
1191fdfdea60Sskrll }
1192fdfdea60Sskrll }
1193fdfdea60Sskrll }
1194fdfdea60Sskrll
1195fdfdea60Sskrll void
dino_wr_4(void * v,bus_space_handle_t h,bus_size_t o,const uint32_t * a,bus_size_t c)1196fdfdea60Sskrll dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c)
1197fdfdea60Sskrll {
1198fdfdea60Sskrll volatile uint32_t *p, data;
1199fdfdea60Sskrll
1200fdfdea60Sskrll h += o;
1201fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1202fdfdea60Sskrll p = (volatile uint32_t *)h;
1203fdfdea60Sskrll while (c--) {
1204fdfdea60Sskrll data = *a++;
1205fdfdea60Sskrll *p++ = htole32(data);
1206fdfdea60Sskrll }
1207fdfdea60Sskrll } else {
1208fdfdea60Sskrll struct dino_softc *sc = v;
1209fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1210fdfdea60Sskrll
1211fdfdea60Sskrll for (; c--; h += 4) {
1212fdfdea60Sskrll r->pci_addr = h;
1213fdfdea60Sskrll data = *a++;
1214fdfdea60Sskrll r->pci_io_data = htole32(data);
1215fdfdea60Sskrll }
1216fdfdea60Sskrll }
1217fdfdea60Sskrll }
1218fdfdea60Sskrll
1219fdfdea60Sskrll void
dino_wr_8(void * v,bus_space_handle_t h,bus_size_t o,const uint64_t * a,bus_size_t c)1220fdfdea60Sskrll dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c)
1221fdfdea60Sskrll {
1222fdfdea60Sskrll panic("dino_wr_8: not implemented");
1223fdfdea60Sskrll }
1224fdfdea60Sskrll
1225fdfdea60Sskrll void
dino_rrr_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t * a,bus_size_t c)1226fdfdea60Sskrll dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o,
1227fdfdea60Sskrll uint16_t *a, bus_size_t c)
1228fdfdea60Sskrll {
1229fdfdea60Sskrll volatile uint16_t *p;
1230fdfdea60Sskrll
1231fdfdea60Sskrll h += o;
1232fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1233fdfdea60Sskrll p = (volatile uint16_t *)h;
1234fdfdea60Sskrll while (c--)
1235fdfdea60Sskrll *a++ = *p++;
1236fdfdea60Sskrll } else {
1237fdfdea60Sskrll struct dino_softc *sc = v;
1238fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1239fdfdea60Sskrll
1240fdfdea60Sskrll for (; c--; h += 2) {
1241fdfdea60Sskrll r->pci_addr = h;
1242fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
1243fdfdea60Sskrll if (h & 2)
1244fdfdea60Sskrll p++;
1245fdfdea60Sskrll *a++ = *p;
1246fdfdea60Sskrll }
1247fdfdea60Sskrll }
1248fdfdea60Sskrll }
1249fdfdea60Sskrll
1250fdfdea60Sskrll void
dino_rrr_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t * a,bus_size_t c)1251fdfdea60Sskrll dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o,
1252fdfdea60Sskrll uint32_t *a, bus_size_t c)
1253fdfdea60Sskrll {
1254fdfdea60Sskrll volatile uint32_t *p;
1255fdfdea60Sskrll
1256fdfdea60Sskrll h += o;
1257fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1258fdfdea60Sskrll p = (volatile uint32_t *)h;
1259fdfdea60Sskrll while (c--)
1260fdfdea60Sskrll *a++ = *p++;
1261fdfdea60Sskrll } else {
1262fdfdea60Sskrll struct dino_softc *sc = v;
1263fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1264fdfdea60Sskrll
1265fdfdea60Sskrll for (; c--; h += 4) {
1266fdfdea60Sskrll r->pci_addr = h;
1267fdfdea60Sskrll *a++ = r->pci_io_data;
1268fdfdea60Sskrll }
1269fdfdea60Sskrll }
1270fdfdea60Sskrll }
1271fdfdea60Sskrll
1272fdfdea60Sskrll void
dino_rrr_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t * a,bus_size_t c)1273fdfdea60Sskrll dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o,
1274fdfdea60Sskrll uint64_t *a, bus_size_t c)
1275fdfdea60Sskrll {
1276fdfdea60Sskrll panic("dino_rrr_8: not implemented");
1277fdfdea60Sskrll }
1278fdfdea60Sskrll
1279fdfdea60Sskrll void
dino_wrr_2(void * v,bus_space_handle_t h,bus_size_t o,const uint16_t * a,bus_size_t c)1280fdfdea60Sskrll dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o,
1281fdfdea60Sskrll const uint16_t *a, bus_size_t c)
1282fdfdea60Sskrll {
1283fdfdea60Sskrll volatile uint16_t *p;
1284fdfdea60Sskrll
1285fdfdea60Sskrll h += o;
1286fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1287fdfdea60Sskrll p = (volatile uint16_t *)h;
1288fdfdea60Sskrll while (c--)
1289fdfdea60Sskrll *p++ = *a++;
1290fdfdea60Sskrll } else {
1291fdfdea60Sskrll struct dino_softc *sc = v;
1292fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1293fdfdea60Sskrll
1294fdfdea60Sskrll for (; c--; h += 2) {
1295fdfdea60Sskrll r->pci_addr = h;
1296fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
1297fdfdea60Sskrll if (h & 2)
1298fdfdea60Sskrll p++;
1299fdfdea60Sskrll *p = *a++;
1300fdfdea60Sskrll }
1301fdfdea60Sskrll }
1302fdfdea60Sskrll }
1303fdfdea60Sskrll
1304fdfdea60Sskrll void
dino_wrr_4(void * v,bus_space_handle_t h,bus_size_t o,const uint32_t * a,bus_size_t c)1305fdfdea60Sskrll dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o,
1306fdfdea60Sskrll const uint32_t *a, bus_size_t c)
1307fdfdea60Sskrll {
1308fdfdea60Sskrll volatile uint32_t *p;
1309fdfdea60Sskrll
1310fdfdea60Sskrll c /= 4;
1311fdfdea60Sskrll h += o;
1312fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1313fdfdea60Sskrll p = (volatile uint32_t *)h;
1314fdfdea60Sskrll while (c--)
1315fdfdea60Sskrll *p++ = *a++;
1316fdfdea60Sskrll } else {
1317fdfdea60Sskrll struct dino_softc *sc = v;
1318fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1319fdfdea60Sskrll
1320fdfdea60Sskrll for (; c--; h += 4) {
1321fdfdea60Sskrll r->pci_addr = h;
1322fdfdea60Sskrll r->pci_io_data = *a++;
1323fdfdea60Sskrll }
1324fdfdea60Sskrll }
1325fdfdea60Sskrll }
1326fdfdea60Sskrll
1327fdfdea60Sskrll void
dino_wrr_8(void * v,bus_space_handle_t h,bus_size_t o,const uint64_t * a,bus_size_t c)1328fdfdea60Sskrll dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o,
1329fdfdea60Sskrll const uint64_t *a, bus_size_t c)
1330fdfdea60Sskrll {
1331fdfdea60Sskrll panic("dino_wrr_8: not implemented");
1332fdfdea60Sskrll }
1333fdfdea60Sskrll
1334fdfdea60Sskrll void
dino_sr_1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t vv,bus_size_t c)1335fdfdea60Sskrll dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c)
1336fdfdea60Sskrll {
1337fdfdea60Sskrll volatile uint8_t *p;
1338fdfdea60Sskrll
1339fdfdea60Sskrll h += o;
1340fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1341fdfdea60Sskrll p = (volatile uint8_t *)h;
1342fdfdea60Sskrll while (c--)
1343fdfdea60Sskrll *p++ = vv;
1344fdfdea60Sskrll } else {
1345fdfdea60Sskrll struct dino_softc *sc = v;
1346fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1347fdfdea60Sskrll
1348fdfdea60Sskrll for (; c--; h++) {
1349fdfdea60Sskrll r->pci_addr = h;
1350fdfdea60Sskrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
1351fdfdea60Sskrll *p = vv;
1352fdfdea60Sskrll }
1353fdfdea60Sskrll }
1354fdfdea60Sskrll }
1355fdfdea60Sskrll
1356fdfdea60Sskrll void
dino_sr_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t vv,bus_size_t c)1357fdfdea60Sskrll dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c)
1358fdfdea60Sskrll {
1359fdfdea60Sskrll volatile uint16_t *p;
1360fdfdea60Sskrll
1361fdfdea60Sskrll h += o;
1362fdfdea60Sskrll vv = htole16(vv);
1363fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1364fdfdea60Sskrll p = (volatile uint16_t *)h;
1365fdfdea60Sskrll while (c--)
1366fdfdea60Sskrll *p++ = vv;
1367fdfdea60Sskrll } else {
1368fdfdea60Sskrll struct dino_softc *sc = v;
1369fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1370fdfdea60Sskrll
1371fdfdea60Sskrll for (; c--; h += 2) {
1372fdfdea60Sskrll r->pci_addr = h;
1373fdfdea60Sskrll p = (volatile uint16_t *)&r->pci_io_data;
1374fdfdea60Sskrll if (h & 2)
1375fdfdea60Sskrll p++;
1376fdfdea60Sskrll *p = vv;
1377fdfdea60Sskrll }
1378fdfdea60Sskrll }
1379fdfdea60Sskrll }
1380fdfdea60Sskrll
1381fdfdea60Sskrll void
dino_sr_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t vv,bus_size_t c)1382fdfdea60Sskrll dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c)
1383fdfdea60Sskrll {
1384fdfdea60Sskrll volatile uint32_t *p;
1385fdfdea60Sskrll
1386fdfdea60Sskrll h += o;
1387fdfdea60Sskrll vv = htole32(vv);
1388fdfdea60Sskrll if (h & HPPA_IOSPACE) {
1389fdfdea60Sskrll p = (volatile uint32_t *)h;
1390fdfdea60Sskrll while (c--)
1391fdfdea60Sskrll *p++ = vv;
1392fdfdea60Sskrll } else {
1393fdfdea60Sskrll struct dino_softc *sc = v;
1394fdfdea60Sskrll volatile struct dino_regs *r = sc->sc_regs;
1395fdfdea60Sskrll
1396fdfdea60Sskrll for (; c--; h += 4) {
1397fdfdea60Sskrll r->pci_addr = h;
1398fdfdea60Sskrll r->pci_io_data = vv;
1399fdfdea60Sskrll }
1400fdfdea60Sskrll }
1401fdfdea60Sskrll }
1402fdfdea60Sskrll
1403fdfdea60Sskrll void
dino_sr_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t vv,bus_size_t c)1404fdfdea60Sskrll dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c)
1405fdfdea60Sskrll {
1406fdfdea60Sskrll panic("dino_sr_8: not implemented");
1407fdfdea60Sskrll }
1408fdfdea60Sskrll
1409fdfdea60Sskrll void
dino_cp_1(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)1410fdfdea60Sskrll dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1,
1411fdfdea60Sskrll bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
1412fdfdea60Sskrll {
1413fdfdea60Sskrll while (c--)
1414fdfdea60Sskrll dino_w1(v, h1, o1++, dino_r1(v, h2, o2++));
1415fdfdea60Sskrll }
1416fdfdea60Sskrll
1417fdfdea60Sskrll void
dino_cp_2(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)1418fdfdea60Sskrll dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1,
1419fdfdea60Sskrll bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
1420fdfdea60Sskrll {
1421fdfdea60Sskrll while (c--) {
1422fdfdea60Sskrll dino_w2(v, h1, o1, dino_r2(v, h2, o2));
1423fdfdea60Sskrll o1 += 2;
1424fdfdea60Sskrll o2 += 2;
1425fdfdea60Sskrll }
1426fdfdea60Sskrll }
1427fdfdea60Sskrll
1428fdfdea60Sskrll void
dino_cp_4(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)1429fdfdea60Sskrll dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1,
1430fdfdea60Sskrll bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
1431fdfdea60Sskrll {
1432fdfdea60Sskrll while (c--) {
1433fdfdea60Sskrll dino_w4(v, h1, o1, dino_r4(v, h2, o2));
1434fdfdea60Sskrll o1 += 4;
1435fdfdea60Sskrll o2 += 4;
1436fdfdea60Sskrll }
1437fdfdea60Sskrll }
1438fdfdea60Sskrll
1439fdfdea60Sskrll void
dino_cp_8(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)1440fdfdea60Sskrll dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1,
1441fdfdea60Sskrll bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
1442fdfdea60Sskrll {
1443fdfdea60Sskrll while (c--) {
1444fdfdea60Sskrll dino_w8(v, h1, o1, dino_r8(v, h2, o2));
1445fdfdea60Sskrll o1 += 8;
1446fdfdea60Sskrll o2 += 8;
1447fdfdea60Sskrll }
1448fdfdea60Sskrll }
1449fdfdea60Sskrll
1450fdfdea60Sskrll
1451fdfdea60Sskrll const struct hppa_bus_space_tag dino_iomemt = {
1452fdfdea60Sskrll NULL,
1453fdfdea60Sskrll
1454fdfdea60Sskrll NULL, dino_unmap, dino_subregion, NULL, dino_free,
1455fdfdea60Sskrll dino_barrier, dino_vaddr, dino_mmap,
1456fdfdea60Sskrll dino_r1, dino_r2, dino_r4, dino_r8,
1457fdfdea60Sskrll dino_w1, dino_w2, dino_w4, dino_w8,
1458fdfdea60Sskrll dino_rm_1, dino_rm_2, dino_rm_4, dino_rm_8,
1459fdfdea60Sskrll dino_wm_1, dino_wm_2, dino_wm_4, dino_wm_8,
1460fdfdea60Sskrll dino_sm_1, dino_sm_2, dino_sm_4, dino_sm_8,
1461fdfdea60Sskrll dino_rrm_2, dino_rrm_4, dino_rrm_8,
1462fdfdea60Sskrll dino_wrm_2, dino_wrm_4, dino_wrm_8,
1463fdfdea60Sskrll dino_rr_1, dino_rr_2, dino_rr_4, dino_rr_8,
1464fdfdea60Sskrll dino_wr_1, dino_wr_2, dino_wr_4, dino_wr_8,
1465fdfdea60Sskrll dino_rrr_2, dino_rrr_4, dino_rrr_8,
1466fdfdea60Sskrll dino_wrr_2, dino_wrr_4, dino_wrr_8,
1467fdfdea60Sskrll dino_sr_1, dino_sr_2, dino_sr_4, dino_sr_8,
1468fdfdea60Sskrll dino_cp_1, dino_cp_2, dino_cp_4, dino_cp_8
1469fdfdea60Sskrll };
1470fdfdea60Sskrll
1471fdfdea60Sskrll int
dino_dmamap_create(void * v,bus_size_t size,int nsegments,bus_size_t maxsegsz,bus_size_t boundary,int flags,bus_dmamap_t * dmamp)1472fdfdea60Sskrll dino_dmamap_create(void *v, bus_size_t size, int nsegments,
1473fdfdea60Sskrll bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp)
1474fdfdea60Sskrll {
1475fdfdea60Sskrll struct dino_softc *sc = v;
1476fdfdea60Sskrll
1477fdfdea60Sskrll /* TODO check the addresses, boundary, enable dma */
1478fdfdea60Sskrll
1479fdfdea60Sskrll return bus_dmamap_create(sc->sc_dmat, size, nsegments,
1480fdfdea60Sskrll maxsegsz, boundary, flags, dmamp);
1481fdfdea60Sskrll }
1482fdfdea60Sskrll
1483fdfdea60Sskrll void
dino_dmamap_destroy(void * v,bus_dmamap_t map)1484fdfdea60Sskrll dino_dmamap_destroy(void *v, bus_dmamap_t map)
1485fdfdea60Sskrll {
1486fdfdea60Sskrll struct dino_softc *sc = v;
1487fdfdea60Sskrll
1488fdfdea60Sskrll bus_dmamap_destroy(sc->sc_dmat, map);
1489fdfdea60Sskrll }
1490fdfdea60Sskrll
1491fdfdea60Sskrll int
dino_dmamap_load(void * v,bus_dmamap_t map,void * addr,bus_size_t size,struct proc * p,int flags)1492fdfdea60Sskrll dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size,
1493fdfdea60Sskrll struct proc *p, int flags)
1494fdfdea60Sskrll {
1495fdfdea60Sskrll struct dino_softc *sc = v;
1496fdfdea60Sskrll
1497fdfdea60Sskrll return bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags);
1498fdfdea60Sskrll }
1499fdfdea60Sskrll
1500fdfdea60Sskrll int
dino_dmamap_load_mbuf(void * v,bus_dmamap_t map,struct mbuf * m,int flags)1501fdfdea60Sskrll dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags)
1502fdfdea60Sskrll {
1503fdfdea60Sskrll struct dino_softc *sc = v;
1504fdfdea60Sskrll
1505fdfdea60Sskrll return bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags);
1506fdfdea60Sskrll }
1507fdfdea60Sskrll
1508fdfdea60Sskrll int
dino_dmamap_load_uio(void * v,bus_dmamap_t map,struct uio * uio,int flags)1509fdfdea60Sskrll dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags)
1510fdfdea60Sskrll {
1511fdfdea60Sskrll struct dino_softc *sc = v;
1512fdfdea60Sskrll
1513fdfdea60Sskrll return bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags);
1514fdfdea60Sskrll }
1515fdfdea60Sskrll
1516fdfdea60Sskrll int
dino_dmamap_load_raw(void * v,bus_dmamap_t map,bus_dma_segment_t * segs,int nsegs,bus_size_t size,int flags)1517fdfdea60Sskrll dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs,
1518fdfdea60Sskrll int nsegs, bus_size_t size, int flags)
1519fdfdea60Sskrll {
1520fdfdea60Sskrll struct dino_softc *sc = v;
1521fdfdea60Sskrll
1522fdfdea60Sskrll return bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags);
1523fdfdea60Sskrll }
1524fdfdea60Sskrll
1525fdfdea60Sskrll void
dino_dmamap_unload(void * v,bus_dmamap_t map)1526fdfdea60Sskrll dino_dmamap_unload(void *v, bus_dmamap_t map)
1527fdfdea60Sskrll {
1528fdfdea60Sskrll struct dino_softc *sc = v;
1529fdfdea60Sskrll
1530fdfdea60Sskrll bus_dmamap_unload(sc->sc_dmat, map);
1531fdfdea60Sskrll }
1532fdfdea60Sskrll
1533fdfdea60Sskrll void
dino_dmamap_sync(void * v,bus_dmamap_t map,bus_addr_t off,bus_size_t len,int ops)1534fdfdea60Sskrll dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off,
1535fdfdea60Sskrll bus_size_t len, int ops)
1536fdfdea60Sskrll {
1537fdfdea60Sskrll struct dino_softc *sc = v;
1538fdfdea60Sskrll
1539fdfdea60Sskrll return bus_dmamap_sync(sc->sc_dmat, map, off, len, ops);
1540fdfdea60Sskrll }
1541fdfdea60Sskrll
1542fdfdea60Sskrll int
dino_dmamem_alloc(void * v,bus_size_t size,bus_size_t alignment,bus_size_t boundary,bus_dma_segment_t * segs,int nsegs,int * rsegs,int flags)1543fdfdea60Sskrll dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment,
1544fdfdea60Sskrll bus_size_t boundary, bus_dma_segment_t *segs,
1545fdfdea60Sskrll int nsegs, int *rsegs, int flags)
1546fdfdea60Sskrll {
1547fdfdea60Sskrll struct dino_softc *sc = v;
1548fdfdea60Sskrll
1549fdfdea60Sskrll return bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary,
1550fdfdea60Sskrll segs, nsegs, rsegs, flags);
1551fdfdea60Sskrll }
1552fdfdea60Sskrll
1553fdfdea60Sskrll void
dino_dmamem_free(void * v,bus_dma_segment_t * segs,int nsegs)1554fdfdea60Sskrll dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs)
1555fdfdea60Sskrll {
1556fdfdea60Sskrll struct dino_softc *sc = v;
1557fdfdea60Sskrll
1558fdfdea60Sskrll bus_dmamem_free(sc->sc_dmat, segs, nsegs);
1559fdfdea60Sskrll }
1560fdfdea60Sskrll
1561fdfdea60Sskrll int
dino_dmamem_map(void * v,bus_dma_segment_t * segs,int nsegs,size_t size,void ** kvap,int flags)1562fdfdea60Sskrll dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size,
1563fdfdea60Sskrll void **kvap, int flags)
1564fdfdea60Sskrll {
1565fdfdea60Sskrll struct dino_softc *sc = v;
1566fdfdea60Sskrll
1567fdfdea60Sskrll return bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags);
1568fdfdea60Sskrll }
1569fdfdea60Sskrll
1570fdfdea60Sskrll void
dino_dmamem_unmap(void * v,void * kva,size_t size)1571fdfdea60Sskrll dino_dmamem_unmap(void *v, void *kva, size_t size)
1572fdfdea60Sskrll {
1573fdfdea60Sskrll struct dino_softc *sc = v;
1574fdfdea60Sskrll
1575fdfdea60Sskrll bus_dmamem_unmap(sc->sc_dmat, kva, size);
1576fdfdea60Sskrll }
1577fdfdea60Sskrll
1578fdfdea60Sskrll paddr_t
dino_dmamem_mmap(void * v,bus_dma_segment_t * segs,int nsegs,off_t off,int prot,int flags)1579fdfdea60Sskrll dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off,
1580fdfdea60Sskrll int prot, int flags)
1581fdfdea60Sskrll {
1582fdfdea60Sskrll struct dino_softc *sc = v;
1583fdfdea60Sskrll
1584fdfdea60Sskrll return bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags);
1585fdfdea60Sskrll }
1586fdfdea60Sskrll
1587fdfdea60Sskrll const struct hppa_bus_dma_tag dino_dmat = {
1588fdfdea60Sskrll NULL,
1589fdfdea60Sskrll dino_dmamap_create, dino_dmamap_destroy,
1590fdfdea60Sskrll dino_dmamap_load, dino_dmamap_load_mbuf,
1591fdfdea60Sskrll dino_dmamap_load_uio, dino_dmamap_load_raw,
1592fdfdea60Sskrll dino_dmamap_unload, dino_dmamap_sync,
1593fdfdea60Sskrll
1594fdfdea60Sskrll dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map,
1595fdfdea60Sskrll dino_dmamem_unmap, dino_dmamem_mmap
1596fdfdea60Sskrll };
1597fdfdea60Sskrll
1598fdfdea60Sskrll const struct hppa_pci_chipset_tag dino_pc = {
15993b0b7435Sskrll .pc_attach_hook = dino_attach_hook,
16003b0b7435Sskrll .pc_bus_maxdevs = dino_maxdevs,
16013b0b7435Sskrll .pc_make_tag = dino_make_tag,
16023b0b7435Sskrll .pc_decompose_tag = dino_decompose_tag,
16033b0b7435Sskrll .pc_conf_read = dino_conf_read,
16043b0b7435Sskrll .pc_conf_write = dino_conf_write,
16053b0b7435Sskrll .pc_intr_map = dino_intr_map,
16063b0b7435Sskrll .pc_intr_string = dino_intr_string,
16073b0b7435Sskrll .pc_intr_establish = dino_intr_establish,
16083b0b7435Sskrll .pc_intr_disestablish = dino_intr_disestablish,
1609fdfdea60Sskrll #if NCARDBUS > 0
16103b0b7435Sskrll .pc_alloc_parent = dino_alloc_parent,
1611fdfdea60Sskrll #endif
1612fdfdea60Sskrll };
1613fdfdea60Sskrll
1614fdfdea60Sskrll int
dinomatch(device_t parent,cfdata_t cfdata,void * aux)1615fdfdea60Sskrll dinomatch(device_t parent, cfdata_t cfdata, void *aux)
1616fdfdea60Sskrll {
1617fdfdea60Sskrll struct confargs *ca = aux;
1618fdfdea60Sskrll
1619fdfdea60Sskrll /* there will be only one */
1620fdfdea60Sskrll if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE ||
1621fdfdea60Sskrll ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO)
1622fdfdea60Sskrll return 0;
1623fdfdea60Sskrll
1624fdfdea60Sskrll /* do not match on the elroy family */
1625fdfdea60Sskrll if (ca->ca_type.iodc_model == 0x78)
1626fdfdea60Sskrll return 0;
1627fdfdea60Sskrll
1628fdfdea60Sskrll return 1;
1629fdfdea60Sskrll }
1630fdfdea60Sskrll
1631fdfdea60Sskrll void
dinoattach(device_t parent,device_t self,void * aux)1632fdfdea60Sskrll dinoattach(device_t parent, device_t self, void *aux)
1633fdfdea60Sskrll {
1634fdfdea60Sskrll struct dino_softc *sc = device_private(self);
1635fdfdea60Sskrll struct confargs *ca = (struct confargs *)aux, nca;
1636fdfdea60Sskrll struct pcibus_attach_args pba;
1637fdfdea60Sskrll volatile struct dino_regs *r;
1638fdfdea60Sskrll struct cpu_info *ci = &cpus[0];
1639fdfdea60Sskrll const char *p = NULL;
1640fdfdea60Sskrll int s, ver;
1641fdfdea60Sskrll
1642fdfdea60Sskrll sc->sc_dv = self;
1643fdfdea60Sskrll sc->sc_bt = ca->ca_iot;
1644fdfdea60Sskrll sc->sc_dmat = ca->ca_dmatag;
1645fdfdea60Sskrll
1646fdfdea60Sskrll ca->ca_irq = hppa_intr_allocate_bit(&ci->ci_ir, ca->ca_irq);
1647fdfdea60Sskrll if (ca->ca_irq == HPPACF_IRQ_UNDEF) {
1648fdfdea60Sskrll aprint_error_dev(self, ": can't allocate interrupt");
1649fdfdea60Sskrll return;
1650fdfdea60Sskrll }
1651fdfdea60Sskrll
1652fdfdea60Sskrll if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) {
1653fdfdea60Sskrll aprint_error(": can't map space\n");
1654fdfdea60Sskrll return;
1655fdfdea60Sskrll }
1656fdfdea60Sskrll
1657fdfdea60Sskrll sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh;
1658fdfdea60Sskrll #ifdef trust_the_firmware_to_proper_initialize_everything
1659fdfdea60Sskrll r->io_addr_en = 0;
1660fdfdea60Sskrll r->io_control = 0x80;
1661fdfdea60Sskrll r->pamr = 0;
1662fdfdea60Sskrll r->papr = 0;
1663fdfdea60Sskrll r->io_fbb_en |= 1;
1664fdfdea60Sskrll r->damode = 0;
1665fdfdea60Sskrll r->gmask &= ~1; /* allow GSC bus req */
1666fdfdea60Sskrll r->pciror = 0;
1667fdfdea60Sskrll r->pciwor = 0;
1668fdfdea60Sskrll r->brdg_feat = 0xc0000000;
1669fdfdea60Sskrll #endif
1670fdfdea60Sskrll
1671fdfdea60Sskrll snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname),
1672fdfdea60Sskrll "%s_io", device_xname(self));
1673cadbabe0Schs sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff,
1674cadbabe0Schs NULL, 0, EX_WAITOK | EX_MALLOCOK);
1675fdfdea60Sskrll
1676fdfdea60Sskrll /* interrupts guts */
1677fdfdea60Sskrll s = splhigh();
1678fdfdea60Sskrll r->icr = 0;
1679fdfdea60Sskrll r->imr = 0;
1680f27c7d63Sskrll (void)r->irr0;
1681fdfdea60Sskrll r->iar0 = ci->ci_hpa | (31 - ca->ca_irq);
1682fdfdea60Sskrll splx(s);
1683fdfdea60Sskrll /* Establish the interrupt register. */
1684fdfdea60Sskrll hppa_interrupt_register_establish(ci, &sc->sc_ir);
1685fdfdea60Sskrll sc->sc_ir.ir_name = device_xname(self);
1686fdfdea60Sskrll sc->sc_ir.ir_mask = &r->imr;
1687fdfdea60Sskrll sc->sc_ir.ir_req = &r->irr0;
1688fdfdea60Sskrll sc->sc_ir.ir_level = &r->ilr;
1689fdfdea60Sskrll /* Add the I/O interrupt register. */
1690fdfdea60Sskrll
1691fdfdea60Sskrll sc->sc_ih = hppa_intr_establish(IPL_NONE, NULL, &sc->sc_ir,
1692fdfdea60Sskrll &ci->ci_ir, ca->ca_irq);
1693fdfdea60Sskrll
1694fdfdea60Sskrll /* TODO establish the bus error interrupt */
1695fdfdea60Sskrll
1696fdfdea60Sskrll ver = ca->ca_type.iodc_revision;
1697fdfdea60Sskrll switch ((ca->ca_type.iodc_model << 4) |
1698fdfdea60Sskrll (ca->ca_type.iodc_revision >> 4)) {
1699fdfdea60Sskrll case 0x05d:
1700fdfdea60Sskrll p = "Dino (card)"; /* j2240 */
1701fdfdea60Sskrll /* FALLTHROUGH */
1702fdfdea60Sskrll case 0x680:
1703fdfdea60Sskrll if (!p)
1704fdfdea60Sskrll p = "Dino";
1705fdfdea60Sskrll switch (ver & 0xf) {
1706fdfdea60Sskrll case 0: ver = 0x20; break;
1707fdfdea60Sskrll case 1: ver = 0x21; break;
1708fdfdea60Sskrll case 2: ver = 0x30; break;
1709fdfdea60Sskrll case 3: ver = 0x31; break;
1710fdfdea60Sskrll }
1711fdfdea60Sskrll break;
1712fdfdea60Sskrll
1713fdfdea60Sskrll case 0x682:
1714fdfdea60Sskrll p = "Cujo";
1715fdfdea60Sskrll switch (ver & 0xf) {
1716fdfdea60Sskrll case 0: ver = 0x10; break;
1717fdfdea60Sskrll case 1: ver = 0x20; break;
1718fdfdea60Sskrll }
1719fdfdea60Sskrll break;
1720fdfdea60Sskrll
1721fdfdea60Sskrll default:
1722fdfdea60Sskrll p = "Mojo";
1723fdfdea60Sskrll break;
1724fdfdea60Sskrll }
1725fdfdea60Sskrll
1726fdfdea60Sskrll sc->sc_ver = ver;
1727fdfdea60Sskrll aprint_normal(": %s V%d.%d\n", p, ver >> 4, ver & 0xf);
1728fdfdea60Sskrll
1729fdfdea60Sskrll sc->sc_iot = dino_iomemt;
1730fdfdea60Sskrll sc->sc_iot.hbt_cookie = sc;
1731fdfdea60Sskrll sc->sc_iot.hbt_map = dino_iomap;
1732fdfdea60Sskrll sc->sc_iot.hbt_alloc = dino_ioalloc;
1733fdfdea60Sskrll sc->sc_memt = dino_iomemt;
1734fdfdea60Sskrll sc->sc_memt.hbt_cookie = sc;
1735fdfdea60Sskrll sc->sc_memt.hbt_map = dino_memmap;
1736fdfdea60Sskrll sc->sc_memt.hbt_alloc = dino_memalloc;
1737fdfdea60Sskrll sc->sc_pc = dino_pc;
1738fdfdea60Sskrll sc->sc_pc._cookie = sc;
1739fdfdea60Sskrll sc->sc_dmatag = dino_dmat;
1740fdfdea60Sskrll sc->sc_dmatag._cookie = sc;
1741fdfdea60Sskrll
1742fdfdea60Sskrll /* scan for ps2 kbd/ms, serial, and flying toasters */
1743fdfdea60Sskrll nca = *ca;
1744fdfdea60Sskrll
1745fdfdea60Sskrll nca.ca_hpabase = 0;
1746fdfdea60Sskrll nca.ca_nmodules = MAXMODBUS;
1747fdfdea60Sskrll pdc_scanbus(self, &nca, dino_callback);
1748fdfdea60Sskrll
1749fdfdea60Sskrll memset(&pba, 0, sizeof(pba));
1750fdfdea60Sskrll pba.pba_iot = &sc->sc_iot;
1751fdfdea60Sskrll pba.pba_memt = &sc->sc_memt;
1752fdfdea60Sskrll pba.pba_dmat = &sc->sc_dmatag;
1753fdfdea60Sskrll pba.pba_pc = &sc->sc_pc;
1754fdfdea60Sskrll pba.pba_bus = 0;
1755fdfdea60Sskrll pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
17563bee0c11Sthorpej config_found(self, &pba, pcibusprint,
1757beecddb6Sthorpej CFARGS(.iattr = "pcibus"));
1758fdfdea60Sskrll }
1759fdfdea60Sskrll
1760fdfdea60Sskrll static device_t
dino_callback(device_t self,struct confargs * ca)1761fdfdea60Sskrll dino_callback(device_t self, struct confargs *ca)
1762fdfdea60Sskrll {
17633bee0c11Sthorpej return config_found(self, ca, mbprint,
1764beecddb6Sthorpej CFARGS(.submatch = mbsubmatch,
1765beecddb6Sthorpej .iattr = "gedoens"));
1766fdfdea60Sskrll }
1767