1 /* $NetBSD: db_disasm.c,v 1.1 2002/06/05 01:04:19 fredette Exp $ */ 2 3 /* $OpenBSD: db_disasm.c,v 1.9 2000/04/18 20:02:45 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 1999 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Michael Shalayeff. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /* 35 * (c) Copyright 1992 HEWLETT-PACKARD COMPANY 36 * 37 * To anyone who acknowledges that this file is provided "AS IS" 38 * without any express or implied warranty: 39 * permission to use, copy, modify, and distribute this file 40 * for any purpose is hereby granted without fee, provided that 41 * the above copyright notice and this notice appears in all 42 * copies, and that the name of Hewlett-Packard Company not be 43 * used in advertising or publicity pertaining to distribution 44 * of the software without specific, written prior permission. 45 * Hewlett-Packard Company makes no representations about the 46 * suitability of this software for any purpose. 47 */ 48 49 /* 50 * unasm.c -- HP_PA Instruction Printer 51 */ 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 56 #include <machine/db_machdep.h> 57 #include <ddb/db_access.h> 58 #include <ddb/db_sym.h> 59 #include <ddb/db_output.h> 60 #include <ddb/db_interface.h> 61 62 63 /* IMPORTANT NOTE: 64 * All modules using this header may assume that the datatype "int" is a 65 * 32-bit (or > 32-bit) signed quantity. 66 */ 67 68 69 /* Spectrum Architecturally Defined Datatypes */ 70 struct doubleword { 71 int wd0; 72 int wd1; 73 }; 74 75 struct quadword { 76 struct doubleword d0; 77 struct doubleword d1; 78 }; 79 80 /* datatypes for halfword and byte fields of a word are defined 81 * in ssBits.h */ 82 83 /* Memory addressing datatypes */ 84 typedef unsigned int SID, /* range [0..MAXSID] */ 85 PGID, /* range [0..MAXPGID] */ 86 OFS, /* range [0..MAXINT] */ 87 REALADR; /* range [0..MAXINT] */ 88 89 90 /* data sizes */ 91 enum datasize { Byte, Halfword, Word, Doubleword, Quadword, Variable }; 92 93 /* Miscellaneous datatypes */ 94 typedef unsigned int FLAGS; 95 96 /* struct for entry in unwind table */ 97 struct ute { 98 int word1; 99 int word2; 100 int word3; 101 int word4; 102 }; 103 /* 104 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 105 * 106 * Spectrum Instruction Set Condition Completer Bit Assignments 107 * Dan Magenheimer - 6/14/82 108 * Terrence Miller - 6/21/82 109 * Computer Research Center, Hewlett-Packard Labs 110 * 111 * (c) copyright 1982 112 * (p) protected 1982 113 * The Hewlett-Packard Company 114 * Hewlett-Packard Laboratories 115 * Computer Research Center 116 * Palo Alto, California 117 * 118 * *** HP Company Confidential *** 119 * 120 * Log: unasm.c,v 121 * Revision 1.5 1994/07/21 22:32:05 mike 122 * official HP copyright notice 123 * 124 * Revision 1.4 1992/07/08 12:19:52 dalton 125 * Checkin before split to 1.0.4 release (by LBS). 126 * 127 * Revision 1.3 92/06/06 16:16:45 dalton 128 * *** empty log message *** 129 * 130 * Revision 1.2 92/06/06 15:42:28 dalton 131 * Changed include to be a path relative to hp800. 132 * 133 * Revision 1.1 92/06/06 14:05:33 dalton 134 * Initial revision 135 * 136 * Revision 1.2 91/04/14 20:29:49 osfrcs 137 * Initial version. 138 * [91/03/30 09:20:34 brezak] 139 * 140 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 141 * Initial version. 142 * [91/03/30 09:20:34 brezak] 143 * 144 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 145 * Initial version. 146 * 147 * Revision 1.1 88/07/11 14:05:15 14:05:15 ren (Bob Naas) 148 * Initial revision 149 * 150 * Revision 5.2 87/07/02 14:45:57 14:45:57 kent (Kent McMullen) 151 * added constants to support addDasm and addDCond added to ssDID.c 152 * 153 * Revision 5.1 87/02/27 11:12:08 11:12:08 kent (Kent McMullen) 154 * update all src to 5.1 155 * 156 * Revision 5.0 87/02/18 16:31:15 16:31:15 kent (Kent McMullen) 157 * update all revision numbers to 5.0 for release 158 * 159 * Revision 1.1 86/07/15 08:34:55 08:34:55 kent (Kent McMullen) 160 * Initial revision 161 * 162 * Revision 4.1 83/10/25 17:01:22 17:01:22 djm (Daniel J Magenheimer) 163 * First release for ACD v4 164 * 165 * Revision 3.0 83/06/13 10:22:59 djm (Daniel Magenheimer) 166 * First release for distribution 167 * 168 * 169 */ 170 171 172 /* Arithmetic/Logical Conditions */ 173 #define NEV 0x0 174 #define EQZ 0x2 175 #define LT 0x4 176 #define LE 0x6 177 #define LLT 0x8 178 #define NUV 0x8 179 #define LLE 0xA 180 #define ZNV 0xA 181 #define SV 0xC 182 #define OD 0xE 183 #define TR 0x1 184 #define NEQZ 0x3 185 #define GE 0x5 186 #define GT 0x7 187 #define LGE 0x9 188 #define UV 0x9 189 #define LGT 0xB 190 #define VNZ 0xB 191 #define NSV 0xD 192 #define EV 0xF 193 194 /* unit conditions */ 195 #define SBZ 0x4 196 #define SHZ 0x6 197 #define SDC 0x8 198 #define SBC 0xC 199 #define SHC 0xE 200 #define NBZ 0x5 201 #define NHZ 0x7 202 #define NDC 0x9 203 #define NBC 0xD 204 #define NHC 0xF 205 206 /*field conditions */ 207 #define XEQ 0x1 208 #define XLT 0x2 209 #define XOD 0x3 210 #define XTR 0x4 211 #define XNE 0x5 212 #define XGE 0x6 213 #define XEV 0x7 214 215 216 217 /* 218 * These macros are designed to be portable to all machines that have 219 * a wordsize greater than or equal to 32 bits that support the portable 220 * C compiler and the standard C preprocessor. Wordsize (default 32) 221 * and bitfield assignment (default left-to-right, unlike VAX, PDP-11) 222 * should be predefined using the constants HOSTWDSZ and BITFRL and 223 * the C compiler "-D" flag (e.g., -DHOSTWDSZ=36 -DBITFLR for the DEC-20). 224 * Note that the macro arguments assume that the integer being referenced 225 * is a 32-bit integer (right-justified on the 20) and that bit 0 is the 226 * most significant bit. 227 */ 228 229 #ifndef HOSTWDSZ 230 #define HOSTWDSZ 32 231 #endif 232 233 #ifdef vax 234 #ifndef BITFLR 235 #define BITFRL 236 #endif 237 #else 238 #define BITFLR 239 #endif 240 241 /*########################### Macros ######################################*/ 242 243 /*--------------------------------------------------------------------------- 244 * DeclareBitfield$Reference - Declare a structure to be used to reference 245 * a specified bitfield within an integer (using BitfR, see below). 246 * The argument "n" must be an identifier name not used elsewhere in the 247 * program , "s" and "l" must (alas!) be constants. (Suggestion: if 248 * "s" == 2 and "l" == 8, use _b28 for "n".) The name "BITFLR" should 249 * be pre-defined if the compiler assigns bitfields from left-to-right. 250 * The resultant macro expansion defines a stucture in which the bit field 251 * starting at position "s" with length "l" may be referenced by accessing 252 * member "n". [Note: The leftmost bits in a 36-bit word may be accessed 253 * by specifying -4 <= s < 0 on the DEC-20.] 254 *---------------------------------------------------------------------------*/ 255 256 #ifdef BITFRL 257 #define DeclBitfR(s,l,n) struct n { int:(HOSTWDSZ-(s)-(l)); unsigned n:l;}; 258 #else 259 #define DeclBitfR(s,l,n) struct n { int:((s)+(HOSTWDSZ-32)); unsigned n:l;}; 260 #endif 261 262 /*--------------------------------------------------------------------------- 263 * Bitfield$Reference - Reference a specified bitfield within an integer. 264 * The argument "i" must be an addressable variable (i.e., not a register 265 * variable or an expression... but see BitfX below), "n" must be an 266 * identifier name declared in a DeclBitfR invocation. The resultant 267 * macro expansion references the bit field in "i" described by the 268 * DeclBitfR invocation with the same name ("n"). BitfR may be used as 269 * an lvalue or an rvalue. (i.e., either side of an assignment statement) 270 * The "s" and "l" arguments are historical and are now unused. (They 271 * correspond to the "s" and "l" arguments in DeclBitfR) 272 * Translates to a single instruction on both the VAX and the DEC-20. 273 *---------------------------------------------------------------------------*/ 274 #define BitfR(i,s,l,n) (((struct n *)&i)->n) 275 276 /*--------------------------------------------------------------------------- 277 * Bitfield$eXtract - Extract the specified field from an integer. Arguments 278 * are the same as for BitfR (except no "n"), however both "s" and "l" need 279 * no longer be constants. May only be used as an rvalue. Translates to 280 * two instructions on the VAX, three on the DEC-20. 281 *---------------------------------------------------------------------------*/ 282 283 #define BitfX(i,s,l) (((i) >> (32-(s)-(l))) & ((1 << (l)) - 1)) 284 285 286 /*--------------------------------------------------------------------------- 287 * Mask$32bits - Mask the low order 32 bits of passed word. No-op on 32 288 * bit machines. 289 *---------------------------------------------------------------------------*/ 290 291 #if HOSTWDSZ > 32 292 #define Mask32(x) ((x) & 0xffffffff) 293 #else 294 #define Mask32(x) (x) 295 #endif 296 297 298 /*--------------------------------------------------------------------------- 299 * SignExtend$32bits - Force the high-order bits in machines with wordsize 300 * longer than 32 to match bit 0. 301 *---------------------------------------------------------------------------*/ 302 303 #if HOSTWDSZ > 32 304 #define SignEx32(x) (((x) & 0x80000000) ? ((x) | ((unsigned)-1 << 32)) \ 305 : Mask32(x)) 306 #else 307 #define SignEx32(x) (x) 308 #endif 309 310 /**************************/ 311 /* bit field declarations */ 312 /**************************/ 313 314 /* since the compiler complains if a structure name is declared twice, even 315 * if the declarations are identical, all DeclBitfR invocations are 316 * given here in one file. */ 317 318 DeclBitfR(0,1,_b01) 319 DeclBitfR(0,15,_b015) 320 DeclBitfR(0,16,_b016) 321 DeclBitfR(0,4,_b04) 322 DeclBitfR(0,6,_b06) 323 DeclBitfR(0,8,_b08) 324 DeclBitfR(4,1,_b41) 325 DeclBitfR(4,4,_b44) 326 DeclBitfR(6,1,_b61) 327 DeclBitfR(6,13,_b613) 328 DeclBitfR(6,15,_b615) 329 DeclBitfR(6,17,_b617) 330 DeclBitfR(6,26,_b626) 331 DeclBitfR(6,5,_b65) 332 DeclBitfR(7,1,_b71) 333 DeclBitfR(8,1,_b81) 334 DeclBitfR(8,4,_b84) 335 DeclBitfR(8,8,_b88) 336 DeclBitfR(9,1,_b91) 337 DeclBitfR(10,1,_b101) 338 DeclBitfR(11,1,_b111) 339 DeclBitfR(11,10,_b1110) 340 DeclBitfR(11,4,_b114) 341 DeclBitfR(11,5,_b115) 342 DeclBitfR(12,1,_b121) 343 DeclBitfR(12,4,_b124) 344 DeclBitfR(13,1,_b131) 345 DeclBitfR(14,1,_b141) 346 DeclBitfR(15,1,_b151) 347 DeclBitfR(16,1,_b161) 348 DeclBitfR(16,15,_b1615) 349 DeclBitfR(16,16,_b1616) 350 DeclBitfR(16,2,_b162) 351 DeclBitfR(16,3,_b163) 352 DeclBitfR(16,4,_b164) 353 DeclBitfR(16,5,_b165) 354 DeclBitfR(16,8,_b168) 355 DeclBitfR(17,1,_b171) 356 DeclBitfR(18,1,_b181) 357 DeclBitfR(18,13,_b1813) 358 DeclBitfR(18,2,_b182) 359 DeclBitfR(18,7,_b187) 360 DeclBitfR(19,1,_b191) 361 DeclBitfR(19,8,_b198) 362 DeclBitfR(19,10,_b1910) 363 DeclBitfR(20,11,_b2011) 364 DeclBitfR(20,2,_b202) 365 DeclBitfR(20,4,_b204) 366 DeclBitfR(21,10,_b2110) 367 DeclBitfR(21,2,_b212) 368 DeclBitfR(21,5,_b215) 369 DeclBitfR(22,5,_b225) 370 DeclBitfR(23,3,_b233) 371 DeclBitfR(24,1,_b241) 372 DeclBitfR(24,4,_b244) 373 DeclBitfR(24,8,_b248) 374 DeclBitfR(25,1,_b251) 375 DeclBitfR(26,1,_b261) 376 DeclBitfR(27,1,_b271) 377 DeclBitfR(27,4,_b274) 378 DeclBitfR(27,5,_b275) 379 DeclBitfR(28,1,_b281) 380 DeclBitfR(28,4,_b284) 381 DeclBitfR(29,1,_b291) 382 DeclBitfR(30,1,_b301) 383 DeclBitfR(30,2,_b302) 384 DeclBitfR(31,1,_b311) 385 386 /******************/ 387 /* Word subfields */ 388 /******************/ 389 390 #define Sign(i) BitfR(i,0,1,_b01) 391 /* halfwords */ 392 #define Hwd0(i) BitfR(i,0,16,_b016) 393 #define Hwd1sign(i) BitfR(i,16,1,_b161) 394 #define Hwd1(i) BitfR(i,16,16,_b1616) 395 /* bytes */ 396 #define Byte0(i) BitfR(i,0,8,_b08) 397 #define Byte1sign(i) BitfR(i,8,1,_b81) 398 #define Byte1(i) BitfR(i,8,8,_b88) 399 #define Byte2(i) BitfR(i,16,8,_b168) 400 #define Byte3sign(i) BitfR(i,24,1,_b241) 401 #define Byte3(i) BitfR(i,24,8,_b248) 402 /* digits */ 403 #define Digit0(i) BitfR(i,0,4,_b04) 404 #define Digit1(i) BitfR(i,4,4,_b44) 405 #define Digit2(i) BitfR(i,8,4,_b84) 406 #define Digit3(i) BitfR(i,12,4,_b124) 407 #define Digit4(i) BitfR(i,16,4,_b164) 408 #define Digit5(i) BitfR(i,20,4,_b204) 409 #define Digit6(i) BitfR(i,24,4,_b244) 410 #define Digit7(i) BitfR(i,28,4,_b284) 411 412 /* Wordsize definitions */ 413 414 #define BIT_P_DW 64 /* bits/doubleword */ 415 #define BIT_P_WD 32 /* bits/word */ 416 #define BIT_P_HW 16 /* bits/halfword */ 417 #define BIT_P_BYT 8 /* bits/byte */ 418 #define BYT_P_DW 8 /* bytes/doubleword */ 419 #define BYT_P_WD 4 /* bytes/word */ 420 #define BYT_P_HW 2 /* bytes/halfword */ 421 422 /* Masks */ 423 424 #define WDMASK 0xffffffff /* 32-bit mask */ 425 #define OFSMASK 0xffffffff /* 32-bit mask */ 426 #define SIDMASK 0xffffffff /* 32-bit mask */ 427 #define SIGNMASK 0x80000000 /* 32 bit word sign bit */ 428 429 /* Alignments */ 430 431 #define wdalign(ofs) (ofs &= ~3) 432 /* 433 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 434 * 435 * Spectrum Simulator Instruction Opcode Definitions 436 * Dan Magenheimer 437 * Computer Research Center, Hewlett-Packard Labs 438 * 439 * (c) copyright 1982 440 * (p) protected 1982 441 * The Hewlett-Packard Company 442 * Hewlett-Packard Laboratories 443 * Computer Research Center 444 * Palo Alto, California 445 * 446 * *** HP Company Confidential *** 447 * 448 * Log: unasm.c,v 449 * Revision 1.5 1994/07/21 22:32:05 mike 450 * official HP copyright notice 451 * 452 * Revision 1.4 1992/07/08 12:19:52 dalton 453 * Checkin before split to 1.0.4 release (by LBS). 454 * 455 * Revision 1.3 92/06/06 16:16:45 dalton 456 * *** empty log message *** 457 * 458 * Revision 1.2 92/06/06 15:42:28 dalton 459 * Changed include to be a path relative to hp800. 460 * 461 * Revision 1.1 92/06/06 14:05:33 dalton 462 * Initial revision 463 * 464 * Revision 1.2 91/04/14 20:29:49 osfrcs 465 * Initial version. 466 * [91/03/30 09:20:34 brezak] 467 * 468 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 469 * Initial version. 470 * [91/03/30 09:20:34 brezak] 471 * 472 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 473 * Initial version. 474 * 475 * Revision 6.1 89/09/06 10:39:58 burroughs 476 * Added shadow registers for gr0-gr7. 477 * gr0-7 are copied into sh0-7 whenever a trap occurs 478 * the instruction RFIR restores gr0-7 from sh0-7 and returns from 479 * interrupt. 480 * the "sh" command displays the shadow registers 481 * = sh7 0x789 works, too. 482 * 483 * Revision 6.0 89/09/01 15:46:37 15:46:37 burroughs (Greg Burroughs) 484 * baseline for pcx simple offsite 485 * 486 * Revision 5.2 87/09/02 14:30:23 14:30:23 kent 487 * separated stat gathering for indexed vs short. 488 * this will NOT work if cache hints ever get used 489 * since this field was assumed always zero 490 * 491 * Revision 5.1 87/02/27 11:12:16 11:12:16 kent (Kent McMullen) 492 * update all src to 5.1 493 * 494 * Revision 5.0 87/02/18 16:31:35 16:31:35 kent (Kent McMullen) 495 * update all revision numbers to 5.0 for release 496 * 497 * Revision 1.1 86/07/15 08:34:57 08:34:57 kent (Kent McMullen) 498 * Initial revision 499 * 500 * Revision 4.1 83/10/25 17:02:34 17:02:34 djm (Daniel J Magenheimer) 501 * First release for ACD v4 502 * 503 * Revision 3.0 83/06/13 10:24:45 djm (Daniel Magenheimer) 504 * First release for distribution 505 * 506 * 507 */ 508 509 /* 510 * Changes: 511 * 01/30/90 ejf Simplify SPOPn support, now only gives assist emulation trap. 512 * 01/19/90 ejf Replace linpak instructions with just FSTQ[SX]. 513 * 12/19/89 ejf Add PA89 new floating point opcode 0E. 514 * 12/18/89 ejf Change 5 ops to PA89 format. 515 * 12/01/89 ejf Move additional instructions fmas, fmaa, fld2, fst2 to ssILst 516 * 09/22/89 ejf Fix unbalanced comments. 517 */ 518 519 520 /* ..and modified by hand to remove the load/store short references */ 521 /* ..and modified by hand to make memory management ops conform to the 522 * requirement that all subops of a major opcode begin in the same 523 * place and have the same length */ 524 525 #define LDW 0x12, 0x00, 0, 0 /* LOAD WORD */ 526 #define LDWM 0x13, 0x00, 0, 0 /* LOAD WORD and MODIFY */ 527 #define LDH 0x11, 0x00, 0, 0 /* LOAD HALFWORD */ 528 #define LDB 0x10, 0x00, 0, 0 /* LOAD BYTE */ 529 #define LDO 0x0d, 0x00, 0, 0 /* LOAD OFFSET */ 530 #define STW 0x1a, 0x00, 0, 0 /* STORE WORD */ 531 #define STWM 0x1b, 0x00, 0, 0 /* STORE WORD and MODIFY */ 532 #define STH 0x19, 0x00, 0, 0 /* STORE HALFWORD */ 533 #define STB 0x18, 0x00, 0, 0 /* STORE BYTE */ 534 #define LDWX 0x03, 0x02, 19, 7 /* LOAD WORD INDEXED */ 535 #define LDHX 0x03, 0x01, 19, 7 /* LOAD HALFWORD INDEXED */ 536 #define LDBX 0x03, 0x00, 19, 7 /* LOAD BYTE INDEXED */ 537 #define LDWAX 0x03, 0x06, 19, 7 /* LOAD WORD ABSOLUTE INDEXED */ 538 #define LDCWX 0x03, 0x07, 19, 7 /* LOAD and CLEAR WORD INDEXED */ 539 #define LDWS 0x03, 0x42, 19, 7 /* LOAD WORD SHORT DISP */ 540 #define LDHS 0x03, 0x41, 19, 7 /* LOAD HALFWORD SHORT DISP */ 541 #define LDBS 0x03, 0x40, 19, 7 /* LOAD BYTE SHORT DISP */ 542 #define LDWAS 0x03, 0x46, 19, 7 /* LOAD WORD ABSOLUTE SHORT DISP */ 543 #define LDCWS 0x03, 0x47, 19, 7 /* LOAD and CLEAR WORD SHORT DISP */ 544 #define STWS 0x03, 0x4a, 19, 7 /* STORE WORD SHORT DISP */ 545 #define STHS 0x03, 0x49, 19, 7 /* STORE HALFWORD SHORT DISP */ 546 #define STBS 0x03, 0x48, 19, 7 /* STORE BYTE SHORT DISP */ 547 #define STWAS 0x03, 0x4e, 19, 7 /* STORE WORD ABSOLUTE SHORT DISP */ 548 #define STBYS 0x03, 0x4c, 19, 7 /* STORE BYTES SHORT DISP */ 549 #define LDIL 0x08, 0x00, 0, 0 /* LOAD IMMED LEFT */ 550 #define ADDIL 0x0a, 0x00, 0, 0 /* ADD IMMED LEFT */ 551 #define BL 0x3a, 0x00, 16, 3 /* BRANCH [and LINK] */ 552 #define GATE 0x3a, 0x01, 16, 3 /* GATEWAY */ 553 #define BLR 0x3a, 0x02, 16, 3 /* BRANCH and LINK REGISTER */ 554 #define BV 0x3a, 0x06, 16, 3 /* BRANCH VECTORED */ 555 #define BE 0x38, 0x00, 0, 0 /* BRANCH EXTERNAL */ 556 #define BLE 0x39, 0x00, 0, 0 /* BRANCH and LINK EXTERNAL */ 557 #define MOVB 0x32, 0x00, 0, 0 /* MOVE and BRANCH */ 558 #define MOVIB 0x33, 0x00, 0, 0 /* MOVE IMMED and BRANCH */ 559 #define COMBT 0x20, 0x00, 0, 0 /* COMPARE and BRANCH if TRUE */ 560 #define COMBF 0x22, 0x00, 0, 0 /* COMPARE and BRANCH if FALSE */ 561 #define COMIBT 0x21, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if TRUE */ 562 #define COMIBF 0x23, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if FALSE */ 563 #define ADDBT 0x28, 0x00, 0, 0 /* ADD and BRANCH if TRUE */ 564 #define ADDBF 0x2a, 0x00, 0, 0 /* ADD and BRANCH if FALSE */ 565 #define ADDIBT 0x29, 0x00, 0, 0 /* ADD IMMED and BRANCH if TRUE */ 566 #define ADDIBF 0x2b, 0x00, 0, 0 /* ADD IMMED and BRANCH if FALSE */ 567 #define BVB 0x30, 0x00, 0, 0 /* BRANCH on VARIABLE BIT */ 568 #define BB 0x31, 0x00, 0, 0 /* BRANCH on BIT */ 569 #define ADD 0x02, 0x30, 20, 7 /* ADD */ 570 #define ADDL 0x02, 0x50, 20, 7 /* ADD LOGICAL */ 571 #define ADDO 0x02, 0x70, 20, 7 /* ADD and TRAP on OVFLO */ 572 #define SH1ADD 0x02, 0x32, 20, 7 /* SHIFT 1, ADD */ 573 #define SH1ADDL 0x02, 0x52, 20, 7 /* SHIFT 1, ADD LOGICAL */ 574 #define SH1ADDO 0x02, 0x72, 20, 7 /* SHIFT 1, ADD and TRAP on OVFLO */ 575 #define SH2ADD 0x02, 0x34, 20, 7 /* SHIFT 2, ADD */ 576 #define SH2ADDL 0x02, 0x54, 20, 7 /* SHIFT 2, ADD LOGICAL */ 577 #define SH2ADDO 0x02, 0x74, 20, 7 /* SHIFT 2, ADD and TRAP on OVFLO */ 578 #define SH3ADD 0x02, 0x36, 20, 7 /* SHIFT 3, ADD */ 579 #define SH3ADDL 0x02, 0x56, 20, 7 /* SHIFT 3, ADD LOGICAL */ 580 #define SH3ADDO 0x02, 0x76, 20, 7 /* SHIFT 3, ADD and TRAP on OVFLO */ 581 #define ADDC 0x02, 0x38, 20, 7 /* ADD with CARRY */ 582 #define ADDCO 0x02, 0x78, 20, 7 /* ADD with CARRY and TRAP on OVFLO */ 583 #define SUB 0x02, 0x20, 20, 7 /* SUBTRACT */ 584 #define SUBO 0x02, 0x60, 20, 7 /* SUBTRACT and TRAP on OVFLO */ 585 #define SUBB 0x02, 0x28, 20, 7 /* SUBTRACT with BORROW */ 586 #define SUBBO 0x02, 0x68, 20, 7 /* SUBTRACT with BORROW and TRAP on OVFLO */ 587 #define SUBT 0x02, 0x26, 20, 7 /* SUBTRACT and TRAP on COND */ 588 #define SUBTO 0x02, 0x66, 20, 7 /* SUBTRACT and TRAP on COND or OVFLO */ 589 #define DS 0x02, 0x22, 20, 7 /* DIVIDE STEP */ 590 #define COMCLR 0x02, 0x44, 20, 7 /* COMPARE and CLEAR */ 591 #define OR 0x02, 0x12, 20, 7 /* INCLUSIVE OR */ 592 #define XOR 0x02, 0x14, 20, 7 /* EXCLUSIVE OR */ 593 #define AND 0x02, 0x10, 20, 7 /* AND */ 594 #define ANDCM 0x02, 0x00, 20, 7 /* AND COMPLEMENT */ 595 #define UXOR 0x02, 0x1c, 20, 7 /* UNIT XOR */ 596 #define UADDCM 0x02, 0x4c, 20, 7 /* UNIT ADD COMPLEMENT */ 597 #define UADDCMT 0x02, 0x4e, 20, 7 /* UNIT ADD COMPLEMENT and TRAP on COND */ 598 #define DCOR 0x02, 0x5c, 20, 7 /* DECIMAL CORRECT */ 599 #define IDCOR 0x02, 0x5e, 20, 7 /* INTERMEDIATE DECIMAL CORRECT */ 600 #define ADDI 0x2d, 0x00, 20, 1 /* ADD to IMMED */ 601 #define ADDIO 0x2d, 0x01, 20, 1 /* ADD to IMMED and TRAP on OVFLO */ 602 #define ADDIT 0x2c, 0x00, 20, 1 /* ADD to IMMED and TRAP on COND */ 603 #define ADDITO 0x2c, 0x01, 20, 1 /* ADD to IMMED and TRAP on COND or OVFLO */ 604 #define SUBI 0x25, 0x00, 20, 1 /* SUBTRACT from IMMED */ 605 #define SUBIO 0x25, 0x01, 20, 1 /* SUBTRACT from IMMED and TRAP on OVFLO */ 606 #define COMICLR 0x24, 0x00, 0, 0 /* COMPARE IMMED and CLEAR */ 607 #define VSHD 0x34, 0x00, 19, 3 /* VARIABLE SHIFT DOUBLE */ 608 #define SHD 0x34, 0x02, 19, 3 /* SHIFT DOUBLE */ 609 #define VEXTRU 0x34, 0x04, 19, 3 /* VARIABLE EXTRACT RIGHT UNSIGNED */ 610 #define VEXTRS 0x34, 0x05, 19, 3 /* VARIABLE EXTRACT RIGHT SIGNED */ 611 #define EXTRU 0x34, 0x06, 19, 3 /* EXTRACT RIGHT UNSIGNED */ 612 #define EXTRS 0x34, 0x07, 19, 3 /* EXTRACT RIGHT SIGNED */ 613 #define VDEP 0x35, 0x01, 19, 3 /* VARIABLE DEPOSIT */ 614 #define DEP 0x35, 0x03, 19, 3 /* DEPOSIT */ 615 #define VDEPI 0x35, 0x05, 19, 3 /* VARIABLE DEPOSIT IMMED */ 616 #define DEPI 0x35, 0x07, 19, 3 /* DEPOSIT IMMED */ 617 #define ZVDEP 0x35, 0x00, 19, 3 /* ZERO and VARIABLE DEPOSIT */ 618 #define ZDEP 0x35, 0x02, 19, 3 /* ZERO and DEPOSIT */ 619 #define ZVDEPI 0x35, 0x04, 19, 3 /* ZERO and VARIABLE DEPOSIT IMMED */ 620 #define ZDEPI 0x35, 0x06, 19, 3 /* ZERO and DEPOSIT IMMED */ 621 #define BREAK 0x00, 0x00, 19, 8 /* BREAK */ 622 #define RFI 0x00, 0x60, 19, 8 /* RETURN FROM INTERRUPTION */ 623 #define RFIR 0x00, 0x65, 19, 8 /* RFI & RESTORE SHADOW REGISTERS */ 624 #define SSM 0x00, 0x6b, 19, 8 /* SET SYSTEM MASK */ 625 #define RSM 0x00, 0x73, 19, 8 /* RESET SYSTEM MASK */ 626 #define MTSM 0x00, 0xc3, 19, 8 /* MOVE TO SYSTEM MASK */ 627 #define LDSID 0x00, 0x85, 19, 8 /* LOAD SPACE IDENTIFIER */ 628 #define MTSP 0x00, 0xc1, 19, 8 /* MOVE TO SPACE REGISTER */ 629 #define MTCTL 0x00, 0xc2, 19, 8 /* MOVE TO SYSTEM CONTROL REGISTER */ 630 #define MFSP 0x00, 0x25, 19, 8 /* MOVE FROM SPACE REGISTER */ 631 #define MFCTL 0x00, 0x45, 19, 8 /* MOVE FROM SYSTEM CONTROL REGISTER */ 632 #define SYNC 0x00, 0x20, 19, 8 /* SYNCHRONIZE DATA CACHE */ 633 #define DIAG 0x05, 0x00, 0, 0 /* DIAGNOSE */ 634 #define SPOP 0x04, 0x00, 0, 0 /* SPECIAL FUNCTION UNIT */ 635 #define COPR 0x0c, 0x00, 0, 0 /* COPROCESSOR */ 636 #define CLDWX 0x09, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 637 #define CLDDX 0x0b, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 638 #define CSTWX 0x09, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 639 #define CSTDX 0x0b, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 640 #define CLDWS 0x09, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 641 #define CLDDS 0x0b, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 642 #define CSTWS 0x09, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 643 #define CSTDS 0x0b, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 644 #define FLOAT0 0x0e, 0x00, 21, 2 /* FLOATING POINT CLASS 0 */ 645 #define FLOAT1 0x0e, 0x01, 21, 2 /* FLOATING POINT CLASS 1 */ 646 #define FLOAT2 0x0e, 0x02, 21, 2 /* FLOATING POINT CLASS 2 */ 647 #define FLOAT3 0x0e, 0x03, 21, 2 /* FLOATING POINT CLASS 3 */ 648 #define FMPYSUB 0x26, 0x00, 0, 0 /* FP MULTIPLY AND SUBTRACT */ 649 #define FMPYADD 0x06, 0x00, 0, 0 /* FP MULTIPLY AND ADD/TRUNCATE */ 650 #define FSTQX 0x0f, 0x01, 19, 4 /* FLOATING POINT STORE QUAD INDEXED */ 651 #define FSTQS 0x0f, 0x09, 19, 4 /* FLOATING POINT STORE QUAD SHORT */ 652 /* all of the following have been pushed around to conform */ 653 #define PROBER 0x01, 0x46, 19, 7 /* PROBE READ ACCESS */ 654 #ifdef notdef 655 #define PROBERI 0x01, 0xc6, 19, 7 /* PROBE READ ACCESS IMMEDIATE */ 656 #endif 657 #define PROBEW 0x01, 0x47, 19, 7 /* PROBE WRITE ACCESS */ 658 #ifdef notdef 659 #define PROBEWI 0x01, 0xc7, 19, 7 /* PROBE WRITE ACCESS IMMEDIATE */ 660 #endif 661 #define LPA 0x01, 0x4d, 19, 7 /* LOAD PHYSICAL ADDRESS */ 662 #define LHA 0x01, 0x4c, 19, 7 /* LOAD HASH ADDRESS */ 663 #define PDTLB 0x01, 0x48, 19, 7 /* PURGE DATA TRANS LOOKASIDE BUFFER */ 664 #define PITLB 0x01, 0x08, 19, 7 /* PURGE INST TRANS LOOKASIDE BUFFER */ 665 #define PDTLBE 0x01, 0x49, 19, 7 /* PURGE DATA TLB ENTRY */ 666 #define PITLBE 0x01, 0x09, 19, 7 /* PURGE INST TLB ENTRY */ 667 #define IDTLBA 0x01, 0x41, 19, 7 /* INSERT DATA TLB ADDRESS */ 668 #define IITLBA 0x01, 0x01, 19, 7 /* INSERT INSTRUCTION TLB ADDRESS */ 669 #define IDTLBP 0x01, 0x40, 19, 7 /* INSERT DATA TLB PROTECTION */ 670 #define IITLBP 0x01, 0x00, 19, 7 /* INSERT INSTRUCTION TLB PROTECTION */ 671 #define PDC 0x01, 0x4e, 19, 7 /* PURGE DATA CACHE */ 672 #define FDC 0x01, 0x4a, 19, 7 /* FLUSH DATA CACHE */ 673 #define FIC 0x01, 0x0a, 19, 7 /* FLUSH INSTRUCTION CACHE */ 674 #define FDCE 0x01, 0x4b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 675 #define FICE 0x01, 0x0b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 676 677 /* 678 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 679 * 680 * Spectrum Simulator Instruction Set Constants and Datatypes 681 * Dan Magenheimer - 4/28/82 682 * Computer Research Center, Hewlett-Packard Labs 683 * 684 * (c) copyright 1982 685 * (p) protected 1982 686 * The Hewlett-Packard Company 687 * Hewlett-Packard Laboratories 688 * Computer Research Center 689 * Palo Alto, California 690 * 691 * *** HP Company Confidential *** 692 * 693 * Log: unasm.c,v 694 * Revision 1.5 1994/07/21 22:32:05 mike 695 * official HP copyright notice 696 * 697 * Revision 1.4 1992/07/08 12:19:52 dalton 698 * Checkin before split to 1.0.4 release (by LBS). 699 * 700 * Revision 1.3 92/06/06 16:16:45 dalton 701 * *** empty log message *** 702 * 703 * Revision 1.2 92/06/06 15:42:28 dalton 704 * Changed include to be a path relative to hp800. 705 * 706 * Revision 1.1 92/06/06 14:05:33 dalton 707 * Initial revision 708 * 709 * Revision 1.2 91/04/14 20:29:49 osfrcs 710 * Initial version. 711 * [91/03/30 09:20:34 brezak] 712 * 713 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 714 * Initial version. 715 * [91/03/30 09:20:34 brezak] 716 * 717 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 718 * Initial version. 719 * 720 ;Revision 1.1 88/07/11 14:05:21 14:05:21 ren (Bob Naas) 721 ;Initial revision 722 ; 723 * Revision 5.1 87/02/27 11:12:23 11:12:23 kent (Kent McMullen) 724 * update all src to 5.1 725 * 726 * Revision 5.0 87/02/18 16:31:52 16:31:52 kent (Kent McMullen) 727 * update all revision numbers to 5.0 for release 728 * 729 * Revision 1.1 86/07/15 08:35:00 08:35:00 kent (Kent McMullen) 730 * Initial revision 731 * 732 * Revision 4.3 85/11/12 09:28:44 09:28:44 viggy (Viggy Mokkarala) 733 * first mpsim version, partially stable 734 * 735 * Revision 4.2 84/07/16 17:20:57 17:20:57 djm () 736 * Define field macros for COPR and SFU insts 737 * 738 * Revision 4.1 83/10/25 17:10:14 djm (Daniel Magenheimer) 739 * First release for ACD v4 740 * 741 * Revision 3.1 83/08/03 14:09:59 djm (Daniel Magenheimer) 742 * Sys calls, args, -S, bug fixes, etc. 743 * 744 * Revision 3.0 83/06/13 10:25:13 djm (Daniel Magenheimer) 745 * First release for distribution 746 * 747 * 748 */ 749 /* 750 * Changes: 751 * 12/01/89 ejf Add Rsd(), Rse(), Rtd(), Rte() for 5 ops. 752 * 11/30/89 ejf Make instruction use counters shared, not per cpu. 753 * 11/28/89 ejf Change majoropcode for quicker extension extract. 754 */ 755 756 757 758 /* 759 * Dependencies: std.h, ssDefs.h, bits.h 760 */ 761 762 763 /* Lookup/Execute structure for instructions */ 764 struct inst { 765 u_char majopc; /* major opcode of instruction, 0..MAXOPC */ 766 u_char opcext; /* opcode extension, 0 if not applic. */ 767 u_char extbs; /* starting bit pos of extension field */ 768 u_char extbl; /* bit length of extension field */ 769 u_int count; /* frequency counter for analysis */ 770 char mnem[8]; /* ascii mnemonic */ 771 /* disassembly function */ 772 int (*dasmfcn)(const struct inst *, OFS, int); 773 }; 774 775 776 #define NMAJOPCS 64 777 778 struct majoropcode { 779 const struct inst **subops; /* pointer to table of subops indexed by 780 * opcode extension */ 781 u_int maxsubop; /* largest opcode extension value or 0 */ 782 u_int extshft; /* right shift amount for extension field */ 783 u_int extmask; /* post shift mask for extension field */ 784 }; 785 786 #define OpExt(i,m) ((i >> m->extshft) & m->extmask) /* extract opcode extension */ 787 788 789 /*****************************/ 790 /* Miscellaneous definitions */ 791 /*****************************/ 792 793 /* Load/Store Indexed Opcode Extension Cache Control */ 794 #define NOACTION 0 795 #define STACKREF 1 796 #define SEQPASS 2 797 #define PREFETCH 3 798 799 /******************************/ 800 /* Fields within instructions */ 801 /******************************/ 802 803 /* opcode */ 804 #define Opcode(i) BitfR(i,0,6,_b06) 805 /* opcode true/false bit */ 806 #define OpcTF(i) BitfR(i,4,1,_b41) 807 /* register sources */ 808 #define Rsa(i) BitfR(i,11,5,_b115) 809 #define Rsb(i) BitfR(i,6,5,_b65) 810 #define Rsc(i) BitfR(i,27,5,_b275) 811 #define Rsd(i) BitfR(i,21,5,_b215) 812 #define Rse(i) BitfR(i,16,5,_b165) 813 /* register targets */ 814 #define Rta(i) BitfR(i,11,5,_b115) 815 #define Rtb(i) BitfR(i,6,5,_b65) 816 #define Rtc(i) BitfR(i,27,5,_b275) 817 #define Rtd(i) BitfR(i,21,5,_b215) 818 #define Rte(i) BitfR(i,16,5,_b165) 819 /* 5-bit immediates (Magnitude, Sign) */ 820 #define Imb5(i) BitfR(i,6,5,_b65) 821 #define Ima5M(i) BitfR(i,11,4,_b114) 822 #define Ima5S(i) BitfR(i,15,1,_b151) 823 #define Ima5A(i) BitfR(i,11,5,_b115) 824 #define Imd5(i) BitfR(i,22,5,_b225) 825 #define Imc5M(i) BitfR(i,27,4,_b274) 826 #define Imc5S(i) BitfR(i,31,1,_b311) 827 #define Imc5A(i) BitfR(i,27,5,_b275) 828 /* Other immediates */ 829 #define Im21L(i) BitfR(i,18,2,_b182) 830 #define Im21H(i) BitfR(i,20,11,_b2011) 831 #define Im21M1(i) BitfR(i,16,2,_b162) 832 #define Im21M2(i) BitfR(i,11,5,_b115) 833 #define Im21S(i) BitfR(i,31,1,_b311) 834 #define Im11M(i) BitfR(i,21,10,_b2110) 835 #define Im11S(i) BitfR(i,31,1,_b311) 836 /* displacements/offsets */ 837 #define DispM(i) BitfR(i,18,13,_b1813) 838 #define DispS(i) BitfR(i,31,1,_b311) 839 #define Off5(i) BitfR(i,11,5,_b115) 840 #define Off11H(i) BitfR(i,19,10,_b1910) 841 #define Off11L(i) BitfR(i,29,1,_b291) 842 #define OffS(i) BitfR(i,31,1,_b311) 843 /* miscellaneous */ 844 #define Dss(i) BitfR(i,16,2,_b162) 845 #define Cond(i) BitfR(i,16,3,_b163) 846 #define Cneg(i) BitfR(i,19,1,_b191) 847 #define Cond4(i) BitfR(i,16,4,_b164) /* Cond AND Cneg */ 848 #define Nu(i) BitfR(i,30,1,_b301) 849 #define SrL(i) BitfR(i,16,2,_b162) 850 #define SrH(i) BitfR(i,18,1,_b181) 851 #define ShortDisp(i) BitfR(i,19,1,_b191) 852 #define IndxShft(i) BitfR(i,18,1,_b181) 853 #define ModBefore(i) BitfR(i,18,1,_b181) 854 #define CacheCtrl(i) BitfR(i,20,2,_b202) 855 #define Modify(i) BitfR(i,26,1,_b261) 856 #define ProbeI(i) BitfR(i,18,1,_b181) 857 #define Uid(i) BitfR(i,23,3,_b233) 858 #define Sfu(i) BitfR(i,23,3,_b233) 859 #define CopExt17(i) BitfR(i,6,17,_b617) 860 #define CopExt5(i) BitfR(i,27,5,_b275) 861 #define SpopType(i) BitfR(i,21,2,_b212) 862 #define SpopExt15(i) BitfR(i,6,15,_b615) 863 #define SpopExt10(i) BitfR(i,11,10,_b1110) 864 #define SpopExt5L(i) BitfR(i,16,5,_b165) 865 #define SpopExt5(i) BitfR(i,27,5,_b275) 866 #define NoMajOpc(i) BitfR(i,6,26,_b626) 867 #define Bi1(i) BitfR(i,27,5,_b275) /* fields in BREAK */ 868 #define Bi2(i) BitfR(i,6,13,_b613) 869 870 /* fragmented field collating macros */ 871 #define Ima5(i) (Ima5S(i) ? Ima5M(i) | (-1<<4) : Ima5M(i)) 872 873 #define Imc5(i) (Imc5S(i) ? Imc5M(i) | (-1<<4) : Imc5M(i)) 874 875 #define Disp(i) (DispS(i) ? DispM(i) | (-1<<13) : DispM(i)) 876 877 #define Im21(i) (Im21S(i) << 31 | Im21H(i) << 20 | Im21M1(i) << 18 | \ 878 Im21M2(i) << 13 | Im21L(i) << 11) 879 880 #define Im11(i) (Im11S(i) ? Im11M(i) | (-1<<10) : Im11M(i)) 881 882 #define Bdisp(i) ((OffS(i) ? (Off5(i)<<11 | Off11L(i)<<10|Off11H(i)) \ 883 /* branch displacement (bytes) */ | (-1 << 16) \ 884 : (Off5(i)<<11|Off11L(i)<<10|Off11H(i))) << 2) 885 886 #define Cbdisp(i) ((OffS(i) ? (Off11L(i) << 10 | Off11H(i)) \ 887 /* compare/branch disp (bytes) */ | (-1 << 11) \ 888 : Off11L(i) << 10 | Off11H(i)) << 2) 889 890 #define Sr(i) (SrH(i)<<2 | SrL(i)) 891 892 /* sfu/copr */ 893 #define CoprExt1(i) (CopExt17(i)) 894 #define CoprExt2(i) (CopExt5(i)) 895 #define CoprExt(i) ((CopExt17(i)<<5) | CopExt5(i)) 896 #define Spop0Ext(i) ((SpopExt15(i)<<5) | SpopExt5(i)) 897 #define Spop1Ext(i) (SpopExt15(i)) 898 #define Spop2Ext(i) ((SpopExt10(i)<<5) | SpopExt5(i)) 899 #define Spop3Ext(i) ((SpopExt5L(i)<<5) | SpopExt5(i)) 900 901 902 /*##################### Globals - Imports ##################################*/ 903 904 /* Disassembly functions */ 905 int fcoprDasm __P((int w, u_int op1, u_int)); 906 char *edDCond __P((u_int cond)); 907 char *unitDCond __P((u_int cond)); 908 char *addDCond __P((u_int cond)); 909 char *subDCond __P((u_int cond)); 910 int blDasm __P((const struct inst *i, OFS ofs, int w)); 911 int ldDasm __P((const struct inst *, OFS, int)); 912 int stDasm __P((const struct inst *i, OFS, int)); 913 int addDasm __P((const struct inst *i, OFS, int)); 914 int unitDasm __P((const struct inst *i, OFS, int)); 915 int iaDasm __P((const struct inst *i, OFS, int)); 916 int shdDasm __P((const struct inst *i, OFS, int)); 917 int extrDasm __P((const struct inst *i, OFS, int)); 918 int vextrDasm __P((const struct inst *i, OFS, int)); 919 int depDasm __P((const struct inst *i, OFS, int)); 920 int vdepDasm __P((const struct inst *i, OFS, int)); 921 int depiDasm __P((const struct inst *i, OFS, int)); 922 int vdepiDasm __P((const struct inst *i, OFS, int)); 923 int limmDasm __P((const struct inst *i, OFS, int)); 924 int brkDasm __P((const struct inst *i, OFS, int)); 925 int lpkDasm __P((const struct inst *i, OFS, int)); 926 int fmpyaddDasm __P((const struct inst *i, OFS, int)); 927 int fmpysubDasm __P((const struct inst *i, OFS, int)); 928 int floatDasm __P((const struct inst *i, OFS, int)); 929 int coprDasm __P((const struct inst *i, OFS, int)); 930 int diagDasm __P((const struct inst *i, OFS, int)); 931 int scDasm __P((const struct inst *i, OFS, int)); 932 int mmgtDasm __P((const struct inst *i, OFS, int)); 933 int ldxDasm __P((const struct inst *i, OFS, int)); 934 int stsDasm __P((const struct inst *i, OFS, int)); 935 int stbysDasm __P((const struct inst *i, OFS, int)); 936 int brDasm __P((const struct inst *i, OFS, int)); 937 int bvDasm __P((const struct inst *i, OFS, int)); 938 int beDasm __P((const struct inst *i, OFS, int)); 939 int cbDasm __P((const struct inst *i,OFS ofs, int)); 940 int cbiDasm __P((const struct inst *i,OFS ofs, int)); 941 int bbDasm __P((const struct inst *i,OFS ofs, int)); 942 int ariDasm __P((const struct inst *i, OFS, int)); 943 944 /*##################### Globals - Exports ##################################*/ 945 /*##################### Local Variables ####################################*/ 946 947 static const char fcoprUndef[] = "copr\t(rsvd or undef.)"; 948 static const char fmtStrTbl[][5] = { "sgl", "dbl", "sgl", "quad" }; 949 static const char condStrTbl[][7] = { 950 "false?", "false", "?", "!<=>", "=", "=t", "?=", "!<>", 951 "!?>=", "<", "?<", "!>=", "!?>", "<=", "?<=", "!>", 952 "!?<=", ">", "?>", "!<=", "!?<", ">=", "?>=", "!<", 953 "!?=", "<>", "!=", "!=t", "!?", "<=>", "true?", "true" 954 }; 955 static const char fsreg[][5] = { 956 "r0L", "r0R", "r1L", "r1R", "r2L", "r2R", "r3L", "r3R", 957 "r4L", "r4R", "r5L", "r5R", "r6L", "r6R", "r7L", "r7R", 958 "r8L", "r8R", "r9L", "r9R", "r10L", "r10R", "r11L", "r11R", 959 "r12L", "r12R", "r13L", "r13R", "r14L", "r14R", "r15L", "r15R", 960 "r16L", "r16R", "r17L", "r17R", "r18L", "r18R", "r19L", "r19R", 961 "r20L", "r20R", "r21L", "r21R", "r22L", "r22R", "r23L", "r23R", 962 "r24L", "r24R", "r25L", "r25R", "r26L", "r26R", "r27L", "r27R", 963 "r28L", "r28R", "r29L", "r29R", "r30L", "r30R", "r31L", "r31R" 964 }; 965 static const char fdreg[][4] = { 966 "r0", "r0", "r1", "r1", "r2", "r2", "r3", "r3", 967 "r4", "r4", "r5", "r5", "r6", "r6", "r7", "r7", 968 "r8", "r8", "r9", "r9", "r10", "r10", "r11", "r11", 969 "r12", "r12", "r13", "r13", "r14", "r14", "r15", "r15", 970 "r16", "r16", "r17", "r17", "r18", "r18", "r19", "r19", 971 "r20", "r20", "r21", "r21", "r22", "r22", "r23", "r23", 972 "r24", "r24", "r25", "r25", "r26", "r26", "r27", "r27", 973 "r28", "r28", "r29", "r29", "r30", "r30", "r31", "r31" 974 }; 975 976 /*##################### Macros #############################################*/ 977 978 #define Match(s) (strncmp(s,i->mnem,sizeof(s)-1) == 0) 979 980 /* bits for assist ops */ 981 #define AstNu(w) Modify(w) 982 #define Fpi(w) (Uid(w)>3) 983 984 /* bits for 5 ops */ 985 #define SinglePrec(i) Modify(i) 986 #define Ms1(i) ((Rsb(i)<<1)+(SinglePrec(i)?((Rsb(i)>15)?1:32):0)) 987 #define Ms2(i) ((Rsa(i)<<1)+(SinglePrec(i)?((Rsa(i)>15)?1:32):0)) 988 #define Mt(i) ((Rtc(i)<<1)+(SinglePrec(i)?((Rtc(i)>15)?1:32):0)) 989 #define As(i) ((Rsd(i)<<1)+(SinglePrec(i)?((Rsd(i)>15)?1:32):0)) 990 #define Ad(i) ((Rte(i)<<1)+(SinglePrec(i)?((Rte(i)>15)?1:32):0)) 991 992 /*##################### Globals - Exports ##################################*/ 993 994 /* To replace instr function, do the following: */ 995 /* a) locate the desired entry in instrs[] below */ 996 /* b) change the 3rd field if an alternate mneumonic is */ 997 /* desired for window disassembly */ 998 /* c) change the 4th field to the name of the function being */ 999 /* used for replacement (i.e. ldwRepl instead of ldw) */ 1000 /* d) change the 5th field if an alternate disassembly routine */ 1001 /* is desired (i.e. ldDasmRepl) */ 1002 1003 static const struct inst instrs[] = { 1004 { LDW, 0, "ldw", ldDasm }, 1005 { LDH, 0, "ldh", ldDasm }, 1006 { LDB, 0, "ldb", ldDasm }, 1007 { LDWM, 0, "ldwm", ldDasm }, 1008 { LDO, 0, "ldo", ldDasm }, 1009 { STW, 0, "stw", stDasm }, 1010 { STH, 0, "sth", stDasm }, 1011 { STB, 0, "stb", stDasm }, 1012 { STWM, 0, "stwm", stDasm }, 1013 { LDWX, 0, "ldw", ldxDasm }, 1014 { LDHX, 0, "ldh", ldxDasm }, 1015 { LDBX, 0, "ldb", ldxDasm }, 1016 { LDCWX, 0, "ldcw", ldxDasm }, 1017 { LDWAX, 0, "ldwa", ldxDasm }, 1018 { LDWS, 0, "ldw", ldxDasm }, 1019 { LDHS, 0, "ldh", ldxDasm }, 1020 { LDBS, 0, "ldb", ldxDasm }, 1021 { LDCWS, 0, "ldcw", ldxDasm }, 1022 { LDWAS, 0, "ldwa", ldxDasm }, 1023 { STWS, 0, "stws", stsDasm }, 1024 { STHS, 0, "sths", stsDasm }, 1025 { STBS, 0, "stbs", stsDasm }, 1026 { STWAS, 0, "stwas", stsDasm }, 1027 { STBYS, 0, "stbys", stbysDasm }, 1028 { LDIL, 0, "ldil", limmDasm }, 1029 { ADDIL, 0, "addil", limmDasm }, 1030 { GATE, 0, "gate", blDasm }, 1031 { BL, 0, "b", blDasm }, 1032 { BLR, 0, "blr", brDasm }, 1033 { BV, 0, "bv", bvDasm }, 1034 { BE, 0, "be", beDasm }, 1035 { BLE, 0, "ble", beDasm }, 1036 { COMBT, 0, "combt", cbDasm }, 1037 { COMBF, 0, "combf", cbDasm }, 1038 { COMIBT, 0, "comibt", cbiDasm }, 1039 { COMIBF, 0, "comibf", cbiDasm }, 1040 { ADDBT, 0, "addbt", cbDasm }, 1041 { ADDBF, 0, "addbf", cbDasm }, 1042 { ADDIBT, 0, "addibt", cbiDasm }, 1043 { ADDIBF, 0, "addibf", cbiDasm }, 1044 { MOVB, 0, "movb", cbDasm }, 1045 { MOVIB, 0, "movib", cbiDasm }, 1046 { BB, 0, "bb", bbDasm }, 1047 { BVB, 0, "bvb", bbDasm }, 1048 { SUBO, 0, "subo", ariDasm }, 1049 { ADD, 0, "add", addDasm }, 1050 { ADDL, 0, "addl", addDasm }, 1051 { ADDO, 0, "addo", ariDasm }, 1052 { SH1ADD, 0, "sh1add", ariDasm }, 1053 { SH1ADDL,0, "sh1addl", ariDasm }, 1054 { SH1ADDO,0, "sh1addo", ariDasm }, 1055 { SH2ADD, 0, "sh2add", ariDasm }, 1056 { SH2ADDL,0, "sh2addl", ariDasm }, 1057 { SH2ADDO,0, "sh2addo", ariDasm }, 1058 { SH3ADD, 0, "sh3add", ariDasm }, 1059 { SH3ADDL,0, "sh3addl", ariDasm }, 1060 { SH3ADDO,0, "sh3addo", ariDasm }, 1061 { SUB, 0, "sub", ariDasm }, 1062 { ADDCO, 0, "addco", ariDasm }, 1063 { SUBBO, 0, "subbo", ariDasm }, 1064 { ADDC, 0, "addc", ariDasm }, 1065 { SUBB, 0, "subb", ariDasm }, 1066 { COMCLR, 0, "comclr", ariDasm }, 1067 { OR, 0, "or", ariDasm }, 1068 { AND, 0, "and", ariDasm }, 1069 { XOR, 0, "xor", ariDasm }, 1070 { ANDCM, 0, "andcm", ariDasm }, 1071 { DS, 0, "ds", ariDasm }, 1072 { UXOR, 0, "uxor", unitDasm }, 1073 { UADDCM, 0, "uaddcm", unitDasm }, 1074 { UADDCMT,0, "uaddcmt", unitDasm }, 1075 { SUBTO, 0, "subto", ariDasm }, 1076 { SUBT, 0, "subt", ariDasm }, 1077 { DCOR, 0, "dcor", unitDasm }, 1078 { IDCOR, 0, "idcor", unitDasm }, 1079 { ADDIO, 0, "addio", iaDasm }, 1080 { SUBIO, 0, "subio", iaDasm }, 1081 { ADDI, 0, "addi", iaDasm }, 1082 { SUBI, 0, "subi", iaDasm }, 1083 { COMICLR,0, "comiclr", iaDasm }, 1084 { ADDITO, 0, "addito", iaDasm }, 1085 { ADDIT, 0, "addit", iaDasm }, 1086 { SHD, 0, "shd", shdDasm }, 1087 { VSHD, 0, "vshd", shdDasm }, 1088 { EXTRU, 0, "extru", extrDasm }, 1089 { EXTRS, 0, "extrs", extrDasm }, 1090 { VEXTRU, 0, "vextru", vextrDasm }, 1091 { VEXTRS, 0, "vextrs", vextrDasm }, 1092 { DEP, 0, "dep", depDasm }, 1093 { VDEP, 0, "vdep", vdepDasm }, 1094 { DEPI, 0, "depi", depiDasm }, 1095 { VDEPI, 0, "vdepi", vdepiDasm }, 1096 { ZDEP, 0, "zdep", depDasm }, 1097 { ZVDEP, 0, "zvdep", vdepDasm }, 1098 { ZDEPI, 0, "zdepi", depiDasm }, 1099 { ZVDEPI, 0, "zvdepi", vdepiDasm }, 1100 { BREAK, 0, "break", brkDasm }, 1101 { RFI, 0, "rfi", 0 }, 1102 { RFIR, 0, "rfir", 0 }, 1103 { SSM, 0, "ssm", scDasm }, 1104 { RSM, 0, "rsm", scDasm }, 1105 { MTSM, 0, "mtsm", scDasm }, 1106 { PROBER, 0, "prober", mmgtDasm }, 1107 { PROBEW, 0, "probew", mmgtDasm }, 1108 { LPA, 0, "lpa", mmgtDasm }, 1109 { LHA, 0, "lha", mmgtDasm }, 1110 { LDSID, 0, "ldsid", scDasm }, 1111 { PDTLB, 0, "pdtlb", mmgtDasm }, 1112 { PDTLBE, 0, "pdtlbe", mmgtDasm }, 1113 { PITLB, 0, "pitlb", mmgtDasm }, 1114 { PITLBE, 0, "pitlbe", mmgtDasm }, 1115 { IDTLBA, 0, "idtlba", mmgtDasm }, 1116 { IITLBA, 0, "iitlba", mmgtDasm }, 1117 { IDTLBP, 0, "idtlbp", mmgtDasm }, 1118 { IITLBP, 0, "iitlbp", mmgtDasm }, 1119 { FIC, 0, "fic", mmgtDasm }, 1120 { FICE, 0, "fice", mmgtDasm }, 1121 { PDC, 0, "pdc", mmgtDasm }, 1122 { FDC, 0, "fdc", mmgtDasm }, 1123 { FDCE, 0, "fdce", mmgtDasm }, 1124 { SYNC, 0, "sync", 0 }, 1125 { MTSP, 0, "mtsp", scDasm }, 1126 { MTCTL, 0, "mtctl", scDasm }, 1127 { MFSP, 0, "mfsp", scDasm }, 1128 { MFCTL, 0, "mfctl", scDasm }, 1129 { DIAG, 0, "diag", diagDasm }, 1130 { SPOP, 0, "???", 0 }, 1131 { COPR, 0, "copr", coprDasm }, 1132 { CLDWX, 0, "cldw", coprDasm }, 1133 { CLDDX, 0, "cldd", coprDasm }, 1134 { CSTWX, 0, "cstw", coprDasm }, 1135 { CSTDX, 0, "cstd", coprDasm }, 1136 { CLDWS, 0, "cldw", coprDasm }, 1137 { CLDDS, 0, "cldd", coprDasm }, 1138 { CSTWS, 0, "cstw", coprDasm }, 1139 { CSTDS, 0, "cstd", coprDasm }, 1140 { FLOAT0, 0, "f", floatDasm }, 1141 { FLOAT1, 0, "fcnv", floatDasm }, 1142 { FLOAT2, 0, "f", floatDasm }, 1143 { FLOAT3, 0, "f", floatDasm }, 1144 { FMPYSUB,0, "fmpy", fmpysubDasm }, 1145 { FMPYADD,0, "fmpy", fmpyaddDasm }, 1146 { FSTQX, 0, "fstqx", lpkDasm }, 1147 { FSTQS, 0, "fstqs", lpkDasm }, 1148 {0} 1149 }; 1150 1151 1152 static const struct inst illeg = { 0, 0, 0, 0, 0, "???", 0 }; 1153 static const struct inst *so_sysop[0xd0]; 1154 static const struct inst *so_mmuop[0x50]; 1155 static const struct inst *so_arith[0x80]; 1156 static const struct inst *so_loads[0x50]; 1157 static const struct inst *so_cldw [0x0A]; 1158 static const struct inst *so_cldd [0x0A]; 1159 static const struct inst *so_float[0x04]; 1160 static const struct inst *so_fstq [0x0A]; 1161 static const struct inst *so_ebran[0x08]; 1162 static const struct inst *so_addit[0x02]; 1163 static const struct inst *so_addi [0x02]; 1164 static const struct inst *so_subi [0x02]; 1165 static const struct inst *so_shext[0x08]; 1166 static const struct inst *so_deps [0x08]; 1167 1168 #define ILLEG (const struct inst **)&illeg 1169 #define NENTS(a) (sizeof(a)/sizeof(a[0])-1) 1170 static struct majoropcode majopcs[NMAJOPCS] = { 1171 { so_sysop, NENTS(so_sysop) }, /* 00 */ 1172 { so_mmuop, NENTS(so_mmuop) }, /* 01 */ 1173 { so_arith, NENTS(so_arith) }, /* 02 */ 1174 { so_loads, NENTS(so_loads) }, /* 03 */ 1175 { ILLEG, 1 }, /* 04 */ 1176 { ILLEG, 1 }, /* 05 */ 1177 { ILLEG, 1 }, /* 06 */ 1178 { ILLEG, 1 }, /* 07 */ 1179 { ILLEG, 1 }, /* 08 */ 1180 { so_cldw , NENTS(so_cldw ) }, /* 09 */ 1181 { ILLEG, 1 }, /* 0A */ 1182 { so_cldd , NENTS(so_cldd ) }, /* 0B */ 1183 { ILLEG, 1 }, /* 0C */ 1184 { ILLEG, 1 }, /* 0D */ 1185 { so_float, NENTS(so_float) }, /* 0E */ 1186 { so_fstq , NENTS(so_fstq ) }, /* 0F */ 1187 { ILLEG, 1 }, /* 10 */ 1188 { ILLEG, 1 }, /* 11 */ 1189 { ILLEG, 1 }, /* 12 */ 1190 { ILLEG, 1 }, /* 13 */ 1191 { ILLEG, 1 }, /* 14 */ 1192 { ILLEG, 1 }, /* 15 */ 1193 { ILLEG, 1 }, /* 16 */ 1194 { ILLEG, 1 }, /* 17 */ 1195 { ILLEG, 1 }, /* 18 */ 1196 { ILLEG, 1 }, /* 19 */ 1197 { ILLEG, 1 }, /* 1A */ 1198 { ILLEG, 1 }, /* 1B */ 1199 { ILLEG, 1 }, /* 1C */ 1200 { ILLEG, 1 }, /* 1D */ 1201 { ILLEG, 1 }, /* 1E */ 1202 { ILLEG, 1 }, /* 1F */ 1203 { ILLEG, 1 }, /* 20 */ 1204 { ILLEG, 1 }, /* 21 */ 1205 { ILLEG, 1 }, /* 22 */ 1206 { ILLEG, 1 }, /* 23 */ 1207 { ILLEG, 1 }, /* 24 */ 1208 { so_subi , NENTS(so_subi ) }, /* 25 */ 1209 { ILLEG, 1 }, /* 26 */ 1210 { ILLEG, 1 }, /* 27 */ 1211 { ILLEG, 1 }, /* 28 */ 1212 { ILLEG, 1 }, /* 29 */ 1213 { ILLEG, 1 }, /* 2A */ 1214 { ILLEG, 1 }, /* 2B */ 1215 { so_addit, NENTS(so_addit) }, /* 2C */ 1216 { so_addi , NENTS(so_addi ) }, /* 2D */ 1217 { ILLEG, 1 }, /* 2E */ 1218 { ILLEG, 1 }, /* 2F */ 1219 { ILLEG, 1 }, /* 30 */ 1220 { ILLEG, 1 }, /* 31 */ 1221 { ILLEG, 1 }, /* 32 */ 1222 { ILLEG, 1 }, /* 33 */ 1223 { so_shext, NENTS(so_shext) }, /* 34 */ 1224 { so_deps , NENTS(so_deps ) }, /* 35 */ 1225 { ILLEG, 1 }, /* 36 */ 1226 { ILLEG, 1 }, /* 37 */ 1227 { ILLEG, 1 }, /* 38 */ 1228 { ILLEG, 1 }, /* 39 */ 1229 { so_ebran, NENTS(so_ebran) }, /* 3A */ 1230 { ILLEG, 1 }, /* 3B */ 1231 { ILLEG, 1 }, /* 3C */ 1232 { ILLEG, 1 }, /* 3D */ 1233 { ILLEG, 1 }, /* 3E */ 1234 { ILLEG, 1 }, /* 3F */ 1235 }; 1236 #undef NENTS 1237 #undef ILLEG 1238 1239 /*-------------------------------------------------------------------------- 1240 * instruction$ExecutionInitialize - Initialize the instruction execution 1241 * data structures. 1242 *---------------------------------------------------------------------------*/ 1243 static int iExInit __P((void)); 1244 static int 1245 iExInit(void) 1246 { 1247 static int unasm_initted = 0; 1248 register const struct inst *i; 1249 register struct majoropcode *m; 1250 u_int shft, mask; 1251 1252 if (unasm_initted) 1253 return 0; 1254 1255 /* 1256 * Determine maxsubop for each major opcode. 1257 * Also, check all instructions of a given major opcode 1258 * for consistent opcode extension field definition, and 1259 * save a converted form of this definition in the majopcs 1260 * entry for this major opcode. 1261 */ 1262 for (i = &instrs[0]; *i->mnem; i++) { 1263 m = &majopcs[i->majopc]; 1264 if (m->maxsubop < i->opcext) 1265 panic("iExInit not enough space for opcode %d", 1266 i->majopc); 1267 shft = 32 - i->extbs - i->extbl; 1268 mask = (1 << i->extbl) - 1; 1269 if (m->extshft || m->extmask) { 1270 if (m->extshft != shft || m->extmask != mask) { 1271 db_printf("%s - Bad instruction initialization!\n", i->mnem); 1272 return (0); 1273 } 1274 } else { 1275 m->extshft = shft; 1276 m->extmask = mask; 1277 } 1278 } 1279 1280 /* 1281 * Lastly, fill in all legal subops with the appropriate info. 1282 */ 1283 for (i = &instrs[0]; *i->mnem; i++) { 1284 m = &majopcs[i->majopc]; 1285 if (m->maxsubop == 1) 1286 m->subops = (const struct inst **)i; 1287 else 1288 m->subops[i->opcext] = i; 1289 } 1290 1291 unasm_initted++; 1292 return (1); 1293 } 1294 1295 1296 1297 /*##################### Functions and Subroutines ##########################*/ 1298 1299 /**************************************/ 1300 /* Miscellaneous Disassembly Routines */ 1301 /**************************************/ 1302 1303 /* Add instructions */ 1304 int 1305 addDasm(i, ofs, w) 1306 const struct inst *i; 1307 OFS ofs; 1308 int w; 1309 { 1310 db_printf("%s\t%%r%d,%%r%d,%%r%d",addDCond(Cond4(w)), 1311 Rsa(w),Rsb(w),Rtc(w)); 1312 return (1); 1313 } 1314 1315 /* Unit instructions */ 1316 int 1317 unitDasm(i, ofs, w) 1318 const struct inst *i; 1319 OFS ofs; 1320 int w; 1321 { 1322 db_printf(unitDCond(Cond4(w))); 1323 if (Match("dcor") || Match("idcor")) 1324 db_printf("\t%%r%d,%%r%d",Rsb(w),Rtc(w)); 1325 else 1326 db_printf("\t%%r%d,%%r%d,%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1327 return (1); 1328 } 1329 1330 /* Immediate Arithmetic instructions */ 1331 int 1332 iaDasm(i, ofs, w) 1333 const struct inst *i; 1334 OFS ofs; 1335 int w; 1336 { 1337 if (Match("addi")) 1338 db_printf("%s\t%d,%%r%d,%%r%d", 1339 addDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1340 else 1341 db_printf("%s\t%d,%%r%d,%%r%d", 1342 subDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1343 return (1); 1344 } 1345 1346 /* Shift double instructions */ 1347 int 1348 shdDasm(i, ofs, w) 1349 const struct inst *i; 1350 OFS ofs; 1351 int w; 1352 { 1353 if (Match("vshd")) 1354 db_printf("%s\t%%r%d,%%r%d,%%r%d", 1355 edDCond(Cond(w)), Rsa(w),Rsb(w),Rtc(w)); 1356 else 1357 db_printf("%s\t%%r%d,%%r%d,%d,%%r%d", 1358 edDCond(Cond(w)),Rsa(w),Rsb(w),31-Imd5(w),Rtc(w)); 1359 return (1); 1360 } 1361 1362 /* Extract instructions */ 1363 int 1364 extrDasm(i, ofs, w) 1365 const struct inst *i; 1366 OFS ofs; 1367 int w; 1368 { 1369 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1370 edDCond(Cond(w)),Rsb(w),Imd5(w),32 - Rsc(w),Rta(w)); 1371 return (1); 1372 } 1373 1374 1375 /* Variable extract instructions */ 1376 int 1377 vextrDasm(i, ofs, w) 1378 const struct inst *i; 1379 OFS ofs; 1380 int w; 1381 { 1382 db_printf("%s\t%%r%d,%d,%%r%d", 1383 edDCond(Cond(w)),Rsb(w),32 - Rsc(w),Rta(w)); 1384 return (1); 1385 } 1386 1387 1388 /* Deposit instructions */ 1389 int 1390 depDasm(i, ofs, w) 1391 const struct inst *i; 1392 OFS ofs; 1393 int w; 1394 { 1395 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1396 edDCond(Cond(w)),Rsa(w),31 - Imd5(w),32 - Rsc(w),Rtb(w)); 1397 return (1); 1398 } 1399 1400 1401 /* Variable deposit instructions */ 1402 int 1403 vdepDasm(i, ofs, w) 1404 const struct inst *i; 1405 OFS ofs; 1406 int w; 1407 { 1408 db_printf("%s\t%%r%d,%d,%%r%d", 1409 edDCond(Cond(w)),Rsa(w),32 - Rsc(w),Rtb(w)); 1410 return (1); 1411 } 1412 1413 1414 /* Deposit Immediate instructions */ 1415 int 1416 depiDasm(i, ofs, w) 1417 const struct inst *i; 1418 OFS ofs; 1419 int w; 1420 { 1421 db_printf("%s\t%d,%d,%d,%%r%d", 1422 edDCond(Cond(w)),Ima5(w),31 - Imd5(w),32 - Imc5A(w),Rtb(w)); 1423 return (1); 1424 } 1425 1426 /* Variable Deposit Immediate instructions */ 1427 int 1428 vdepiDasm(i, ofs, w) 1429 const struct inst *i; 1430 OFS ofs; 1431 int w; 1432 { 1433 db_printf("%s\t%d,%d,%%r%d",edDCond(Cond(w)),Ima5(w),32-Imc5A(w),Rtb(w)); 1434 return (1); 1435 } 1436 1437 /*--------------------------------------------------------------------------- 1438 * conditionType$DisassembleCondition - Return a string which contains the 1439 * ascii description of the passed numeric condition. 1440 *---------------------------------------------------------------------------*/ 1441 1442 char * 1443 subDCond(cond) 1444 u_int cond; 1445 { 1446 switch(cond) { 1447 case EQZ: return(",="); 1448 case LT: return(",<"); 1449 case LE: return(",<="); 1450 case LLT: return(",<<"); 1451 case LLE: return(",<<="); 1452 case SV: return(",sv"); 1453 case OD: return(",od"); 1454 case NEQZ: return(",<>"); 1455 case GE: return(",>="); 1456 case GT: return(",>"); 1457 case LGE: return(",>>="); 1458 case LGT: return(",>>"); 1459 case NSV: return(",nsv"); 1460 case EV: return(",ev"); 1461 case TR: return(",tr"); 1462 case NEV: return(""); 1463 default: 1464 panic("subDCond: unknown condition"); 1465 } 1466 } 1467 1468 1469 /*--------------------------------------------------------------------------- 1470 * conditionType$DisassembleCondition - Return a string which contains the 1471 * ascii description of the passed numeric condition. 1472 *---------------------------------------------------------------------------*/ 1473 1474 char * 1475 addDCond(cond) 1476 u_int cond; 1477 { 1478 switch(cond) { 1479 case EQZ: return(",="); 1480 case LT: return(",<"); 1481 case LE: return(",<="); 1482 case NUV: return(",nuv"); 1483 case ZNV: return(",znv"); 1484 case SV: return(",sv"); 1485 case OD: return(",od"); 1486 case NEQZ: return(",<>"); 1487 case GE: return(",>="); 1488 case GT: return(",>"); 1489 case UV: return(",uv"); 1490 case VNZ: return(",vnz"); 1491 case NSV: return(",nsv"); 1492 case EV: return(",ev"); 1493 case TR: return(",tr"); 1494 case NEV: return(""); 1495 default: 1496 panic("addDCond: unknown condition"); 1497 } 1498 } 1499 1500 char * 1501 unitDCond(cond) 1502 u_int cond; 1503 { 1504 switch(cond) { 1505 case SHC: return(",shc"); 1506 case SHZ: return(",shz"); 1507 case SBC: return(",sbc"); 1508 case SBZ: return(",sbz"); 1509 case SDC: return(",sdc"); 1510 case NHC: return(",nhc"); 1511 case NHZ: return(",nhz"); 1512 case NBC: return(",nbc"); 1513 case NBZ: return(",nbz"); 1514 case NDC: return(",ndc"); 1515 case TR: return(",tr"); 1516 case NEV: return(""); 1517 default: 1518 panic("unitDCond: unknown condition"); 1519 } 1520 } 1521 1522 char * 1523 edDCond(cond) 1524 u_int cond; 1525 { 1526 switch(cond) { 1527 case XOD: return(",od"); 1528 case XTR: return(",tr"); 1529 case XNE: return(",<>"); 1530 case XLT: return(",<"); 1531 case XEQ: return(",="); 1532 case XGE: return(",>="); 1533 case XEV: return(",ev"); 1534 case NEV: return(""); 1535 default: 1536 panic("edDCond: unknown condition"); 1537 } 1538 } 1539 1540 1541 1542 /****************************************/ 1543 /* Format Specific Disassembly Routines */ 1544 /****************************************/ 1545 1546 1547 /* Load [modify] instructions */ 1548 int 1549 ldDasm(i, ofs, w) 1550 const struct inst *i; 1551 OFS ofs; 1552 int w; 1553 { 1554 register int d = Disp(w); 1555 char s[2]; 1556 1557 s[1] = '\0'; 1558 if (d < 0) { 1559 d = -d; 1560 s[0] = '-'; 1561 } else 1562 s[0] = '\0'; 1563 1564 if (Rsb(w) == 0 && Match("ldo")) { 1565 db_printf("ldi\t%s%X,%%r%d",s,d,Rta(w)); 1566 return (1); 1567 } 1568 db_printf("%s\t%s%s%X",i->mnem,(d < 2048? "R'":""), s, d); 1569 if (Dss(w)) 1570 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rta(w)); 1571 else 1572 db_printf("(%%r%d),%%r%d",Rsb(w),Rta(w)); 1573 return (1); 1574 } 1575 1576 /* Store [modify] instructions */ 1577 int 1578 stDasm(i, ofs, w) 1579 const struct inst *i; 1580 OFS ofs; 1581 int w; 1582 { 1583 register int d = Disp(w); 1584 char s[2]; 1585 1586 db_printf("\t%%r%d,",Rta(w)); 1587 1588 s[1] = '\0'; 1589 if (d < 0) { 1590 d = -d; 1591 s[0] = '-'; 1592 } else 1593 s[0] = '\0'; 1594 1595 db_printf("%s%s%X", (d < 2048? "R'":""), s, d); 1596 1597 if (Dss(w)) 1598 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 1599 else 1600 db_printf("(%%r%d)",Rsb(w)); 1601 return (1); 1602 } 1603 1604 /* Load indexed instructions */ 1605 int 1606 ldxDasm(i, ofs, w) 1607 const struct inst *i; 1608 OFS ofs; 1609 int w; 1610 { 1611 register const char *p; 1612 1613 if (ShortDisp(w)) { 1614 db_printf("s"); 1615 if (Modify(w)) 1616 db_printf(",m%s", ModBefore(w)? "b": "a"); 1617 } else { 1618 db_printf("x"); 1619 if (Modify(w)) 1620 db_printf(",%sm", IndxShft(w)? "s":""); 1621 } 1622 switch (CacheCtrl(w)) { 1623 case NOACTION: p = ""; break; 1624 case STACKREF: p = ",c"; break; 1625 case SEQPASS: p = ",q"; break; 1626 case PREFETCH: p = ",p"; break; 1627 } 1628 if (ShortDisp(w)) 1629 db_printf("%s\t%d", p, Ima5(w)); 1630 else 1631 db_printf("%s\t%%r%d", p, Rsa(w)); 1632 1633 if (Dss(w)) 1634 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1635 else 1636 db_printf("(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1637 return (1); 1638 } 1639 1640 /* Store short displacement instructions */ 1641 int 1642 stsDasm(i, ofs, w) 1643 const struct inst *i; 1644 OFS ofs; 1645 int w; 1646 { 1647 register const char *p; 1648 if (Modify(w)) 1649 db_printf(",m%s", ModBefore(w)? "b":"a"); 1650 1651 switch (CacheCtrl(w)) { 1652 case NOACTION: p = ""; break; 1653 case STACKREF: p = ",c"; break; 1654 case SEQPASS: p = ",q"; break; 1655 case PREFETCH: p = ",p"; break; 1656 } 1657 db_printf("%s\t%%r%d,", p, Rta(w)); 1658 if (Dss(w)) 1659 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1660 else 1661 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1662 return (1); 1663 } 1664 1665 /* Store Bytes Instruction */ 1666 int 1667 stbysDasm(i, ofs, w) 1668 const struct inst *i; 1669 OFS ofs; 1670 int w; 1671 { 1672 register const char *p; 1673 db_printf(ModBefore(w)? ",e":",b"); 1674 if (Modify(w)) 1675 db_printf(",m"); 1676 switch (CacheCtrl(w)) { 1677 case NOACTION: p = ""; break; 1678 case STACKREF: p = ",f"; break; 1679 case SEQPASS: p = ",r"; break; 1680 case PREFETCH: p = ",z"; break; 1681 } 1682 db_printf("%s\t%%r%d,", p, Rta(w)); 1683 if (Dss(w)) 1684 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1685 else 1686 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1687 return (1); 1688 } 1689 1690 /* Long Immediate instructions */ 1691 int 1692 limmDasm(i, ofs, w) 1693 const struct inst *i; 1694 OFS ofs; 1695 int w; 1696 { 1697 db_printf("\tL'%X,%%r%d", Im21(w), Rtb(w)); 1698 return (1); 1699 } 1700 1701 1702 /* Branch and Link instruction(s) (Branch, too!!) */ 1703 int 1704 blDasm(i, ofs, w) 1705 const struct inst *i; 1706 OFS ofs; 1707 int w; 1708 { 1709 register OFS tgtofs = ofs + 8 + Bdisp(w); 1710 register u_int link = Rtb(w); 1711 1712 if (link && !Match("gate")) 1713 db_printf("l"); 1714 if (Nu(w)) 1715 db_printf(",n"); 1716 db_printf("\t"); 1717 1718 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1719 1720 if (link || Match("gate")) 1721 db_printf(",%%r%d",link); 1722 1723 return (1); 1724 } 1725 1726 /* Branch Register instruction */ 1727 int 1728 brDasm(i, ofs, w) 1729 const struct inst *i; 1730 OFS ofs; 1731 int w; 1732 { 1733 db_printf("%s\t%%r%d,%%r%d", Nu(w)?",n":"", Rsa(w), Rtb(w)); 1734 return (1); 1735 } 1736 1737 /* Dispatch instructions */ 1738 int 1739 bvDasm(i, ofs, w) 1740 const struct inst *i; 1741 OFS ofs; 1742 int w; 1743 { 1744 db_printf("%s\t%%r%d(%%r%d)", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1745 return (1); 1746 } 1747 1748 /* Branch External instructions */ 1749 int 1750 beDasm(i, ofs, w) 1751 const struct inst *i; 1752 OFS ofs; 1753 int w; 1754 { 1755 register int d = Bdisp(w); 1756 register const char *p; 1757 char s[2]; 1758 1759 s[1] = '\0'; 1760 if (d < 0) { 1761 d = -d; 1762 s[0] = '-'; 1763 } else 1764 s[0] = '\0'; 1765 1766 p = Nu(w)? ",n":""; 1767 db_printf("%s\tR'%s%X(%%sr%d,%%r%d)", p, 1768 s, d, Sr(w), Rsb(w)); 1769 return (1); 1770 } 1771 1772 1773 /* Compare/Add and Branch instructions */ 1774 int 1775 cbDasm(i, ofs, w) 1776 const struct inst *i; 1777 OFS ofs; 1778 int w; 1779 { 1780 register OFS tgtofs = ofs + 8 + Cbdisp(w); 1781 1782 if (Match("movb")) 1783 db_printf(edDCond(Cond(w))); 1784 else if (Match("addb")) 1785 db_printf(addDCond(Cond(w) << 1)); 1786 else 1787 db_printf(subDCond(Cond(w) << 1)); 1788 db_printf("%s\t%%r%d,%%r%d,", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1789 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1790 return (1); 1791 } 1792 1793 /* Compare/Add and Branch Immediate instructions */ 1794 int 1795 cbiDasm(i, ofs, w) 1796 const struct inst *i; 1797 OFS ofs; 1798 int w; 1799 { 1800 register OFS tgtofs = ofs + 8 + Cbdisp(w); 1801 1802 if (Match("movib")) 1803 db_printf(edDCond(Cond(w))); 1804 else if (Match("addib")) 1805 db_printf(addDCond(Cond(w) << 1)); 1806 else 1807 db_printf(subDCond(Cond(w) << 1)); 1808 db_printf("%s\t%d,%%r%d,", Nu(w)? ",n":"", Ima5(w), Rsb(w)); 1809 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1810 return (1); 1811 } 1812 1813 /* Branch on Bit instructions */ 1814 int 1815 bbDasm(i, ofs, w) 1816 const struct inst *i; 1817 OFS ofs; 1818 int w; 1819 { 1820 register OFS tgtofs = ofs + 8 + Cbdisp(w); 1821 register const char *p; 1822 1823 db_printf(edDCond(Cond(w))); 1824 p = Nu(w)? ",n":""; 1825 if (Match("bvb")) 1826 db_printf("%s\t%%r%d,", p, Rta(w)); 1827 else 1828 db_printf("%s\t%%r%d,%d,", p, Rsa(w), Imb5(w)); 1829 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1830 return (1); 1831 } 1832 1833 /* Arithmetic instructions */ 1834 int 1835 ariDasm(i, ofs, w) 1836 const struct inst *i; 1837 OFS ofs; 1838 int w; 1839 { 1840 if (Match("or") && Rsb(w) == 0 && Cond4(w) == NEV) { 1841 if (Rsa(w) == 0 && Rtc(w) == 0) 1842 db_printf("nop"); 1843 else 1844 db_printf("copy\t%%r%d,%%r%d",Rsa(w),Rtc(w)); 1845 } else 1846 db_printf("%s%s\t%%r%d,%%r%d,%%r%d", i->mnem, 1847 subDCond(Cond4(w)), Rsa(w),Rsb(w),Rtc(w)); 1848 return(1); 1849 } 1850 1851 /* System control operations */ 1852 int 1853 scDasm(i, ofs, w) 1854 const struct inst *i; 1855 OFS ofs; 1856 int w; 1857 { 1858 if (Match("mtctl")) { 1859 if (Rtb(w) == 11) 1860 db_printf("mtsar\t%%r%d",Rsa(w)); 1861 else 1862 db_printf("mtctl\t%%r%d,%%cr%d",Rsa(w),Rtb(w)); 1863 return (1); 1864 } 1865 db_printf(i->mnem); 1866 if (Match("ssm") || Match("rsm")) 1867 db_printf("\t%d,%%r%d",Ima5A(w),Rtc(w)); 1868 else if (Match("mtsm")) db_printf("\t%%r%d",Rsa(w)); 1869 else if (Match("ldprid")) db_printf("\t%%r%d",Rtc(w)); 1870 else if (Match("mtsp")) db_printf("\t%%r%d,%%sr%d",Rsa(w),Sr(w)); 1871 else if (Match("mfsp")) db_printf("\t%%sr%d,%%r%d",Sr(w),Rtc(w)); 1872 else if (Match("mfctl")) db_printf("\t%%cr%d,%%r%d",Rsb(w),Rtc(w)); 1873 else if (Match("ldsid")) { 1874 if (Dss(w)) 1875 db_printf("\t(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1876 else 1877 db_printf("\t(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1878 } else { 1879 db_printf("?????"); 1880 return (0); 1881 } 1882 return (1); 1883 } 1884 1885 /* Instruction cache/tlb control instructions */ 1886 int 1887 mmgtDasm(i, ofs, w) 1888 const struct inst *i; 1889 OFS ofs; 1890 int w; 1891 { 1892 if (Match("probe")) { 1893 if (ProbeI(w)) { 1894 if (Dss(w)) 1895 db_printf("i\t(%%sr%d,%%r%d),%d,%%r%d", 1896 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1897 else 1898 db_printf("i\t(%%r%d),%d,%%r%d", 1899 Rsb(w),Rsa(w),Rtc(w)); 1900 } else { 1901 if (Dss(w)) 1902 db_printf("\t(%%sr%d,%%r%d),%%r%d,%%r%d", 1903 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1904 else 1905 db_printf("\t(%%r%d),%%r%d,%%r%d", 1906 Rsb(w),Rsa(w),Rtc(w)); 1907 } 1908 } 1909 else if (Match("lha") || Match("lpa")) { 1910 if (Modify(w)) 1911 db_printf(",m"); 1912 if (Dss(w)) 1913 db_printf("\t%%r%d(%%sr%d,%%r%d),%%r%d", 1914 Rsa(w),Dss(w),Rsb(w),Rtc(w)); 1915 else 1916 db_printf("\t%%r%d(%%r%d),%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1917 } 1918 else if (Match("pdtlb") || Match("pdc") || Match("fdc")) { 1919 if (Modify(w)) db_printf(",m"); 1920 if (Dss(w)) 1921 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1922 else 1923 db_printf("\t%%r%d(%%r%d)",Rsa(w),Rsb(w)); 1924 } 1925 else if (Match("pitlb") || Match("fic")) { 1926 if (Modify(w)) 1927 db_printf(",m"); 1928 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1929 } 1930 else if (Match("idtlb")) { 1931 if (Dss(w)) 1932 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1933 else 1934 db_printf("\t%%r%d,(%%r%d)",Rsa(w),Rsb(w)); 1935 } 1936 else if (Match("iitlb")) 1937 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1938 else { 1939 db_printf("?????"); 1940 return (0); 1941 } 1942 return(1); 1943 } 1944 1945 /* break instruction */ 1946 int 1947 brkDasm(i, ofs, w) 1948 const struct inst *i; 1949 OFS ofs; 1950 int w; 1951 { 1952 db_printf("\t%d,%d",Bi1(w),Bi2(w)); 1953 return (1); 1954 } 1955 1956 int 1957 floatDasm(i, ofs, w) 1958 const struct inst *i; 1959 OFS ofs; 1960 int w; 1961 { 1962 register u_int op1, r1, fmt, t; 1963 u_int op2, r2, dfmt; 1964 char *p; 1965 1966 op1 = CoprExt1(w); 1967 op2 = CoprExt2(w); 1968 fmt = (op1 >> 2) & 3; /* get precision of source */ 1969 1970 #define ST(r) ((fmt & 1)? fdreg[(r)]:fsreg[(r)]) 1971 /* 1972 * get first (or only) source register 1973 * (independent of class) 1974 */ 1975 r1 = (op1 >> 11) & 0x3e; 1976 if ((fmt & 1) == 0 && (Uid(w) & 2)) 1977 r1++; 1978 1979 if (op1 & 2) { /* class 2 or 3 */ 1980 /* 1981 * get second source register 1982 */ 1983 r2 = (op1 >> 6) & 0x3e; 1984 if (fmt == 2) 1985 r2++; 1986 1987 if ((op1 & 1) == 0) { /* class 2 */ 1988 /* Opclass 2: 2 sources, no destination */ 1989 switch((op1 >> 4) & 7) { 1990 case 0: 1991 p = "cmp"; 1992 break; 1993 default: 1994 db_printf(fcoprUndef); 1995 return(0); 1996 } 1997 db_printf("%s,%s",p,fmtStrTbl[fmt]); 1998 db_printf(",%s\t%%f%s,%%f%s", 1999 condStrTbl[op2], ST(r1), ST(r2)); 2000 return (1); 2001 } 2002 /* 2003 * get target register (class 3) 2004 */ 2005 t = (op2 << 1); 2006 if ((fmt & 1) == 0 && (Uid(w) & 1)) 2007 t++; 2008 /* Opclass 3: 2 sources, 1 destination */ 2009 switch((op1 >> 4) & 7) { 2010 case 0: p = "add"; break; 2011 case 1: p = "sub"; break; 2012 case 2: p = (Fpi(w)) ? "mpyi" : "mpy"; break; 2013 case 3: p = "div"; break; 2014 case 4: p = "rem"; break; 2015 default: db_printf(fcoprUndef); return (0); 2016 } 2017 db_printf("%s,%s", p, fmtStrTbl[fmt]); 2018 db_printf("\t%%f%s,%%f%s,%%f%s",ST(r1),ST(r2),ST(t)); 2019 } else if (op1 & 1) { /* class 1 */ 2020 dfmt = (op1 >> 4) & 3; 2021 #define DT(r) ((dfmt & 1)? fdreg[(r)]:fsreg[(r)]) 2022 2023 /* 2024 * get target register 2025 */ 2026 t = (op2 << 1); 2027 if ((dfmt & 1) == 0 && (Uid(w) & 1)) 2028 t++; 2029 /* Opclass 1: 1 source, 1 destination conversions */ 2030 switch((op1 >> 6) & 3) { 2031 case 0: p = "ff"; break; 2032 case 1: p = "xf"; break; 2033 case 2: p = "fx"; break; 2034 case 3: p = "fxt"; break; 2035 } 2036 db_printf("%s,%s", p, fmtStrTbl[fmt]); 2037 db_printf(",%s\t%%f%s,%%f%s",fmtStrTbl[dfmt],ST(r1),DT(t)); 2038 } else { /* class 0 */ 2039 /* 2040 * get target register 2041 */ 2042 t = (op2 << 1); 2043 if ((fmt & 1) == 0 && (Uid(w) & 1)) 2044 t++; 2045 /* Opclass 0: 1 source, 1 destination */ 2046 switch((op1 >> 4) & 7) { 2047 case 1: p = "rsqrt"; break; 2048 case 2: p = "cpy"; break; 2049 case 3: p = "abs"; break; 2050 case 4: p = "sqrt"; break; 2051 case 5: p = "rnd"; break; 2052 default: db_printf(fcoprUndef); return (0); 2053 } 2054 db_printf("%s,%s",p,fmtStrTbl[fmt]); 2055 db_printf("\t%%f%s,%%f%s",ST(r1),ST(t)); 2056 } 2057 return (1); 2058 } 2059 2060 int 2061 fcoprDasm(w, op1, op2) 2062 int w; 2063 u_int op1, op2; 2064 { 2065 register u_int r1, r2, t, fmt, dfmt; 2066 register char *p; 2067 2068 if (AstNu(w) && op1 == ((1<<4) | 2)) { 2069 if (op2 == 0 || op2 == 1 || op2 == 2) { 2070 db_printf("ftest"); 2071 if (op2 == 1) 2072 db_printf(",acc"); 2073 else if (op2 == 2) 2074 db_printf(",rej"); 2075 return (1); 2076 } 2077 return (0); 2078 } else if (0 == op1 && 0 == op2) { 2079 db_printf("fcopr identify"); 2080 return (1); 2081 } 2082 switch(op1 & 3) { 2083 case 0: 2084 /* Opclass 0: 1 source, 1 destination */ 2085 r1 = (op1 >> 12) & 0x1f; t = op2; fmt = (op1 >> 2) & 3; 2086 switch((op1 >> 4) & 7) { 2087 case 1: p = "rsqrt"; break; 2088 case 2: p = "cpy"; break; 2089 case 3: p = "abs"; break; 2090 case 4: p = "sqrt"; break; 2091 case 5: p = "rnd"; break; 2092 default: db_printf(fcoprUndef); return(0); 2093 } 2094 db_printf("f%s,%s\t%%fr%d,%%fr%d", p, fmtStrTbl[fmt], r1, t); 2095 break; 2096 case 1: 2097 /* Opclass 1: 1 source, 1 destination conversions */ 2098 r1 = (op1 >> 12) & 0x1f; t = op2; 2099 fmt = (op1 >> 2) & 3; dfmt = (op1 >> 4) & 3; 2100 switch((op1 >> 6) & 3) { 2101 case 0: p = "ff"; break; 2102 case 1: p = "xf"; break; 2103 case 2: p = "fx"; break; 2104 case 3: p = "fxt"; break; 2105 } 2106 db_printf("fcnv%s,%s,%s\t%%fr%d,%%fr%d", 2107 p, fmtStrTbl[fmt], fmtStrTbl[dfmt], r1, t); 2108 break; 2109 case 2: 2110 /* Opclass 2: 2 sources, no destination */ 2111 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; 2112 fmt = (op1 >> 2) & 3; 2113 switch((op1 >> 4) & 7) { 2114 case 0: p = "fcmp"; break; 2115 default: db_printf(fcoprUndef); return (0); 2116 } 2117 db_printf("%s,%s,%s\t%%fr%d,%%fr%d", 2118 p,fmtStrTbl[fmt],condStrTbl[op2],r1,r2); 2119 break; 2120 case 3: 2121 /* Opclass 3: 2 sources, 1 destination */ 2122 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; t = op2; 2123 fmt = (op1 >> 2) & 3; 2124 switch((op1 >> 4) & 7) { 2125 case 0: p = "add"; break; 2126 case 1: p = "sub"; break; 2127 case 2: p = "mpy"; break; 2128 case 3: p = "div"; break; 2129 case 4: p = "rem"; break; 2130 default: db_printf(fcoprUndef); return (0); 2131 } 2132 db_printf("f%s,%s\t%%fr%d,%%fr%d,%%fr%d", 2133 p, fmtStrTbl[fmt], r1, r2, t); 2134 break; 2135 default: 2136 db_printf(fcoprUndef); 2137 return(0); 2138 } 2139 return (1); 2140 } 2141 2142 int 2143 coprDasm(i, ofs, w) 2144 const struct inst *i; 2145 OFS ofs; 2146 int w; 2147 { 2148 register u_int uid = Uid(w); 2149 register int load = 0; 2150 register char *pfx = uid > 1 ? "c" : "f"; 2151 register int dreg; 2152 2153 if (Match("copr")) { 2154 if (uid) { 2155 db_printf("copr,%d,0x%x",uid,CoprExt(w)); 2156 if (AstNu(w)) 2157 db_printf(",n"); 2158 return (1); 2159 } 2160 return fcoprDasm(w, CoprExt1(w),CoprExt2(w)); 2161 } 2162 if (Match("cldd")) { 2163 dreg = 1; 2164 load = 1; 2165 db_printf("%sldd",pfx); 2166 } else if (Match("cldw")) { 2167 load = 1; 2168 db_printf("%sldw",pfx); 2169 } else if (Match("cstd")) { 2170 dreg = 1; 2171 db_printf("%sstd",pfx); 2172 } else if (Match("cstw")) 2173 db_printf("%sstw",pfx); 2174 else { 2175 db_printf("copr???"); 2176 return (0); 2177 } 2178 if (ShortDisp(w)) { 2179 db_printf("s"); 2180 if (AstNu(w)) 2181 db_printf(",m%s", ModBefore(w)?"b":"a"); 2182 } 2183 else { 2184 db_printf("x"); 2185 if (AstNu(w)) 2186 db_printf(",%sm", IndxShft(w)?"s":""); 2187 else if (IndxShft(w)) 2188 db_printf(",s"); 2189 } 2190 switch (CacheCtrl(w)) { 2191 case NOACTION: break; 2192 case STACKREF: db_printf(",c"); break; 2193 case SEQPASS: db_printf(",q"); break; 2194 case PREFETCH: db_printf(",p"); break; 2195 } 2196 if (load) { 2197 register const char *p; 2198 2199 if (dreg) 2200 p = fdreg[(Rtc(w)<<1)+(uid&1)]; 2201 else 2202 p = fsreg[(Rtc(w)<<1)+(uid&1)]; 2203 2204 if (ShortDisp(w)) 2205 db_printf("\t%d",Ima5(w)); 2206 else 2207 db_printf("\t%%r%d",Rsa(w)); 2208 if (Dss(w)) 2209 db_printf("(%%sr%d,%%r%d),%%f%s", Dss(w),Rsb(w), p); 2210 else 2211 db_printf("(%%r%d),%%f%s",Rsb(w), p); 2212 } else { 2213 register const char *p; 2214 2215 if (dreg) 2216 p = fdreg[(Rsc(w)<<1)+(uid&1)]; 2217 else 2218 p = fsreg[(Rsc(w)<<1)+(uid&1)]; 2219 2220 if (ShortDisp(w)) 2221 db_printf("\t%%f%s,%d", p, Ima5(w)); 2222 else 2223 db_printf("\t%%f%s,%%r%d", p, Rta(w)); 2224 if (Dss(w)) 2225 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2226 else 2227 db_printf("(%%r%d)",Rsb(w)); 2228 } 2229 return (1); 2230 } 2231 2232 int 2233 lpkDasm(i, ofs, w) 2234 const struct inst *i; 2235 OFS ofs; 2236 int w; 2237 { 2238 /* 2239 * Floating point STore Quad 2240 * Short or Indexed 2241 */ 2242 if (ShortDisp(w)) { 2243 if (Modify(w)) 2244 db_printf(",m%s", ModBefore(w)?"b":"a"); 2245 } else { 2246 if (Modify(w)) 2247 db_printf(",%sm", IndxShft(w)? "s":""); 2248 else if (IndxShft(w)) 2249 db_printf(",s"); 2250 } 2251 switch (CacheCtrl(w)) { 2252 case NOACTION: break; 2253 case STACKREF: db_printf(",c"); break; 2254 case SEQPASS: db_printf(",q"); break; 2255 case PREFETCH: db_printf(",p"); break; 2256 } 2257 if (ShortDisp(w)) 2258 db_printf("\t%%fr%d,%d",Rsc(w),Ima5(w)); 2259 else 2260 db_printf("\t%%fr%d,%%r%d",Rsc(w),Rta(w)); 2261 if (Dss(w)) 2262 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2263 else 2264 db_printf("(%%r%d)",Rsb(w)); 2265 return (1); 2266 } 2267 2268 int 2269 diagDasm(i, ofs, w) 2270 const struct inst *i; 2271 OFS ofs; 2272 int w; 2273 { 2274 if (0x0b0 == BitfR(w,19,8,_b198)) /* mtcpu */ 2275 db_printf("mtcpu\t%%r%d,%%dr%d", Rsa(w), Rtb(w)); 2276 else if (0x0d0 == BitfR(w,19,8,_b198)) /* mfcpu */ 2277 db_printf("mfcpu\t%%dr%d,%%r%d", Rsb(w), Rta(w)); 2278 else { 2279 db_printf(i->mnem); 2280 if (Match("diag")) 2281 db_printf("\t0x%X",w & 0x03ffffff); 2282 else { 2283 db_printf("?????"); 2284 return (0); 2285 } 2286 } 2287 return (1); 2288 } 2289 2290 int 2291 fmpysubDasm(i, ofs, w) 2292 const struct inst *i; 2293 OFS ofs; 2294 int w; 2295 { 2296 if (SinglePrec(w)) 2297 db_printf("SUB,SGL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2298 fsreg[Ms1(w)], fsreg[Ms2(w)], fsreg[Mt(w)], 2299 fsreg[As(w)], fsreg[Ad(w)]); 2300 else 2301 db_printf("SUB,DBL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2302 fdreg[Ms1(w)], fdreg[Ms2(w)], fdreg[Mt(w)], 2303 fdreg[As(w)], fdreg[Ad(w)]); 2304 return (1); 2305 } 2306 2307 int 2308 fmpyaddDasm(i, ofs, w) 2309 const struct inst *i; 2310 OFS ofs; 2311 int w; 2312 { 2313 register const char 2314 *ms1 = SinglePrec(w) ? fsreg[Ms1(w)] : fdreg[Ms1(w)], 2315 *ms2 = SinglePrec(w) ? fsreg[Ms2(w)] : fdreg[Ms2(w)], 2316 *mt = SinglePrec(w) ? fsreg[Mt(w)] : fdreg[Mt(w)], 2317 *as = SinglePrec(w) ? fsreg[As(w)] : fdreg[As(w)], 2318 *ad = SinglePrec(w) ? fsreg[Ad(w)] : fdreg[Ad(w)]; 2319 2320 if (Rsd(w) == 0) 2321 db_printf("\t%%fcfxt,%s,%%f%s,%%f%s,%%f%s", 2322 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt); 2323 else 2324 db_printf("add%s\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2325 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt, as, ad); 2326 2327 return (1); 2328 } 2329 2330 vaddr_t 2331 db_disasm(loc, flag) 2332 vaddr_t loc; 2333 boolean_t flag; 2334 { 2335 register const struct inst *i; 2336 register const struct majoropcode *m; 2337 register u_int ext; 2338 int instruct; 2339 OFS ofs = 0; 2340 2341 iExInit(); 2342 2343 if (USERMODE(loc)) { 2344 if (copyin((caddr_t)(loc &~ HPPA_PC_PRIV_MASK), 2345 &instruct, sizeof(instruct))) 2346 instruct = 0; 2347 } else 2348 instruct = *(int *)loc; 2349 2350 m = &majopcs[Opcode(instruct)]; 2351 ext = OpExt(instruct, m); 2352 if (ext <= m->maxsubop) { 2353 /* special hack for majopcs table layout */ 2354 if (m->maxsubop == 1) 2355 i = (const struct inst *)m->subops; 2356 else 2357 i = m->subops[ext]; 2358 2359 if (i->dasmfcn != coprDasm && i->dasmfcn != diagDasm && 2360 i->dasmfcn != ariDasm && i->dasmfcn != scDasm && 2361 i->dasmfcn != ldDasm) 2362 db_printf(i->mnem); 2363 if (i->dasmfcn) 2364 (*i->dasmfcn)(i, ofs, instruct); 2365 else if (i->mnem[0] == '?') 2366 db_printf(illeg.mnem); 2367 } else 2368 db_printf(illeg.mnem); 2369 2370 db_printf("\n"); 2371 return (loc + sizeof(instruct)); 2372 } 2373