1 /* $NetBSD: machdep.c,v 1.506 2002/12/07 15:36:20 junyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 42 * All rights reserved. 43 * 44 * This code is derived from software contributed to Berkeley by 45 * William Jolitz. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. All advertising materials mentioning features or use of this software 56 * must display the following acknowledgement: 57 * This product includes software developed by the University of 58 * California, Berkeley and its contributors. 59 * 4. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.506 2002/12/07 15:36:20 junyoung Exp $"); 80 81 #include "opt_cputype.h" 82 #include "opt_ddb.h" 83 #include "opt_ipkdb.h" 84 #include "opt_kgdb.h" 85 #include "opt_vm86.h" 86 #include "opt_user_ldt.h" 87 #include "opt_compat_netbsd.h" 88 #include "opt_cpureset_delay.h" 89 #include "opt_compat_svr4.h" 90 #include "opt_realmem.h" 91 #include "opt_compat_mach.h" /* need to get the right segment def */ 92 #include "opt_mtrr.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/signalvar.h> 97 #include <sys/kernel.h> 98 #include <sys/proc.h> 99 #include <sys/user.h> 100 #include <sys/exec.h> 101 #include <sys/buf.h> 102 #include <sys/reboot.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/malloc.h> 106 #include <sys/mbuf.h> 107 #include <sys/msgbuf.h> 108 #include <sys/mount.h> 109 #include <sys/vnode.h> 110 #include <sys/extent.h> 111 #include <sys/syscallargs.h> 112 #include <sys/core.h> 113 #include <sys/kcore.h> 114 #include <machine/kcore.h> 115 116 #ifdef IPKDB 117 #include <ipkdb/ipkdb.h> 118 #endif 119 120 #ifdef KGDB 121 #include <sys/kgdb.h> 122 #endif 123 124 #include <dev/cons.h> 125 126 #include <uvm/uvm_extern.h> 127 #include <uvm/uvm_page.h> 128 129 #include <sys/sysctl.h> 130 131 #include <machine/cpu.h> 132 #include <machine/cpufunc.h> 133 #include <machine/cpuvar.h> 134 #include <machine/gdt.h> 135 #include <machine/pio.h> 136 #include <machine/psl.h> 137 #include <machine/reg.h> 138 #include <machine/specialreg.h> 139 #include <machine/bootinfo.h> 140 #include <machine/mtrr.h> 141 142 #include <dev/isa/isareg.h> 143 #include <machine/isa_machdep.h> 144 #include <dev/ic/i8042reg.h> 145 146 #ifdef DDB 147 #include <machine/db_machdep.h> 148 #include <ddb/db_extern.h> 149 #endif 150 151 #ifdef VM86 152 #include <machine/vm86.h> 153 #endif 154 155 #include "acpi.h" 156 #include "apm.h" 157 #include "bioscall.h" 158 159 #if NBIOSCALL > 0 160 #include <machine/bioscall.h> 161 #endif 162 163 #if NACPI > 0 164 #include <dev/acpi/acpivar.h> 165 #define ACPI_MACHDEP_PRIVATE 166 #include <machine/acpi_machdep.h> 167 #endif 168 169 #if NAPM > 0 170 #include <machine/apmvar.h> 171 #endif 172 173 #include "isa.h" 174 #include "isadma.h" 175 #include "npx.h" 176 177 #include "mca.h" 178 #if NMCA > 0 179 #include <machine/mca_machdep.h> /* for mca_busprobe() */ 180 #endif 181 182 #ifdef MULTIPROCESSOR /* XXX */ 183 #include <machine/mpbiosvar.h> /* XXX */ 184 #endif /* XXX */ 185 186 /* the following is used externally (sysctl_hw) */ 187 char machine[] = "i386"; /* cpu "architecture" */ 188 char machine_arch[] = "i386"; /* machine == machine_arch */ 189 190 volatile u_int32_t ipending; 191 192 int imasks[NIPL]; 193 int iunmask[NIPL]; 194 195 u_int cpu_serial[3]; 196 197 char bootinfo[BOOTINFO_MAXSIZE]; 198 199 /* Our exported CPU info; we have only one right now. */ 200 struct cpu_info cpu_info_store; 201 202 struct bi_devmatch *i386_alldisks = NULL; 203 int i386_ndisks = 0; 204 205 #ifdef CPURESET_DELAY 206 int cpureset_delay = CPURESET_DELAY; 207 #else 208 int cpureset_delay = 2000; /* default to 2s */ 209 #endif 210 211 #ifdef MTRR 212 struct mtrr_funcs *mtrr_funcs; 213 #endif 214 215 int physmem; 216 int dumpmem_low; 217 int dumpmem_high; 218 int cpu_class; 219 int i386_fpu_present; 220 int i386_fpu_exception; 221 int i386_fpu_fdivbug; 222 223 int i386_use_fxsave; 224 int i386_has_sse; 225 int i386_has_sse2; 226 227 int tmx86_has_longrun; 228 229 vaddr_t msgbuf_vaddr; 230 paddr_t msgbuf_paddr; 231 232 vaddr_t idt_vaddr; 233 paddr_t idt_paddr; 234 235 #ifdef I586_CPU 236 vaddr_t pentium_idt_vaddr; 237 #endif 238 239 struct vm_map *exec_map = NULL; 240 struct vm_map *mb_map = NULL; 241 struct vm_map *phys_map = NULL; 242 243 extern paddr_t avail_start, avail_end; 244 245 void (*delay_func) __P((int)) = i8254_delay; 246 void (*microtime_func) __P((struct timeval *)) = i8254_microtime; 247 void (*initclock_func) __P((void)) = i8254_initclocks; 248 249 /* 250 * Size of memory segments, before any memory is stolen. 251 */ 252 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 253 int mem_cluster_cnt; 254 255 int cpu_dump __P((void)); 256 int cpu_dumpsize __P((void)); 257 u_long cpu_dump_mempagecnt __P((void)); 258 void dumpsys __P((void)); 259 void init386 __P((paddr_t)); 260 void initgdt __P((union descriptor *)); 261 262 #if !defined(REALBASEMEM) && !defined(REALEXTMEM) 263 void add_mem_cluster __P((u_int64_t, u_int64_t, u_int32_t)); 264 #endif /* !defnied(REALBASEMEM) && !defined(REALEXTMEM) */ 265 266 static const struct i386_cache_info 267 intel_cpuid_cache_info[] = { 268 { CAI_ITLB, 0x01, 4, 32, 4 * 1024 }, 269 { CAI_ITLB2, 0x02, 0xff, 2, 4 * 1024 * 1024 }, 270 { CAI_DTLB, 0x03, 4, 64, 4 * 1024 }, 271 { CAI_DTLB2, 0x04, 4, 8, 4 * 1024 * 1024 }, 272 { CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries" }, 273 { CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries" }, 274 { CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries" }, 275 { CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries" }, 276 { CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries" }, 277 { CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries" }, 278 279 { CAI_ICACHE, 0x06, 4, 8 * 1024, 32 }, 280 { CAI_ICACHE, 0x08, 4, 16 * 1024, 32 }, 281 { CAI_DCACHE, 0x0a, 2, 8 * 1024, 32 }, 282 { CAI_DCACHE, 0x0c, 4, 16 * 1024, 32 }, 283 { CAI_L2CACHE, 0x40, 0, 0, 0, "not present" }, 284 { CAI_L2CACHE, 0x41, 4, 128 * 1024, 32 }, 285 { CAI_L2CACHE, 0x42, 4, 256 * 1024, 32 }, 286 { CAI_L2CACHE, 0x43, 4, 512 * 1024, 32 }, 287 { CAI_L2CACHE, 0x44, 4, 1 * 1024 * 1024, 32 }, 288 { CAI_L2CACHE, 0x45, 4, 2 * 1024 * 1024, 32 }, 289 { CAI_DCACHE, 0x66, 4, 8 * 1024, 64 }, 290 { CAI_DCACHE, 0x67, 4, 16 * 1024, 64 }, 291 { CAI_DCACHE, 0x68, 4, 32 * 1024, 64 }, 292 { CAI_ICACHE, 0x70, 8, 12 * 1024, 64, "12K uOp cache"}, 293 { CAI_ICACHE, 0x71, 8, 16 * 1024, 64, "16K uOp cache"}, 294 { CAI_ICACHE, 0x72, 8, 32 * 1024, 64, "32K uOp cache"}, 295 { CAI_L2CACHE, 0x79, 8, 128 * 1024, 64 }, 296 { CAI_L2CACHE, 0x7a, 8, 256 * 1024, 64 }, 297 { CAI_L2CACHE, 0x7b, 8, 512 * 1024, 64 }, 298 { CAI_L2CACHE, 0x7c, 8, 1 * 1024 * 1024, 64 }, 299 { CAI_L2CACHE, 0x82, 8, 256 * 1024, 32 }, 300 { CAI_L2CACHE, 0x83, 8, 512 * 1024, 32 }, 301 { CAI_L2CACHE, 0x84, 8, 1 * 1024 * 1024, 32 }, 302 { CAI_L2CACHE, 0x85, 8, 2 * 1024 * 1024, 32 }, 303 { 0, 0, 0, 0, 0 }, 304 }; 305 306 static const struct i386_cache_info * 307 cache_info_lookup(const struct i386_cache_info *cai, u_int8_t desc); 308 309 /* 310 * Map Brand ID from cpuid instruction to brand name. 311 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 312 */ 313 static const char * const i386_intel_brand[] = { 314 "", /* Unsupported */ 315 "Celeron", /* Intel (R) Celeron (TM) processor */ 316 "Pentium III", /* Intel (R) Pentium (R) III processor */ 317 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 318 "Pentium III", /* Intel (R) Pentium (R) III processor */ 319 "", /* Reserved */ 320 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 321 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 322 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 323 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 324 "Celeron", /* Intel (R) Celeron (TM) processor */ 325 "Xeon", /* Intel (R) Xeon (TM) processor */ 326 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 327 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 328 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 329 }; 330 331 /* 332 * AMD processors don't have Brand IDs, so we need these names for probe. 333 */ 334 static const char * const amd_brand[] = { 335 "", 336 "Duron", /* AMD Duron(tm) */ 337 "MP", /* AMD Athlon(tm) MP */ 338 "XP", /* AMD Athlon(tm) XP */ 339 "4" /* AMD Athlon(tm) 4 */ 340 }; 341 342 static char amd_brand_name[48]; 343 344 #ifdef COMPAT_NOMID 345 static int exec_nomid __P((struct proc *, struct exec_package *)); 346 #endif 347 348 void cyrix6x86_cpu_setup __P((struct cpu_info *)); 349 void winchip_cpu_setup __P((struct cpu_info *)); 350 void amd_family5_setup __P((struct cpu_info *)); 351 void transmeta_cpu_setup __P((struct cpu_info *)); 352 353 static void via_cpu_probe __P((struct cpu_info *)); 354 static void amd_family6_probe __P((struct cpu_info *)); 355 356 static const char *intel_family6_name __P((struct cpu_info *)); 357 358 static void transmeta_cpu_info __P((struct cpu_info *)); 359 static void amd_cpu_cacheinfo __P((struct cpu_info *)); 360 361 static __inline u_char 362 cyrix_read_reg(u_char reg) 363 { 364 outb(0x22, reg); 365 return inb(0x23); 366 } 367 368 static __inline void 369 cyrix_write_reg(u_char reg, u_char data) 370 { 371 outb(0x22, reg); 372 outb(0x23, data); 373 } 374 375 static char * 376 print_cache_config(struct cpu_info *ci, int cache_tag, char *name, char *sep) 377 { 378 char cbuf[7]; 379 struct i386_cache_info *cai = &ci->ci_cinfo[cache_tag]; 380 381 if (cai->cai_totalsize == 0) 382 return sep; 383 384 if (sep == NULL) 385 printf("%s: ", ci->ci_dev->dv_xname); 386 else 387 printf("%s", sep); 388 if (name != NULL) 389 printf("%s ", name); 390 391 if (cai->cai_string != NULL) { 392 printf("%s ", cai->cai_string); 393 } else { 394 format_bytes(cbuf, sizeof(cbuf), cai->cai_totalsize); 395 printf("%s %db/line ", cbuf, cai->cai_linesize); 396 } 397 switch (cai->cai_associativity) { 398 case 0: 399 printf("disabled"); 400 break; 401 case 1: 402 printf("direct-mapped"); 403 break; 404 case 0xff: 405 printf("fully associative"); 406 break; 407 default: 408 printf("%d-way", cai->cai_associativity); 409 break; 410 } 411 return ", "; 412 } 413 414 static char * 415 print_tlb_config(struct cpu_info *ci, int cache_tag, char *name, char *sep) 416 { 417 char cbuf[7]; 418 struct i386_cache_info *cai = &ci->ci_cinfo[cache_tag]; 419 420 if (cai->cai_totalsize == 0) 421 return sep; 422 423 if (sep == NULL) 424 printf("%s: ", ci->ci_dev->dv_xname); 425 else 426 printf("%s", sep); 427 if (name != NULL) 428 printf("%s ", name); 429 430 if (cai->cai_string != NULL) { 431 printf("%s", cai->cai_string); 432 } else { 433 format_bytes(cbuf, sizeof(cbuf), cai->cai_linesize); 434 printf("%d %s entries ", cai->cai_totalsize, cbuf); 435 switch (cai->cai_associativity) { 436 case 0: 437 printf("disabled"); 438 break; 439 case 1: 440 printf("direct-mapped"); 441 break; 442 case 0xff: 443 printf("fully associative"); 444 break; 445 default: 446 printf("%d-way", cai->cai_associativity); 447 break; 448 } 449 } 450 return ", "; 451 } 452 453 /* 454 * Machine-dependent startup code 455 */ 456 void 457 cpu_startup() 458 { 459 #if 0 460 struct cpu_info *ci = curcpu(); 461 #endif 462 caddr_t v; 463 int sz, x; 464 vaddr_t minaddr, maxaddr; 465 vsize_t size; 466 char pbuf[9]; 467 #if 0 468 int bigcache, cachesize; 469 #endif 470 471 /* 472 * Initialize error message buffer (et end of core). 473 */ 474 msgbuf_vaddr = uvm_km_valloc(kernel_map, i386_round_page(MSGBUFSIZE)); 475 if (msgbuf_vaddr == 0) 476 panic("failed to valloc msgbuf_vaddr"); 477 478 /* msgbuf_paddr was init'd in pmap */ 479 for (x = 0; x < btoc(MSGBUFSIZE); x++) 480 pmap_kenter_pa((vaddr_t)msgbuf_vaddr + x * PAGE_SIZE, 481 msgbuf_paddr + x * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE); 482 pmap_update(pmap_kernel()); 483 484 initmsgbuf((caddr_t)msgbuf_vaddr, round_page(MSGBUFSIZE)); 485 486 printf("%s", version); 487 488 #ifdef TRAPLOG 489 /* 490 * Enable recording of branch from/to in MSR's 491 */ 492 wrmsr(MSR_DEBUGCTLMSR, 0x1); 493 #endif 494 495 format_bytes(pbuf, sizeof(pbuf), ptoa(physmem)); 496 printf("total memory = %s\n", pbuf); 497 498 /* 499 * Find out how much space we need, allocate it, 500 * and then give everything true virtual addresses. 501 */ 502 sz = (int)allocsys(NULL, NULL); 503 if ((v = (caddr_t)uvm_km_zalloc(kernel_map, round_page(sz))) == 0) 504 panic("startup: no room for tables"); 505 if (allocsys(v, NULL) - v != sz) 506 panic("startup: table size inconsistency"); 507 508 /* 509 * Allocate virtual address space for the buffers. The area 510 * is not managed by the VM system. 511 */ 512 size = MAXBSIZE * nbuf; 513 if (uvm_map(kernel_map, (vaddr_t *) &buffers, round_page(size), 514 NULL, UVM_UNKNOWN_OFFSET, 0, 515 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 516 UVM_ADV_NORMAL, 0)) != 0) 517 panic("cpu_startup: cannot allocate VM for buffers"); 518 minaddr = (vaddr_t)buffers; 519 if ((bufpages / nbuf) >= btoc(MAXBSIZE)) { 520 /* don't want to alloc more physical mem than needed */ 521 bufpages = btoc(MAXBSIZE) * nbuf; 522 } 523 524 /* 525 * XXX We defer allocation of physical pages for buffers until 526 * XXX after autoconfiguration has run. We must do this because 527 * XXX on system with large amounts of memory or with large 528 * XXX user-configured buffer caches, the buffer cache will eat 529 * XXX up all of the lower 16M of RAM. This prevents ISA DMA 530 * XXX maps from allocating bounce pages. 531 * 532 * XXX Note that nothing can use buffer cache buffers until after 533 * XXX autoconfiguration completes!! 534 * 535 * XXX This is a hack, and needs to be replaced with a better 536 * XXX solution! --thorpej@netbsd.org, December 6, 1997 537 */ 538 539 /* 540 * Allocate a submap for exec arguments. This map effectively 541 * limits the number of processes exec'ing at any time. 542 */ 543 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 544 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 545 546 /* 547 * Allocate a submap for physio 548 */ 549 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 550 VM_PHYS_SIZE, 0, FALSE, NULL); 551 552 /* 553 * Finally, allocate mbuf cluster submap. 554 */ 555 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 556 nmbclusters * mclbytes, VM_MAP_INTRSAFE, FALSE, NULL); 557 558 /* 559 * XXX Buffer cache pages haven't yet been allocated, so 560 * XXX we need to account for those pages when printing 561 * XXX the amount of free memory. 562 */ 563 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free - bufpages)); 564 printf("avail memory = %s\n", pbuf); 565 format_bytes(pbuf, sizeof(pbuf), bufpages * PAGE_SIZE); 566 printf("using %d buffers containing %s of memory\n", nbuf, pbuf); 567 568 /* Safe for i/o port / memory space allocation to use malloc now. */ 569 i386_bus_space_mallocok(); 570 } 571 572 /* 573 * Set up proc0's TSS and LDT. 574 */ 575 void 576 i386_proc0_tss_ldt_init() 577 { 578 struct pcb *pcb; 579 int x; 580 581 gdt_init(); 582 583 cpu_info_primary.ci_curpcb = pcb = &proc0.p_addr->u_pcb; 584 585 pcb->pcb_tss.tss_ioopt = 586 ((caddr_t)pcb->pcb_iomap - (caddr_t)&pcb->pcb_tss) << 16; 587 588 for (x = 0; x < sizeof(pcb->pcb_iomap) / 4; x++) 589 pcb->pcb_iomap[x] = 0xffffffff; 590 591 pcb->pcb_ldt_sel = pmap_kernel()->pm_ldt_sel = GSEL(GLDT_SEL, SEL_KPL); 592 pcb->pcb_cr0 = rcr0(); 593 pcb->pcb_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 594 pcb->pcb_tss.tss_esp0 = (int)proc0.p_addr + USPACE - 16; 595 proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_tss.tss_esp0 - 1; 596 proc0.p_md.md_tss_sel = tss_alloc(pcb); 597 598 ltr(proc0.p_md.md_tss_sel); 599 lldt(pcb->pcb_ldt_sel); 600 } 601 602 /* 603 * Set up TSS and LDT for a new PCB. 604 */ 605 606 void 607 i386_init_pcb_tss_ldt(ci) 608 struct cpu_info *ci; 609 { 610 int x; 611 struct pcb *pcb = ci->ci_idle_pcb; 612 613 pcb->pcb_tss.tss_ioopt = 614 ((caddr_t)pcb->pcb_iomap - (caddr_t)&pcb->pcb_tss) << 16; 615 for (x = 0; x < sizeof(pcb->pcb_iomap) / 4; x++) 616 pcb->pcb_iomap[x] = 0xffffffff; 617 618 pcb->pcb_ldt_sel = pmap_kernel()->pm_ldt_sel = GSEL(GLDT_SEL, SEL_KPL); 619 pcb->pcb_cr0 = rcr0(); 620 621 ci->ci_idle_tss_sel = tss_alloc(pcb); 622 } 623 624 /* 625 * XXX Finish up the deferred buffer cache allocation and initialization. 626 */ 627 void 628 i386_bufinit() 629 { 630 int i, base, residual; 631 632 base = bufpages / nbuf; 633 residual = bufpages % nbuf; 634 for (i = 0; i < nbuf; i++) { 635 vsize_t curbufsize; 636 vaddr_t curbuf; 637 struct vm_page *pg; 638 639 /* 640 * Each buffer has MAXBSIZE bytes of VM space allocated. Of 641 * that MAXBSIZE space, we allocate and map (base+1) pages 642 * for the first "residual" buffers, and then we allocate 643 * "base" pages for the rest. 644 */ 645 curbuf = (vaddr_t) buffers + (i * MAXBSIZE); 646 curbufsize = PAGE_SIZE * ((i < residual) ? (base+1) : base); 647 648 while (curbufsize) { 649 /* 650 * Attempt to allocate buffers from the first 651 * 16M of RAM to avoid bouncing file system 652 * transfers. 653 */ 654 pg = uvm_pagealloc_strat(NULL, 0, NULL, 0, 655 UVM_PGA_STRAT_FALLBACK, VM_FREELIST_FIRST16); 656 if (pg == NULL) 657 panic("cpu_startup: not enough memory for " 658 "buffer cache"); 659 pmap_kenter_pa(curbuf, VM_PAGE_TO_PHYS(pg), 660 VM_PROT_READ|VM_PROT_WRITE); 661 curbuf += PAGE_SIZE; 662 curbufsize -= PAGE_SIZE; 663 } 664 } 665 pmap_update(pmap_kernel()); 666 667 /* 668 * Set up buffers, so they can be used to read disk labels. 669 */ 670 bufinit(); 671 } 672 673 /* 674 * Info for CTL_HW 675 */ 676 char cpu_model[120]; 677 678 /* 679 * Note: these are just the ones that may not have a cpuid instruction. 680 * We deal with the rest in a different way. 681 */ 682 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 683 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 684 NULL, NULL}, /* CPU_386SX */ 685 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 686 NULL, NULL}, /* CPU_386 */ 687 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 688 NULL, NULL}, /* CPU_486SX */ 689 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 690 NULL, NULL}, /* CPU_486 */ 691 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 692 NULL, NULL}, /* CPU_486DLC */ 693 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 694 cyrix6x86_cpu_setup, NULL}, /* CPU_6x86 */ 695 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 696 NULL, NULL}, /* CPU_NX586 */ 697 }; 698 699 const char *classnames[] = { 700 "386", 701 "486", 702 "586", 703 "686" 704 }; 705 706 const char *modifiers[] = { 707 "", 708 "OverDrive", 709 "Dual", 710 "" 711 }; 712 713 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 714 { 715 "GenuineIntel", 716 CPUVENDOR_INTEL, 717 "Intel", 718 /* Family 4 */ 719 { { 720 CPUCLASS_486, 721 { 722 "486DX", "486DX", "486SX", "486DX2", "486SL", 723 "486SX2", 0, "486DX2 W/B Enhanced", 724 "486DX4", 0, 0, 0, 0, 0, 0, 0, 725 "486" /* Default */ 726 }, 727 NULL, 728 NULL, 729 NULL, 730 }, 731 /* Family 5 */ 732 { 733 CPUCLASS_586, 734 { 735 "Pentium (P5 A-step)", "Pentium (P5)", 736 "Pentium (P54C)", "Pentium (P24T)", 737 "Pentium/MMX", "Pentium", 0, 738 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 739 0, 0, 0, 0, 0, 0, 0, 740 "Pentium" /* Default */ 741 }, 742 NULL, 743 NULL, 744 NULL, 745 }, 746 /* Family 6 */ 747 { 748 CPUCLASS_686, 749 { 750 "Pentium Pro (A-step)", "Pentium Pro", 0, 751 "Pentium II (Klamath)", "Pentium Pro", 752 "Pentium II/Celeron (Deschutes)", 753 "Celeron (Mendocino)", 754 "Pentium III (Katmai)", 755 "Pentium III (Coppermine)", 756 0, "Pentium III Xeon (Cascades)", 757 "Pentium III (Tualatin)", 0, 0, 0, 0, 758 "Pentium Pro, II or III" /* Default */ 759 }, 760 NULL, 761 NULL, 762 NULL, 763 }, 764 /* Family > 6 */ 765 { 766 CPUCLASS_686, 767 { 768 0, 0, 0, 0, 0, 0, 0, 0, 769 0, 0, 0, 0, 0, 0, 0, 0, 770 "Pentium 4" /* Default */ 771 }, 772 NULL, 773 NULL, 774 NULL, 775 } } 776 }, 777 { 778 "AuthenticAMD", 779 CPUVENDOR_AMD, 780 "AMD", 781 /* Family 4 */ 782 { { 783 CPUCLASS_486, 784 { 785 0, 0, 0, "Am486DX2 W/T", 786 0, 0, 0, "Am486DX2 W/B", 787 "Am486DX4 W/T or Am5x86 W/T 150", 788 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 789 0, 0, "Am5x86 W/T 133/160", 790 "Am5x86 W/B 133/160", 791 "Am486 or Am5x86" /* Default */ 792 }, 793 NULL, 794 NULL, 795 NULL, 796 }, 797 /* Family 5 */ 798 { 799 CPUCLASS_586, 800 { 801 "K5", "K5", "K5", "K5", 0, 0, "K6", 802 "K6", "K6-2", "K6-III", 0, 0, 0, 803 "K6-2+/III+", 0, 0, 804 "K5 or K6" /* Default */ 805 }, 806 amd_family5_setup, 807 NULL, 808 amd_cpu_cacheinfo, 809 }, 810 /* Family 6 */ 811 { 812 CPUCLASS_686, 813 { 814 0, "Athlon Model 1", "Athlon Model 2", 815 "Duron", "Athlon Model 4 (Thunderbird)", 816 0, "Athlon", "Duron", "Athlon", 0, 0, 0, 817 0, 0, 0, 0, 818 "K7 (Athlon)" /* Default */ 819 }, 820 NULL, 821 amd_family6_probe, 822 amd_cpu_cacheinfo, 823 }, 824 /* Family > 6 */ 825 { 826 CPUCLASS_686, 827 { 828 0, 0, 0, 0, 0, 0, 0, 0, 829 0, 0, 0, 0, 0, 0, 0, 0, 830 "Unknown K7 (Athlon)" /* Default */ 831 }, 832 NULL, 833 NULL, 834 NULL, 835 } } 836 }, 837 { 838 "CyrixInstead", 839 CPUVENDOR_CYRIX, 840 "Cyrix", 841 /* Family 4 */ 842 { { 843 CPUCLASS_486, 844 { 845 0, 0, 0, 846 "MediaGX", 847 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 848 "486" /* Default */ 849 }, 850 cyrix6x86_cpu_setup, /* XXX ?? */ 851 NULL, 852 NULL, 853 }, 854 /* Family 5 */ 855 { 856 CPUCLASS_586, 857 { 858 0, 0, "6x86", 0, 859 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 861 "6x86" /* Default */ 862 }, 863 cyrix6x86_cpu_setup, 864 NULL, 865 NULL, 866 }, 867 /* Family 6 */ 868 { 869 CPUCLASS_686, 870 { 871 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 872 0, 0, 0, 0, 0, 0, 0, 0, 873 "6x86MX" /* Default */ 874 }, 875 cyrix6x86_cpu_setup, 876 NULL, 877 NULL, 878 }, 879 /* Family > 6 */ 880 { 881 CPUCLASS_686, 882 { 883 0, 0, 0, 0, 0, 0, 0, 0, 884 0, 0, 0, 0, 0, 0, 0, 0, 885 "Unknown 6x86MX" /* Default */ 886 }, 887 NULL, 888 NULL, 889 NULL, 890 } } 891 }, 892 { /* MediaGX is now owned by National Semiconductor */ 893 "Geode by NSC", 894 CPUVENDOR_CYRIX, /* XXX */ 895 "National Semiconductor", 896 /* Family 4, NSC never had any of these */ 897 { { 898 CPUCLASS_486, 899 { 900 0, 0, 0, 0, 0, 0, 0, 0, 901 0, 0, 0, 0, 0, 0, 0, 0, 902 "486 compatible" /* Default */ 903 }, 904 NULL, 905 NULL, 906 NULL, 907 }, 908 /* Family 5: Geode family, formerly MediaGX */ 909 { 910 CPUCLASS_586, 911 { 912 0, 0, 0, 0, 913 "Geode GX1", 914 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 915 "Geode" /* Default */ 916 }, 917 cyrix6x86_cpu_setup, 918 NULL, 919 NULL, 920 }, 921 /* Family 6, not yet available from NSC */ 922 { 923 CPUCLASS_686, 924 { 925 0, 0, 0, 0, 0, 0, 0, 0, 926 0, 0, 0, 0, 0, 0, 0, 0, 927 "Pentium Pro compatible" /* Default */ 928 }, 929 NULL, 930 NULL, 931 NULL, 932 }, 933 /* Family > 6, not yet available from NSC */ 934 { 935 CPUCLASS_686, 936 { 937 0, 0, 0, 0, 0, 0, 0, 0, 938 0, 0, 0, 0, 0, 0, 0, 0, 939 "Pentium Pro compatible" /* Default */ 940 }, 941 NULL, 942 NULL, 943 NULL, 944 } } 945 }, 946 { 947 "CentaurHauls", 948 CPUVENDOR_IDT, 949 "IDT", 950 /* Family 4, IDT never had any of these */ 951 { { 952 CPUCLASS_486, 953 { 954 0, 0, 0, 0, 0, 0, 0, 0, 955 0, 0, 0, 0, 0, 0, 0, 0, 956 "486 compatible" /* Default */ 957 }, 958 NULL, 959 NULL, 960 NULL, 961 }, 962 /* Family 5 */ 963 { 964 CPUCLASS_586, 965 { 966 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 967 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 968 "WinChip" /* Default */ 969 }, 970 winchip_cpu_setup, 971 NULL, 972 NULL, 973 }, 974 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 975 { 976 CPUCLASS_686, 977 { 978 0, 0, 0, 0, 0, 0, "C3 Samuel", 979 "C3 Samuel 2/Ezra", "C3 Ezra-T", 980 0, 0, 0, 0, 0, 0, 0, 981 "C3" /* Default */ 982 }, 983 NULL, 984 via_cpu_probe, 985 NULL, 986 }, 987 /* Family > 6, not yet available from VIA */ 988 { 989 CPUCLASS_686, 990 { 991 0, 0, 0, 0, 0, 0, 0, 0, 992 0, 0, 0, 0, 0, 0, 0, 0, 993 "Pentium Pro compatible" /* Default */ 994 }, 995 NULL, 996 NULL, 997 NULL, 998 } } 999 }, 1000 { 1001 "GenuineTMx86", 1002 CPUVENDOR_TRANSMETA, 1003 "Transmeta", 1004 /* Family 4, Transmeta never had any of these */ 1005 { { 1006 CPUCLASS_486, 1007 { 1008 0, 0, 0, 0, 0, 0, 0, 0, 1009 0, 0, 0, 0, 0, 0, 0, 0, 1010 "486 compatible" /* Default */ 1011 }, 1012 NULL, 1013 NULL, 1014 NULL, 1015 }, 1016 /* Family 5 */ 1017 { 1018 CPUCLASS_586, 1019 { 1020 0, 0, 0, 0, 0, 0, 0, 0, 1021 0, 0, 0, 0, 0, 0, 0, 0, 1022 "Crusoe" /* Default */ 1023 }, 1024 transmeta_cpu_setup, 1025 NULL, 1026 transmeta_cpu_info, 1027 }, 1028 /* Family 6, not yet available from Transmeta */ 1029 { 1030 CPUCLASS_686, 1031 { 1032 0, 0, 0, 0, 0, 0, 0, 0, 1033 0, 0, 0, 0, 0, 0, 0, 0, 1034 "Pentium Pro compatible" /* Default */ 1035 }, 1036 NULL, 1037 NULL, 1038 NULL, 1039 }, 1040 /* Family > 6, not yet available from Transmeta */ 1041 { 1042 CPUCLASS_686, 1043 { 1044 0, 0, 0, 0, 0, 0, 0, 0, 1045 0, 0, 0, 0, 0, 0, 0, 0, 1046 "Pentium Pro compatible" /* Default */ 1047 }, 1048 NULL, 1049 NULL, 1050 NULL, 1051 } } 1052 } 1053 }; 1054 1055 void 1056 cyrix6x86_cpu_setup(ci) 1057 struct cpu_info *ci; 1058 { 1059 /* 1060 * i8254 latch check routine: 1061 * National Geode (formerly Cyrix MediaGX) has a serious bug in 1062 * its built-in i8254-compatible clock module. 1063 * Set the variable 'clock_broken_latch' to indicate it. 1064 */ 1065 1066 extern int clock_broken_latch; 1067 1068 switch (ci->ci_signature) { 1069 case 0x440: /* Cyrix MediaGX */ 1070 case 0x540: /* GXm */ 1071 clock_broken_latch = 1; 1072 break; 1073 } 1074 1075 /* set up various cyrix registers */ 1076 /* Enable suspend on halt */ 1077 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 1078 /* enable access to ccr4/ccr5 */ 1079 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) | 0x10); 1080 /* cyrix's workaround for the "coma bug" */ 1081 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 1082 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 1083 cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xff); 1084 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 1085 /* disable access to ccr4/ccr5 */ 1086 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10); 1087 1088 /* 1089 * XXX disable page zero in the idle loop, it seems to 1090 * cause panics on these CPUs. 1091 */ 1092 vm_page_zero_enable = FALSE; 1093 } 1094 1095 void 1096 winchip_cpu_setup(ci) 1097 struct cpu_info *ci; 1098 { 1099 #if defined(I586_CPU) 1100 switch (CPUID2MODEL(ci->ci_signature)) { /* model */ 1101 case 4: /* WinChip C6 */ 1102 cpu_feature &= ~CPUID_TSC; 1103 printf("WARNING: WinChip C6: broken TSC disabled\n"); 1104 } 1105 #endif 1106 } 1107 1108 #define CPUID(code, eax, ebx, ecx, edx) \ 1109 __asm("cpuid" \ 1110 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 1111 : "a" (code)); 1112 1113 void 1114 via_cpu_probe(struct cpu_info *ci) 1115 { 1116 u_int descs[4]; 1117 u_int lfunc; 1118 1119 /* 1120 * Determine the largest extended function value. 1121 */ 1122 CPUID(0x80000000, descs[0], descs[1], descs[2], descs[3]); 1123 lfunc = descs[0]; 1124 1125 /* 1126 * Determine the extended feature flags. 1127 */ 1128 if (lfunc >= 0x80000001) { 1129 CPUID(0x80000001, descs[0], descs[1], descs[2], descs[3]); 1130 ci->ci_feature_flags = descs[3]; 1131 } 1132 } 1133 1134 const char * 1135 intel_family6_name(struct cpu_info *ci) 1136 { 1137 int model = CPUID2MODEL(ci->ci_signature); 1138 const char *ret = NULL; 1139 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 1140 1141 if (model == 5) { 1142 switch (l2cache) { 1143 case 0: 1144 case 128 * 1024: 1145 ret = "Celeron (Covington)"; 1146 break; 1147 case 256 * 1024: 1148 ret = "Mobile Pentium II (Dixon)"; 1149 break; 1150 case 512 * 1024: 1151 ret = "Pentium II"; 1152 break; 1153 case 1 * 1024 * 1024: 1154 case 2 * 1024 * 1024: 1155 ret = "Pentium II Xeon"; 1156 break; 1157 } 1158 } else if (model == 6) { 1159 switch (l2cache) { 1160 case 256 * 1024: 1161 case 512 * 1024: 1162 ret = "Mobile Pentium II"; 1163 break; 1164 } 1165 } else if (model == 7) { 1166 switch (l2cache) { 1167 case 512 * 1024: 1168 ret = "Pentium III"; 1169 break; 1170 case 1 * 1024 * 1024: 1171 case 2 * 1024 * 1024: 1172 ret = "Pentium III Xeon"; 1173 break; 1174 } 1175 } else if (model >= 8) { 1176 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 1177 switch (ci->ci_brand_id) { 1178 case 0x3: 1179 if (ci->ci_signature == 0x6B1) 1180 ret = "Celeron"; 1181 break; 1182 case 0x08: 1183 if (ci->ci_signature >= 0xF13) 1184 ret = "genuine processor"; 1185 break; 1186 case 0x0E: 1187 if (ci->ci_signature < 0xF13) 1188 ret = "Xeon"; 1189 break; 1190 } 1191 if (ret == NULL) 1192 ret = i386_intel_brand[ci->ci_brand_id]; 1193 } 1194 } 1195 1196 return ret; 1197 } 1198 1199 static void 1200 cpu_probe_base_features(struct cpu_info *ci) 1201 { 1202 const struct i386_cache_info *cai; 1203 u_int descs[4]; 1204 int iterations, i, j; 1205 u_int8_t desc; 1206 u_int32_t dummy1, dummy2, miscbytes; 1207 1208 if (ci->ci_cpuid_level < 0) 1209 return; 1210 1211 CPUID(0, ci->ci_cpuid_level, 1212 ci->ci_vendor[0], 1213 ci->ci_vendor[2], 1214 ci->ci_vendor[1]); 1215 ci->ci_vendor[3] = 0; 1216 1217 if (ci->ci_cpuid_level < 1) 1218 return; 1219 1220 CPUID(1, ci->ci_signature, miscbytes, dummy1, ci->ci_feature_flags); 1221 1222 /* Brand is low order 8 bits of ebx */ 1223 ci->ci_brand_id = miscbytes & 0xff; 1224 1225 /* CLFLUSH line size is next 8 bits */ 1226 if (ci->ci_feature_flags & CPUID_CFLUSH) 1227 ci->ci_cflush_lsize = ((miscbytes >> 8) & 0xff) << 3; 1228 1229 if (ci->ci_cpuid_level < 2) 1230 return; 1231 1232 /* 1233 * Parse the cache info from `cpuid', if we have it. 1234 * XXX This is kinda ugly, but hey, so is the architecture... 1235 */ 1236 1237 CPUID(2, descs[0], descs[1], descs[2], descs[3]); 1238 1239 iterations = descs[0] & 0xff; 1240 while (iterations-- > 0) { 1241 for (i = 0; i < 4; i++) { 1242 if (descs[i] & 0x80000000) 1243 continue; 1244 for (j = 0; j < 4; j++) { 1245 if (i == 0 && j == 0) 1246 continue; 1247 desc = (descs[i] >> (j * 8)) & 0xff; 1248 if (desc == 0) 1249 continue; 1250 cai = cache_info_lookup(intel_cpuid_cache_info, 1251 desc); 1252 if (cai != NULL) 1253 ci->ci_cinfo[cai->cai_index] = *cai; 1254 } 1255 } 1256 CPUID(2, descs[0], descs[1], descs[2], descs[3]); 1257 } 1258 1259 if (ci->ci_cpuid_level < 3) 1260 return; 1261 1262 /* 1263 * If the processor serial number misfeature is present and supported, 1264 * extract it here. 1265 */ 1266 if ((ci->ci_feature_flags & CPUID_PN) != 0) 1267 { 1268 ci->ci_cpu_serial[0] = ci->ci_signature; 1269 CPUID(3, dummy1, dummy2, 1270 ci->ci_cpu_serial[2], 1271 ci->ci_cpu_serial[1]); 1272 } 1273 } 1274 1275 void 1276 cpu_probe_features(struct cpu_info *ci) 1277 { 1278 const struct cpu_cpuid_nameclass *cpup = NULL; 1279 int i, max, family; 1280 1281 cpu_probe_base_features(ci); 1282 1283 if (ci->ci_cpuid_level < 1) 1284 return; 1285 1286 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]); 1287 for (i = 0; i < max; i++) { 1288 if (!strncmp((char *)ci->ci_vendor, 1289 i386_cpuid_cpus[i].cpu_id, 12)) { 1290 cpup = &i386_cpuid_cpus[i]; 1291 break; 1292 } 1293 } 1294 1295 if (cpup == NULL) 1296 return; 1297 1298 family = (ci->ci_signature >> 8) & 0xf; 1299 1300 if (family > CPU_MAXFAMILY) { 1301 family = CPU_MAXFAMILY; 1302 } 1303 i = family - CPU_MINFAMILY; 1304 1305 if (cpup->cpu_family[i].cpu_probe == NULL) 1306 return; 1307 1308 (*cpup->cpu_family[i].cpu_probe)(ci); 1309 } 1310 1311 void 1312 amd_family6_probe(struct cpu_info *ci) 1313 { 1314 u_int32_t lfunc; 1315 u_int32_t descs[4]; 1316 u_int32_t brand[12]; 1317 char *p; 1318 int i; 1319 1320 CPUID(0x80000000, lfunc, descs[1], descs[2], descs[3]); 1321 1322 /* 1323 * Determine the extended feature flags. 1324 */ 1325 if (lfunc >= 0x80000001) { 1326 CPUID(0x80000001, descs[0], descs[1], descs[2], descs[3]); 1327 ci->ci_feature_flags |= descs[3]; 1328 } 1329 1330 if (lfunc < 0x80000004) 1331 return; 1332 1333 CPUID(0x80000002, brand[0], brand[1], brand[2], brand[3]); 1334 CPUID(0x80000003, brand[4], brand[5], brand[6], brand[7]); 1335 CPUID(0x80000004, brand[8], brand[9], brand[10], brand[11]); 1336 1337 for (i = 1; i < sizeof(amd_brand) / sizeof(amd_brand[0]); i++) 1338 if ((p = strstr((char *)brand, amd_brand[i])) != NULL) { 1339 ci->ci_brand_id = i; 1340 strcpy(amd_brand_name, p); 1341 break; 1342 } 1343 } 1344 1345 void 1346 amd_family5_setup(struct cpu_info *ci) 1347 { 1348 1349 switch (CPUID2MODEL(ci->ci_signature)) { 1350 case 0: /* AMD-K5 Model 0 */ 1351 /* 1352 * According to the AMD Processor Recognition App Note, 1353 * the AMD-K5 Model 0 uses the wrong bit to indicate 1354 * support for global PTEs, instead using bit 9 (APIC) 1355 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1356 */ 1357 if (cpu_feature & CPUID_APIC) 1358 cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE; 1359 /* 1360 * XXX But pmap_pg_g is already initialized -- need to kick 1361 * XXX the pmap somehow. How does the MP branch do this? 1362 */ 1363 break; 1364 } 1365 } 1366 1367 /* 1368 * Transmeta Crusoe LongRun Support by Tamotsu Hattori. 1369 * Port from FreeBSD-current(August, 2001) to NetBSD by tshiozak. 1370 */ 1371 1372 #define MSR_TMx86_LONGRUN 0x80868010 1373 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011 1374 1375 #define LONGRUN_MODE_MASK(x) ((x) & 0x0000007f) 1376 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80) 1377 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | \ 1378 LONGRUN_MODE_MASK(y)) 1379 1380 #define LONGRUN_MODE_MINFREQUENCY 0x00 1381 #define LONGRUN_MODE_ECONOMY 0x01 1382 #define LONGRUN_MODE_PERFORMANCE 0x02 1383 #define LONGRUN_MODE_MAXFREQUENCY 0x03 1384 #define LONGRUN_MODE_UNKNOWN 0x04 1385 #define LONGRUN_MODE_MAX 0x04 1386 1387 union msrinfo { 1388 u_int64_t msr; 1389 u_int32_t regs[2]; 1390 }; 1391 1392 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = { 1393 /* MSR low, MSR high, flags bit0 */ 1394 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */ 1395 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */ 1396 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */ 1397 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */ 1398 }; 1399 1400 static u_int 1401 tmx86_get_longrun_mode(void) 1402 { 1403 u_long eflags; 1404 union msrinfo msrinfo; 1405 u_int low, high, flags, mode; 1406 1407 eflags = read_eflags(); 1408 disable_intr(); 1409 1410 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); 1411 low = LONGRUN_MODE_MASK(msrinfo.regs[0]); 1412 high = LONGRUN_MODE_MASK(msrinfo.regs[1]); 1413 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01; 1414 1415 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) { 1416 if (low == longrun_modes[mode][0] && 1417 high == longrun_modes[mode][1] && 1418 flags == longrun_modes[mode][2]) { 1419 goto out; 1420 } 1421 } 1422 mode = LONGRUN_MODE_UNKNOWN; 1423 out: 1424 write_eflags(eflags); 1425 return (mode); 1426 } 1427 1428 static u_int 1429 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1430 { 1431 u_long eflags; 1432 u_int eax, ebx, ecx, edx; 1433 1434 eflags = read_eflags(); 1435 disable_intr(); 1436 1437 CPUID(0x80860007, eax, ebx, ecx, edx); 1438 *frequency = eax; 1439 *voltage = ebx; 1440 *percentage = ecx; 1441 1442 write_eflags(eflags); 1443 return (1); 1444 } 1445 1446 static u_int 1447 tmx86_set_longrun_mode(u_int mode) 1448 { 1449 u_long eflags; 1450 union msrinfo msrinfo; 1451 1452 if (mode >= LONGRUN_MODE_UNKNOWN) { 1453 return (0); 1454 } 1455 1456 eflags = read_eflags(); 1457 disable_intr(); 1458 1459 /* Write LongRun mode values to Model Specific Register. */ 1460 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); 1461 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0], 1462 longrun_modes[mode][0]); 1463 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1], 1464 longrun_modes[mode][1]); 1465 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr); 1466 1467 /* Write LongRun mode flags to Model Specific Register. */ 1468 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS); 1469 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2]; 1470 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr); 1471 1472 write_eflags(eflags); 1473 return (1); 1474 } 1475 1476 static u_int crusoe_longrun; 1477 static u_int crusoe_frequency; 1478 static u_int crusoe_voltage; 1479 static u_int crusoe_percentage; 1480 1481 static void 1482 tmx86_get_longrun_status_all(void) 1483 { 1484 1485 tmx86_get_longrun_status(&crusoe_frequency, 1486 &crusoe_voltage, &crusoe_percentage); 1487 } 1488 1489 1490 static void 1491 transmeta_cpu_info(struct cpu_info *ci) 1492 { 1493 u_int eax, ebx, ecx, edx, nreg = 0; 1494 1495 CPUID(0x80860000, eax, ebx, ecx, edx); 1496 nreg = eax; 1497 if (nreg >= 0x80860001) { 1498 CPUID(0x80860001, eax, ebx, ecx, edx); 1499 printf("%s: Processor revision %u.%u.%u.%u\n", 1500 ci->ci_dev->dv_xname, 1501 (ebx >> 24) & 0xff, 1502 (ebx >> 16) & 0xff, 1503 (ebx >> 8) & 0xff, 1504 ebx & 0xff); 1505 } 1506 if (nreg >= 0x80860002) { 1507 CPUID(0x80860002, eax, ebx, ecx, edx); 1508 printf("%s: Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1509 ci->ci_dev->dv_xname, (ebx >> 24) & 0xff, 1510 (ebx >> 16) & 0xff, 1511 (ebx >> 8) & 0xff, 1512 ebx & 0xff, 1513 ecx); 1514 } 1515 if (nreg >= 0x80860006) { 1516 union { 1517 char text[65]; 1518 struct 1519 { 1520 u_int eax; 1521 u_int ebx; 1522 u_int ecx; 1523 u_int edx; 1524 } regs[4]; 1525 } info; 1526 int i; 1527 1528 for (i=0; i<4; i++) { 1529 CPUID(0x80860003 + i, 1530 info.regs[i].eax, info.regs[i].ebx, 1531 info.regs[i].ecx, info.regs[i].edx); 1532 } 1533 info.text[64] = 0; 1534 printf("%s: %s\n", ci->ci_dev->dv_xname, info.text); 1535 } 1536 1537 if (nreg >= 0x80860007) { 1538 crusoe_longrun = tmx86_get_longrun_mode(); 1539 tmx86_get_longrun_status(&crusoe_frequency, 1540 &crusoe_voltage, &crusoe_percentage); 1541 printf("%s: LongRun mode: %d <%dMHz %dmV %d%%>\n", 1542 ci->ci_dev->dv_xname, 1543 crusoe_longrun, crusoe_frequency, crusoe_voltage, 1544 crusoe_percentage); 1545 } 1546 } 1547 1548 void 1549 transmeta_cpu_setup(struct cpu_info *ci) 1550 { 1551 u_int nreg = 0, dummy; 1552 1553 CPUID(0x80860000, nreg, dummy, dummy, dummy); 1554 if (nreg >= 0x80860007) 1555 tmx86_has_longrun = 1; 1556 } 1557 1558 1559 /* ---------------------------------------------------------------------- */ 1560 1561 static const struct i386_cache_info * 1562 cache_info_lookup(const struct i386_cache_info *cai, u_int8_t desc) 1563 { 1564 int i; 1565 1566 for (i = 0; cai[i].cai_desc != 0; i++) { 1567 if (cai[i].cai_desc == desc) 1568 return (&cai[i]); 1569 } 1570 1571 return (NULL); 1572 } 1573 1574 /* 1575 * AMD Cache Info: 1576 * 1577 * Athlon, Duron: 1578 * 1579 * Function 8000.0005 L1 TLB/Cache Information 1580 * EAX -- L1 TLB 2/4MB pages 1581 * EBX -- L1 TLB 4K pages 1582 * ECX -- L1 D-cache 1583 * EDX -- L1 I-cache 1584 * 1585 * Function 8000.0006 L2 TLB/Cache Information 1586 * EAX -- L2 TLB 2/4MB pages 1587 * EBX -- L2 TLB 4K pages 1588 * ECX -- L2 Unified cache 1589 * EDX -- reserved 1590 * 1591 * K5, K6: 1592 * 1593 * Function 8000.0005 L1 TLB/Cache Information 1594 * EAX -- reserved 1595 * EBX -- TLB 4K pages 1596 * ECX -- L1 D-cache 1597 * EDX -- L1 I-cache 1598 * 1599 * K6-III: 1600 * 1601 * Function 8000.0006 L2 Cache Information 1602 * EAX -- reserved 1603 * EBX -- reserved 1604 * ECX -- L2 Unified cache 1605 * EDX -- reserved 1606 */ 1607 1608 /* L1 TLB 2/4MB pages */ 1609 #define AMD_L1_EAX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) 1610 #define AMD_L1_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) 1611 #define AMD_L1_EAX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) 1612 #define AMD_L1_EAX_ITLB_ENTRIES(x) ( (x) & 0xff) 1613 1614 /* L1 TLB 4K pages */ 1615 #define AMD_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) 1616 #define AMD_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) 1617 #define AMD_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) 1618 #define AMD_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff) 1619 1620 /* L1 Data Cache */ 1621 #define AMD_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 1622 #define AMD_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff) 1623 #define AMD_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff) 1624 #define AMD_L1_ECX_DC_LS(x) ( (x) & 0xff) 1625 1626 /* L1 Instruction Cache */ 1627 #define AMD_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 1628 #define AMD_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff) 1629 #define AMD_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff) 1630 #define AMD_L1_EDX_IC_LS(x) ( (x) & 0xff) 1631 1632 /* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */ 1633 1634 /* L2 TLB 2/4MB pages */ 1635 #define AMD_L2_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) 1636 #define AMD_L2_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) 1637 #define AMD_L2_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) 1638 #define AMD_L2_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff) 1639 1640 /* L2 TLB 4K pages */ 1641 #define AMD_L2_EBX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) 1642 #define AMD_L2_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) 1643 #define AMD_L2_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) 1644 #define AMD_L2_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff) 1645 1646 /* L2 Cache */ 1647 #define AMD_L2_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024) 1648 #define AMD_L2_ECX_C_ASSOC(x) (((x) >> 12) & 0xf) 1649 #define AMD_L2_ECX_C_LPT(x) (((x) >> 8) & 0xf) 1650 #define AMD_L2_ECX_C_LS(x) ( (x) & 0xff) 1651 1652 static const struct i386_cache_info amd_cpuid_l2cache_assoc_info[] = { 1653 { 0, 0x01, 1 }, 1654 { 0, 0x02, 2 }, 1655 { 0, 0x04, 4 }, 1656 { 0, 0x06, 8 }, 1657 { 0, 0x08, 16 }, 1658 { 0, 0x0f, 0xff }, 1659 { 0, 0x00, 0 }, 1660 }; 1661 1662 void 1663 amd_cpu_cacheinfo(struct cpu_info *ci) 1664 { 1665 const struct i386_cache_info *cp; 1666 struct i386_cache_info *cai; 1667 int family, model; 1668 u_int descs[4]; 1669 u_int lfunc; 1670 1671 family = (ci->ci_signature >> 8) & 15; 1672 if (family < CPU_MINFAMILY) 1673 panic("amd_cpu_cacheinfo: strange family value"); 1674 model = CPUID2MODEL(ci->ci_signature); 1675 1676 /* 1677 * K5 model 0 has none of this info. 1678 */ 1679 if (family == 5 && model == 0) 1680 return; 1681 1682 /* 1683 * Determine the largest extended function value. 1684 */ 1685 CPUID(0x80000000, descs[0], descs[1], descs[2], descs[3]); 1686 lfunc = descs[0]; 1687 1688 /* 1689 * Determine L1 cache/TLB info. 1690 */ 1691 if (lfunc < 0x80000005) { 1692 /* No L1 cache info available. */ 1693 return; 1694 } 1695 1696 CPUID(0x80000005, descs[0], descs[1], descs[2], descs[3]); 1697 1698 /* 1699 * K6-III and higher have large page TLBs. 1700 */ 1701 if ((family == 5 && model >= 9) || family >= 6) { 1702 cai = &ci->ci_cinfo[CAI_ITLB2]; 1703 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1704 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1705 cai->cai_linesize = (4 * 1024 * 1024); 1706 1707 cai = &ci->ci_cinfo[CAI_DTLB2]; 1708 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1709 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1710 cai->cai_linesize = (4 * 1024 * 1024); 1711 } 1712 1713 cai = &ci->ci_cinfo[CAI_ITLB]; 1714 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1715 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1716 cai->cai_linesize = (4 * 1024); 1717 1718 cai = &ci->ci_cinfo[CAI_DTLB]; 1719 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1720 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1721 cai->cai_linesize = (4 * 1024); 1722 1723 cai = &ci->ci_cinfo[CAI_DCACHE]; 1724 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1725 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1726 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[2]); 1727 1728 cai = &ci->ci_cinfo[CAI_ICACHE]; 1729 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1730 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1731 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1732 1733 /* 1734 * Determine L2 cache/TLB info. 1735 */ 1736 if (lfunc < 0x80000006) { 1737 /* No L2 cache info available. */ 1738 return; 1739 } 1740 1741 CPUID(0x80000006, descs[0], descs[1], descs[2], descs[3]); 1742 1743 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1744 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1745 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1746 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1747 1748 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1749 cai->cai_associativity); 1750 if (cp != NULL) 1751 cai->cai_associativity = cp->cai_associativity; 1752 else 1753 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1754 } 1755 1756 static const char n_support[] __attribute__((__unused__)) = 1757 "NOTICE: this kernel does not support %s CPU class\n"; 1758 static const char n_lower[] __attribute__((__unused__)) = 1759 "NOTICE: lowering CPU class to %s\n"; 1760 1761 void 1762 identifycpu(struct cpu_info *ci) 1763 { 1764 const char *name, *modifier, *vendorname, *brand = ""; 1765 int class = CPUCLASS_386, vendor, i, max; 1766 int modif, family, model, step; 1767 const struct cpu_cpuid_nameclass *cpup = NULL; 1768 const struct cpu_cpuid_family *cpufam; 1769 char *cpuname = ci->ci_dev->dv_xname; 1770 char buf[1024]; 1771 char *sep; 1772 char *feature_str[3]; 1773 1774 if (ci->ci_cpuid_level == -1) { 1775 #ifdef DIAGNOSTIC 1776 if (cpu < 0 || cpu >= 1777 sizeof(i386_nocpuid_cpus) / sizeof(i386_nocpuid_cpus[0])) 1778 panic("unknown cpu type %d", cpu); 1779 #endif 1780 name = i386_nocpuid_cpus[cpu].cpu_name; 1781 vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1782 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1783 class = i386_nocpuid_cpus[cpu].cpu_class; 1784 ci->cpu_setup = i386_nocpuid_cpus[cpu].cpu_setup; 1785 ci->ci_info = i386_nocpuid_cpus[cpu].cpu_info; 1786 modifier = ""; 1787 } else { 1788 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]); 1789 modif = (ci->ci_signature >> 12) & 0x3; 1790 family = CPUID2FAMILY(ci->ci_signature); 1791 if (family < CPU_MINFAMILY) 1792 panic("identifycpu: strange family value"); 1793 model = CPUID2MODEL(ci->ci_signature); 1794 step = CPUID2STEPPING(ci->ci_signature); 1795 1796 for (i = 0; i < max; i++) { 1797 if (!strncmp((char *)ci->ci_vendor, 1798 i386_cpuid_cpus[i].cpu_id, 12)) { 1799 cpup = &i386_cpuid_cpus[i]; 1800 break; 1801 } 1802 } 1803 1804 if (cpup == NULL) { 1805 vendor = CPUVENDOR_UNKNOWN; 1806 if (ci->ci_vendor[0] != '\0') 1807 vendorname = (char *)&ci->ci_vendor[0]; 1808 else 1809 vendorname = "Unknown"; 1810 if (family > CPU_MAXFAMILY) 1811 family = CPU_MAXFAMILY; 1812 class = family - 3; 1813 modifier = ""; 1814 name = ""; 1815 ci->cpu_setup = NULL; 1816 ci->ci_info = NULL; 1817 } else { 1818 vendor = cpup->cpu_vendor; 1819 vendorname = cpup->cpu_vendorname; 1820 modifier = modifiers[modif]; 1821 if (family > CPU_MAXFAMILY) { 1822 family = CPU_MAXFAMILY; 1823 model = CPU_DEFMODEL; 1824 } else if (model > CPU_MAXMODEL) 1825 model = CPU_DEFMODEL; 1826 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1827 name = cpufam->cpu_models[model]; 1828 if (name == NULL) 1829 name = cpufam->cpu_models[CPU_DEFMODEL]; 1830 class = cpufam->cpu_class; 1831 ci->cpu_setup = cpufam->cpu_setup; 1832 ci->ci_info = cpufam->cpu_info; 1833 1834 if (vendor == CPUVENDOR_INTEL && family == 6 && 1835 model >= 5) { 1836 const char *tmp = intel_family6_name(ci); 1837 if (tmp != NULL) 1838 name = tmp; 1839 } 1840 1841 if (vendor == CPUVENDOR_AMD && family == 6 && 1842 model >= 6) { 1843 if (ci->ci_brand_id == 1) 1844 /* 1845 * It's Duron. We override the 1846 * name, since it might have been 1847 * misidentified as Athlon. 1848 */ 1849 name = amd_brand[ci->ci_brand_id]; 1850 else 1851 brand = amd_brand_name; 1852 } 1853 1854 if (vendor == CPUVENDOR_IDT && family >= 6) 1855 vendorname = "VIA"; 1856 } 1857 } 1858 1859 cpu_class = class; 1860 ci->ci_cpu_class = class; 1861 1862 #if defined(I586_CPU) || defined(I686_CPU) 1863 /* 1864 * If we have a cycle counter, compute the approximate 1865 * CPU speed in MHz. 1866 * XXX this needs to run on the CPU being probed.. 1867 */ 1868 if (ci->ci_feature_flags & CPUID_TSC) { 1869 u_int64_t last_tsc; 1870 1871 last_tsc = rdtsc(); 1872 delay(100000); 1873 ci->ci_tsc_freq = (rdtsc() - last_tsc) * 10; 1874 microtime_func = tsc_microtime; 1875 } 1876 /* XXX end XXX */ 1877 #endif 1878 1879 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1880 vendorname, 1881 *modifier ? " " : "", modifier, 1882 *name ? " " : "", name, 1883 *brand ? " " : "", brand, 1884 classnames[class]); 1885 printf("%s: %s", cpuname, cpu_model); 1886 1887 if (ci->ci_tsc_freq != 0) 1888 printf(", %qd.%02qd MHz", (ci->ci_tsc_freq + 4999) / 1000000, 1889 ((ci->ci_tsc_freq + 4999) / 10000) % 100); 1890 if (ci->ci_signature != 0) 1891 printf(", id 0x%x", ci->ci_signature); 1892 printf("\n"); 1893 1894 if (ci->ci_info) 1895 (*ci->ci_info)(ci); 1896 1897 if (vendor == CPUVENDOR_INTEL) { 1898 feature_str[0] = CPUID_FLAGS1; 1899 feature_str[1] = CPUID_FLAGS2; 1900 feature_str[2] = CPUID_FLAGS3; 1901 } else { 1902 feature_str[0] = CPUID_FLAGS1; 1903 feature_str[1] = CPUID_EXT_FLAGS2; 1904 feature_str[2] = CPUID_EXT_FLAGS3; 1905 } 1906 1907 if (ci->ci_feature_flags) { 1908 if ((ci->ci_feature_flags & CPUID_MASK1) != 0) { 1909 bitmask_snprintf(ci->ci_feature_flags, 1910 feature_str[0], buf, sizeof(buf)); 1911 printf("%s: features %s\n", cpuname, buf); 1912 } 1913 if ((ci->ci_feature_flags & CPUID_MASK2) != 0) { 1914 bitmask_snprintf(ci->ci_feature_flags, 1915 feature_str[1], buf, sizeof(buf)); 1916 printf("%s: features %s\n", cpuname, buf); 1917 } 1918 if ((ci->ci_feature_flags & CPUID_MASK3) != 0) { 1919 bitmask_snprintf(ci->ci_feature_flags, 1920 feature_str[2], buf, sizeof(buf)); 1921 printf("%s: features %s\n", cpuname, buf); 1922 } 1923 } 1924 1925 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1926 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1927 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1928 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1929 if (sep != NULL) 1930 printf("\n"); 1931 } 1932 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1933 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1934 if (sep != NULL) 1935 printf("\n"); 1936 } 1937 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1938 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1939 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1940 if (sep != NULL) 1941 printf("\n"); 1942 } 1943 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1944 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1945 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1946 if (sep != NULL) 1947 printf("\n"); 1948 } 1949 1950 if (ci->ci_cpuid_level >= 3 && (ci->ci_feature_flags & CPUID_PN)) { 1951 printf("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1952 cpuname, 1953 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1954 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1955 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1956 } 1957 1958 /* 1959 * Now that we have told the user what they have, 1960 * let them know if that machine type isn't configured. 1961 */ 1962 switch (cpu_class) { 1963 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1964 #error No CPU classes configured. 1965 #endif 1966 #ifndef I686_CPU 1967 case CPUCLASS_686: 1968 printf(n_support, "Pentium Pro"); 1969 #ifdef I586_CPU 1970 printf(n_lower, "i586"); 1971 cpu_class = CPUCLASS_586; 1972 break; 1973 #endif 1974 #endif 1975 #ifndef I586_CPU 1976 case CPUCLASS_586: 1977 printf(n_support, "Pentium"); 1978 #ifdef I486_CPU 1979 printf(n_lower, "i486"); 1980 cpu_class = CPUCLASS_486; 1981 break; 1982 #endif 1983 #endif 1984 #ifndef I486_CPU 1985 case CPUCLASS_486: 1986 printf(n_support, "i486"); 1987 #ifdef I386_CPU 1988 printf(n_lower, "i386"); 1989 cpu_class = CPUCLASS_386; 1990 break; 1991 #endif 1992 #endif 1993 #ifndef I386_CPU 1994 case CPUCLASS_386: 1995 printf(n_support, "i386"); 1996 panic("no appropriate CPU class available"); 1997 #endif 1998 default: 1999 break; 2000 } 2001 2002 /* 2003 * Now plug in optimized versions of various routines we 2004 * might have. 2005 */ 2006 switch (cpu_class) { 2007 #if defined(I686_CPU) 2008 case CPUCLASS_686: 2009 copyout_func = i486_copyout; 2010 break; 2011 #endif 2012 #if defined(I586_CPU) 2013 case CPUCLASS_586: 2014 copyout_func = i486_copyout; 2015 break; 2016 #endif 2017 #if defined(I486_CPU) 2018 case CPUCLASS_486: 2019 copyout_func = i486_copyout; 2020 break; 2021 #endif 2022 default: 2023 /* We just inherit the default i386 versions. */ 2024 break; 2025 } 2026 2027 if (cpu == CPU_486DLC) { 2028 #ifndef CYRIX_CACHE_WORKS 2029 printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2030 #else 2031 #ifndef CYRIX_CACHE_REALLY_WORKS 2032 printf("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2033 #else 2034 printf("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2035 #endif 2036 #endif 2037 } 2038 2039 #if defined(I686_CPU) 2040 /* 2041 * If we have FXSAVE/FXRESTOR, use them. 2042 */ 2043 if (cpu_feature & CPUID_FXSR) { 2044 i386_use_fxsave = 1; 2045 2046 /* 2047 * If we have SSE/SSE2, enable XMM exceptions, and 2048 * notify userland. 2049 */ 2050 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) { 2051 if (cpu_feature & CPUID_SSE) 2052 i386_has_sse = 1; 2053 if (cpu_feature & CPUID_SSE2) 2054 i386_has_sse2 = 1; 2055 } 2056 } else 2057 i386_use_fxsave = 0; 2058 #endif /* I686_CPU */ 2059 } 2060 2061 /* 2062 * machine dependent system variables. 2063 */ 2064 int 2065 cpu_sysctl(name, namelen, oldp, oldlenp, newp, newlen, p) 2066 int *name; 2067 u_int namelen; 2068 void *oldp; 2069 size_t *oldlenp; 2070 void *newp; 2071 size_t newlen; 2072 struct proc *p; 2073 { 2074 dev_t consdev; 2075 struct btinfo_bootpath *bibp; 2076 int error, mode; 2077 2078 /* all sysctl names at this level are terminal */ 2079 if (namelen != 1) 2080 return (ENOTDIR); /* overloaded */ 2081 2082 switch (name[0]) { 2083 case CPU_CONSDEV: 2084 if (cn_tab != NULL) 2085 consdev = cn_tab->cn_dev; 2086 else 2087 consdev = NODEV; 2088 return (sysctl_rdstruct(oldp, oldlenp, newp, &consdev, 2089 sizeof consdev)); 2090 2091 case CPU_BIOSBASEMEM: 2092 return (sysctl_rdint(oldp, oldlenp, newp, biosbasemem)); 2093 2094 case CPU_BIOSEXTMEM: 2095 return (sysctl_rdint(oldp, oldlenp, newp, biosextmem)); 2096 2097 case CPU_NKPDE: 2098 return (sysctl_rdint(oldp, oldlenp, newp, nkpde)); 2099 2100 case CPU_FPU_PRESENT: 2101 return (sysctl_rdint(oldp, oldlenp, newp, i386_fpu_present)); 2102 2103 case CPU_BOOTED_KERNEL: 2104 bibp = lookup_bootinfo(BTINFO_BOOTPATH); 2105 if(!bibp) 2106 return(ENOENT); /* ??? */ 2107 return (sysctl_rdstring(oldp, oldlenp, newp, bibp->bootpath)); 2108 case CPU_DISKINFO: 2109 if (i386_alldisks == NULL) 2110 return (ENOENT); 2111 return (sysctl_rdstruct(oldp, oldlenp, newp, i386_alldisks, 2112 sizeof (struct disklist) + 2113 (i386_ndisks - 1) * sizeof (struct nativedisk_info))); 2114 case CPU_OSFXSR: 2115 return (sysctl_rdint(oldp, oldlenp, newp, i386_use_fxsave)); 2116 case CPU_SSE: 2117 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_sse)); 2118 case CPU_SSE2: 2119 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_sse2)); 2120 case CPU_TMLR_MODE: 2121 if (!tmx86_has_longrun) 2122 return (EOPNOTSUPP); 2123 mode = (int)(crusoe_longrun = tmx86_get_longrun_mode()); 2124 error = sysctl_int(oldp, oldlenp, newp, newlen, &mode); 2125 if (!error && (u_int)mode != crusoe_longrun) { 2126 if (tmx86_set_longrun_mode(mode)) { 2127 crusoe_longrun = (u_int)mode; 2128 } else { 2129 error = EINVAL; 2130 } 2131 } 2132 return (error); 2133 case CPU_TMLR_FREQUENCY: 2134 if (!tmx86_has_longrun) 2135 return (EOPNOTSUPP); 2136 tmx86_get_longrun_status_all(); 2137 return (sysctl_rdint(oldp, oldlenp, newp, crusoe_frequency)); 2138 case CPU_TMLR_VOLTAGE: 2139 if (!tmx86_has_longrun) 2140 return (EOPNOTSUPP); 2141 tmx86_get_longrun_status_all(); 2142 return (sysctl_rdint(oldp, oldlenp, newp, crusoe_voltage)); 2143 case CPU_TMLR_PERCENTAGE: 2144 if (!tmx86_has_longrun) 2145 return (EOPNOTSUPP); 2146 tmx86_get_longrun_status_all(); 2147 return (sysctl_rdint(oldp, oldlenp, newp, crusoe_percentage)); 2148 default: 2149 return (EOPNOTSUPP); 2150 } 2151 /* NOTREACHED */ 2152 } 2153 2154 /* 2155 * Send an interrupt to process. 2156 * 2157 * Stack is set up to allow sigcode stored 2158 * in u. to call routine, followed by kcall 2159 * to sigreturn routine below. After sigreturn 2160 * resets the signal mask, the stack, and the 2161 * frame pointer, it returns to the user 2162 * specified pc, psl. 2163 */ 2164 void 2165 sendsig(sig, mask, code) 2166 int sig; 2167 sigset_t *mask; 2168 u_long code; 2169 { 2170 struct proc *p = curproc; 2171 struct sigacts *ps = p->p_sigacts; 2172 struct trapframe *tf; 2173 struct sigframe *fp, frame; 2174 int onstack; 2175 sig_t catcher = SIGACTION(p, sig).sa_handler; 2176 2177 tf = p->p_md.md_regs; 2178 2179 /* Do we need to jump onto the signal stack? */ 2180 onstack = 2181 (p->p_sigctx.ps_sigstk.ss_flags & (SS_DISABLE | SS_ONSTACK)) == 0 && 2182 (SIGACTION(p, sig).sa_flags & SA_ONSTACK) != 0; 2183 2184 /* Allocate space for the signal handler context. */ 2185 if (onstack) 2186 fp = (struct sigframe *)((caddr_t)p->p_sigctx.ps_sigstk.ss_sp + 2187 p->p_sigctx.ps_sigstk.ss_size); 2188 else 2189 fp = (struct sigframe *)tf->tf_esp; 2190 fp--; 2191 2192 /* Build stack frame for signal trampoline. */ 2193 switch (ps->sa_sigdesc[sig].sd_vers) { 2194 #if 1 /* COMPAT_16 */ 2195 case 0: /* legacy on-stack sigtramp */ 2196 frame.sf_ra = (int)p->p_sigctx.ps_sigcode; 2197 break; 2198 #endif /* COMPAT_16 */ 2199 2200 case 1: 2201 frame.sf_ra = (int)ps->sa_sigdesc[sig].sd_tramp; 2202 break; 2203 2204 default: 2205 /* Don't know what trampoline version; kill it. */ 2206 sigexit(p, SIGILL); 2207 } 2208 2209 frame.sf_signum = sig; 2210 frame.sf_code = code; 2211 frame.sf_scp = &fp->sf_sc; 2212 2213 /* Save register context. */ 2214 #ifdef VM86 2215 if (tf->tf_eflags & PSL_VM) { 2216 frame.sf_sc.sc_gs = tf->tf_vm86_gs; 2217 frame.sf_sc.sc_fs = tf->tf_vm86_fs; 2218 frame.sf_sc.sc_es = tf->tf_vm86_es; 2219 frame.sf_sc.sc_ds = tf->tf_vm86_ds; 2220 frame.sf_sc.sc_eflags = get_vflags(p); 2221 (*p->p_emul->e_syscall_intern)(p); 2222 } else 2223 #endif 2224 { 2225 frame.sf_sc.sc_gs = tf->tf_gs; 2226 frame.sf_sc.sc_fs = tf->tf_fs; 2227 frame.sf_sc.sc_es = tf->tf_es; 2228 frame.sf_sc.sc_ds = tf->tf_ds; 2229 frame.sf_sc.sc_eflags = tf->tf_eflags; 2230 } 2231 frame.sf_sc.sc_edi = tf->tf_edi; 2232 frame.sf_sc.sc_esi = tf->tf_esi; 2233 frame.sf_sc.sc_ebp = tf->tf_ebp; 2234 frame.sf_sc.sc_ebx = tf->tf_ebx; 2235 frame.sf_sc.sc_edx = tf->tf_edx; 2236 frame.sf_sc.sc_ecx = tf->tf_ecx; 2237 frame.sf_sc.sc_eax = tf->tf_eax; 2238 frame.sf_sc.sc_eip = tf->tf_eip; 2239 frame.sf_sc.sc_cs = tf->tf_cs; 2240 frame.sf_sc.sc_esp = tf->tf_esp; 2241 frame.sf_sc.sc_ss = tf->tf_ss; 2242 frame.sf_sc.sc_trapno = tf->tf_trapno; 2243 frame.sf_sc.sc_err = tf->tf_err; 2244 2245 /* Save signal stack. */ 2246 frame.sf_sc.sc_onstack = p->p_sigctx.ps_sigstk.ss_flags & SS_ONSTACK; 2247 2248 /* Save signal mask. */ 2249 frame.sf_sc.sc_mask = *mask; 2250 2251 #ifdef COMPAT_13 2252 /* 2253 * XXX We always have to save an old style signal mask because 2254 * XXX we might be delivering a signal to a process which will 2255 * XXX escape from the signal in a non-standard way and invoke 2256 * XXX sigreturn() directly. 2257 */ 2258 native_sigset_to_sigset13(mask, &frame.sf_sc.__sc_mask13); 2259 #endif 2260 2261 if (copyout(&frame, fp, sizeof(frame)) != 0) { 2262 /* 2263 * Process has trashed its stack; give it an illegal 2264 * instruction to halt it in its tracks. 2265 */ 2266 sigexit(p, SIGILL); 2267 /* NOTREACHED */ 2268 } 2269 2270 /* 2271 * Build context to run handler in. We invoke the handler 2272 * directly, only returning via the trampoline. Note the 2273 * trampoline version numbers are coordinated with machine- 2274 * dependent code in libc. 2275 */ 2276 tf->tf_gs = GSEL(GUDATA_SEL, SEL_UPL); 2277 tf->tf_fs = GSEL(GUDATA_SEL, SEL_UPL); 2278 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2279 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2280 tf->tf_eip = (int)catcher; 2281 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2282 tf->tf_eflags &= ~(PSL_T|PSL_VM|PSL_AC); 2283 tf->tf_esp = (int)fp; 2284 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2285 2286 /* Remember that we're now on the signal stack. */ 2287 if (onstack) 2288 p->p_sigctx.ps_sigstk.ss_flags |= SS_ONSTACK; 2289 } 2290 2291 /* 2292 * System call to cleanup state after a signal 2293 * has been taken. Reset signal mask and 2294 * stack state from context left by sendsig (above). 2295 * Return to previous pc and psl as specified by 2296 * context left by sendsig. Check carefully to 2297 * make sure that the user has not modified the 2298 * psl to gain improper privileges or to cause 2299 * a machine fault. 2300 */ 2301 int 2302 sys___sigreturn14(p, v, retval) 2303 struct proc *p; 2304 void *v; 2305 register_t *retval; 2306 { 2307 struct sys___sigreturn14_args /* { 2308 syscallarg(struct sigcontext *) sigcntxp; 2309 } */ *uap = v; 2310 struct sigcontext *scp, context; 2311 struct trapframe *tf; 2312 2313 /* 2314 * The trampoline code hands us the context. 2315 * It is unsafe to keep track of it ourselves, in the event that a 2316 * program jumps out of a signal handler. 2317 */ 2318 scp = SCARG(uap, sigcntxp); 2319 if (copyin((caddr_t)scp, &context, sizeof(*scp)) != 0) 2320 return (EFAULT); 2321 2322 /* Restore register context. */ 2323 tf = p->p_md.md_regs; 2324 #ifdef VM86 2325 if (context.sc_eflags & PSL_VM) { 2326 void syscall_vm86 __P((struct trapframe)); 2327 2328 tf->tf_vm86_gs = context.sc_gs; 2329 tf->tf_vm86_fs = context.sc_fs; 2330 tf->tf_vm86_es = context.sc_es; 2331 tf->tf_vm86_ds = context.sc_ds; 2332 set_vflags(p, context.sc_eflags); 2333 p->p_md.md_syscall = syscall_vm86; 2334 } else 2335 #endif 2336 { 2337 /* 2338 * Check for security violations. If we're returning to 2339 * protected mode, the CPU will validate the segment registers 2340 * automatically and generate a trap on violations. We handle 2341 * the trap, rather than doing all of the checking here. 2342 */ 2343 if (((context.sc_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 || 2344 !USERMODE(context.sc_cs, context.sc_eflags)) 2345 return (EINVAL); 2346 2347 tf->tf_gs = context.sc_gs; 2348 tf->tf_fs = context.sc_fs; 2349 tf->tf_es = context.sc_es; 2350 tf->tf_ds = context.sc_ds; 2351 tf->tf_eflags = context.sc_eflags; 2352 } 2353 tf->tf_edi = context.sc_edi; 2354 tf->tf_esi = context.sc_esi; 2355 tf->tf_ebp = context.sc_ebp; 2356 tf->tf_ebx = context.sc_ebx; 2357 tf->tf_edx = context.sc_edx; 2358 tf->tf_ecx = context.sc_ecx; 2359 tf->tf_eax = context.sc_eax; 2360 tf->tf_eip = context.sc_eip; 2361 tf->tf_cs = context.sc_cs; 2362 tf->tf_esp = context.sc_esp; 2363 tf->tf_ss = context.sc_ss; 2364 2365 /* Restore signal stack. */ 2366 if (context.sc_onstack & SS_ONSTACK) 2367 p->p_sigctx.ps_sigstk.ss_flags |= SS_ONSTACK; 2368 else 2369 p->p_sigctx.ps_sigstk.ss_flags &= ~SS_ONSTACK; 2370 2371 /* Restore signal mask. */ 2372 (void) sigprocmask1(p, SIG_SETMASK, &context.sc_mask, 0); 2373 2374 return (EJUSTRETURN); 2375 } 2376 2377 int waittime = -1; 2378 struct pcb dumppcb; 2379 2380 void 2381 cpu_reboot(howto, bootstr) 2382 int howto; 2383 char *bootstr; 2384 { 2385 2386 if (cold) { 2387 howto |= RB_HALT; 2388 goto haltsys; 2389 } 2390 2391 boothowto = howto; 2392 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 2393 waittime = 0; 2394 vfs_shutdown(); 2395 /* 2396 * If we've been adjusting the clock, the todr 2397 * will be out of synch; adjust it now. 2398 */ 2399 resettodr(); 2400 } 2401 2402 /* Disable interrupts. */ 2403 splhigh(); 2404 2405 /* Do a dump if requested. */ 2406 if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) 2407 dumpsys(); 2408 2409 haltsys: 2410 doshutdownhooks(); 2411 2412 #ifdef MULTIPROCESSOR 2413 i386_broadcast_ipi(I386_IPI_HALT); 2414 #endif 2415 2416 if ((howto & RB_POWERDOWN) == RB_POWERDOWN) { 2417 #if NACPI > 0 2418 delay(500000); 2419 acpi_enter_sleep_state(acpi_softc, ACPI_STATE_S5); 2420 printf("WARNING: powerdown failed!\n"); 2421 #endif 2422 #if NAPM > 0 && !defined(APM_NO_POWEROFF) 2423 /* turn off, if we can. But try to turn disk off and 2424 * wait a bit first--some disk drives are slow to clean up 2425 * and users have reported disk corruption. 2426 */ 2427 delay(500000); 2428 apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2429 delay(500000); 2430 apm_set_powstate(APM_DEV_ALLDEVS, APM_SYS_OFF); 2431 printf("WARNING: powerdown failed!\n"); 2432 /* 2433 * RB_POWERDOWN implies RB_HALT... fall into it... 2434 */ 2435 #endif 2436 } 2437 2438 if (howto & RB_HALT) { 2439 printf("\n"); 2440 printf("The operating system has halted.\n"); 2441 printf("Please press any key to reboot.\n\n"); 2442 cnpollc(1); /* for proper keyboard command handling */ 2443 cngetc(); 2444 cnpollc(0); 2445 } 2446 2447 printf("rebooting...\n"); 2448 if (cpureset_delay > 0) 2449 delay(cpureset_delay * 1000); 2450 cpu_reset(); 2451 for(;;) ; 2452 /*NOTREACHED*/ 2453 } 2454 2455 /* 2456 * These variables are needed by /sbin/savecore 2457 */ 2458 u_int32_t dumpmag = 0x8fca0101; /* magic number */ 2459 int dumpsize = 0; /* pages */ 2460 long dumplo = 0; /* blocks */ 2461 2462 /* 2463 * cpu_dumpsize: calculate size of machine-dependent kernel core dump headers. 2464 */ 2465 int 2466 cpu_dumpsize() 2467 { 2468 int size; 2469 2470 size = ALIGN(sizeof(kcore_seg_t)) + ALIGN(sizeof(cpu_kcore_hdr_t)) + 2471 ALIGN(mem_cluster_cnt * sizeof(phys_ram_seg_t)); 2472 if (roundup(size, dbtob(1)) != dbtob(1)) 2473 return (-1); 2474 2475 return (1); 2476 } 2477 2478 /* 2479 * cpu_dump_mempagecnt: calculate the size of RAM (in pages) to be dumped. 2480 */ 2481 u_long 2482 cpu_dump_mempagecnt() 2483 { 2484 u_long i, n; 2485 2486 n = 0; 2487 for (i = 0; i < mem_cluster_cnt; i++) 2488 n += atop(mem_clusters[i].size); 2489 return (n); 2490 } 2491 2492 /* 2493 * cpu_dump: dump the machine-dependent kernel core dump headers. 2494 */ 2495 int 2496 cpu_dump() 2497 { 2498 int (*dump) __P((dev_t, daddr_t, caddr_t, size_t)); 2499 char buf[dbtob(1)]; 2500 kcore_seg_t *segp; 2501 cpu_kcore_hdr_t *cpuhdrp; 2502 phys_ram_seg_t *memsegp; 2503 const struct bdevsw *bdev; 2504 int i; 2505 2506 bdev = bdevsw_lookup(dumpdev); 2507 if (bdev == NULL) 2508 return (ENXIO); 2509 dump = bdev->d_dump; 2510 2511 memset(buf, 0, sizeof buf); 2512 segp = (kcore_seg_t *)buf; 2513 cpuhdrp = (cpu_kcore_hdr_t *)&buf[ALIGN(sizeof(*segp))]; 2514 memsegp = (phys_ram_seg_t *)&buf[ ALIGN(sizeof(*segp)) + 2515 ALIGN(sizeof(*cpuhdrp))]; 2516 2517 /* 2518 * Generate a segment header. 2519 */ 2520 CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 2521 segp->c_size = dbtob(1) - ALIGN(sizeof(*segp)); 2522 2523 /* 2524 * Add the machine-dependent header info. 2525 */ 2526 cpuhdrp->ptdpaddr = PTDpaddr; 2527 cpuhdrp->nmemsegs = mem_cluster_cnt; 2528 2529 /* 2530 * Fill in the memory segment descriptors. 2531 */ 2532 for (i = 0; i < mem_cluster_cnt; i++) { 2533 memsegp[i].start = mem_clusters[i].start; 2534 memsegp[i].size = mem_clusters[i].size; 2535 } 2536 2537 return (dump(dumpdev, dumplo, (caddr_t)buf, dbtob(1))); 2538 } 2539 2540 /* 2541 * This is called by main to set dumplo and dumpsize. 2542 * Dumps always skip the first PAGE_SIZE of disk space 2543 * in case there might be a disk label stored there. 2544 * If there is extra space, put dump at the end to 2545 * reduce the chance that swapping trashes it. 2546 */ 2547 void 2548 cpu_dumpconf() 2549 { 2550 const struct bdevsw *bdev; 2551 int nblks, dumpblks; /* size of dump area */ 2552 2553 if (dumpdev == NODEV) 2554 goto bad; 2555 bdev = bdevsw_lookup(dumpdev); 2556 if (bdev == NULL) 2557 panic("dumpconf: bad dumpdev=0x%x", dumpdev); 2558 if (bdev->d_psize == NULL) 2559 goto bad; 2560 nblks = (*bdev->d_psize)(dumpdev); 2561 if (nblks <= ctod(1)) 2562 goto bad; 2563 2564 dumpblks = cpu_dumpsize(); 2565 if (dumpblks < 0) 2566 goto bad; 2567 dumpblks += ctod(cpu_dump_mempagecnt()); 2568 2569 /* If dump won't fit (incl. room for possible label), punt. */ 2570 if (dumpblks > (nblks - ctod(1))) 2571 goto bad; 2572 2573 /* Put dump at end of partition */ 2574 dumplo = nblks - dumpblks; 2575 2576 /* dumpsize is in page units, and doesn't include headers. */ 2577 dumpsize = cpu_dump_mempagecnt(); 2578 return; 2579 2580 bad: 2581 dumpsize = 0; 2582 } 2583 2584 /* 2585 * Doadump comes here after turning off memory management and 2586 * getting on the dump stack, either when called above, or by 2587 * the auto-restart code. 2588 */ 2589 #define BYTES_PER_DUMP PAGE_SIZE /* must be a multiple of pagesize XXX small */ 2590 static vaddr_t dumpspace; 2591 2592 vaddr_t 2593 reserve_dumppages(p) 2594 vaddr_t p; 2595 { 2596 2597 dumpspace = p; 2598 return (p + BYTES_PER_DUMP); 2599 } 2600 2601 void 2602 dumpsys() 2603 { 2604 u_long totalbytesleft, bytes, i, n, memseg; 2605 u_long maddr; 2606 int psize; 2607 daddr_t blkno; 2608 const struct bdevsw *bdev; 2609 int (*dump) __P((dev_t, daddr_t, caddr_t, size_t)); 2610 int error; 2611 2612 /* Save registers. */ 2613 savectx(&dumppcb); 2614 2615 if (dumpdev == NODEV) 2616 return; 2617 2618 bdev = bdevsw_lookup(dumpdev); 2619 if (bdev == NULL || bdev->d_psize == NULL) 2620 return; 2621 2622 /* 2623 * For dumps during autoconfiguration, 2624 * if dump device has already configured... 2625 */ 2626 if (dumpsize == 0) 2627 cpu_dumpconf(); 2628 if (dumplo <= 0 || dumpsize == 0) { 2629 printf("\ndump to dev %u,%u not possible\n", major(dumpdev), 2630 minor(dumpdev)); 2631 return; 2632 } 2633 printf("\ndumping to dev %u,%u offset %ld\n", major(dumpdev), 2634 minor(dumpdev), dumplo); 2635 2636 psize = (*bdev->d_psize)(dumpdev); 2637 printf("dump "); 2638 if (psize == -1) { 2639 printf("area unavailable\n"); 2640 return; 2641 } 2642 2643 #if 0 /* XXX this doesn't work. grr. */ 2644 /* toss any characters present prior to dump */ 2645 while (sget() != NULL); /*syscons and pccons differ */ 2646 #endif 2647 2648 if ((error = cpu_dump()) != 0) 2649 goto err; 2650 2651 totalbytesleft = ptoa(cpu_dump_mempagecnt()); 2652 blkno = dumplo + cpu_dumpsize(); 2653 dump = bdev->d_dump; 2654 error = 0; 2655 2656 for (memseg = 0; memseg < mem_cluster_cnt; memseg++) { 2657 maddr = mem_clusters[memseg].start; 2658 bytes = mem_clusters[memseg].size; 2659 2660 for (i = 0; i < bytes; i += n, totalbytesleft -= n) { 2661 /* Print out how many MBs we have left to go. */ 2662 if ((totalbytesleft % (1024*1024)) == 0) 2663 printf("%ld ", totalbytesleft / (1024 * 1024)); 2664 2665 /* Limit size for next transfer. */ 2666 n = bytes - i; 2667 if (n > BYTES_PER_DUMP) 2668 n = BYTES_PER_DUMP; 2669 2670 (void) pmap_map(dumpspace, maddr, maddr + n, 2671 VM_PROT_READ); 2672 2673 error = (*dump)(dumpdev, blkno, (caddr_t)dumpspace, n); 2674 if (error) 2675 goto err; 2676 maddr += n; 2677 blkno += btodb(n); /* XXX? */ 2678 2679 #if 0 /* XXX this doesn't work. grr. */ 2680 /* operator aborting dump? */ 2681 if (sget() != NULL) { 2682 error = EINTR; 2683 break; 2684 } 2685 #endif 2686 } 2687 } 2688 2689 err: 2690 switch (error) { 2691 2692 case ENXIO: 2693 printf("device bad\n"); 2694 break; 2695 2696 case EFAULT: 2697 printf("device not ready\n"); 2698 break; 2699 2700 case EINVAL: 2701 printf("area improper\n"); 2702 break; 2703 2704 case EIO: 2705 printf("i/o error\n"); 2706 break; 2707 2708 case EINTR: 2709 printf("aborted from console\n"); 2710 break; 2711 2712 case 0: 2713 printf("succeeded\n"); 2714 break; 2715 2716 default: 2717 printf("error %d\n", error); 2718 break; 2719 } 2720 printf("\n\n"); 2721 delay(5000000); /* 5 seconds */ 2722 } 2723 2724 /* 2725 * Clear registers on exec 2726 */ 2727 void 2728 setregs(p, pack, stack) 2729 struct proc *p; 2730 struct exec_package *pack; 2731 u_long stack; 2732 { 2733 struct pcb *pcb = &p->p_addr->u_pcb; 2734 struct trapframe *tf; 2735 2736 #if NNPX > 0 2737 /* If we were using the FPU, forget about it. */ 2738 if (p->p_addr->u_pcb.pcb_fpcpu != NULL) 2739 npxsave_proc(p, 0); 2740 #endif 2741 2742 #ifdef USER_LDT 2743 pmap_ldt_cleanup(p); 2744 #endif 2745 2746 p->p_md.md_flags &= ~MDP_USEDFPU; 2747 if (i386_use_fxsave) { 2748 pcb->pcb_savefpu.sv_xmm.sv_env.en_cw = __NetBSD_NPXCW__; 2749 pcb->pcb_savefpu.sv_xmm.sv_env.en_mxcsr = __INITIAL_MXCSR__; 2750 } else 2751 pcb->pcb_savefpu.sv_87.sv_env.en_cw = __NetBSD_NPXCW__; 2752 2753 tf = p->p_md.md_regs; 2754 tf->tf_gs = LSEL(LUDATA_SEL, SEL_UPL); 2755 tf->tf_fs = LSEL(LUDATA_SEL, SEL_UPL); 2756 tf->tf_es = LSEL(LUDATA_SEL, SEL_UPL); 2757 tf->tf_ds = LSEL(LUDATA_SEL, SEL_UPL); 2758 tf->tf_edi = 0; 2759 tf->tf_esi = 0; 2760 tf->tf_ebp = 0; 2761 tf->tf_ebx = (int)p->p_psstr; 2762 tf->tf_edx = 0; 2763 tf->tf_ecx = 0; 2764 tf->tf_eax = 0; 2765 tf->tf_eip = pack->ep_entry; 2766 tf->tf_cs = LSEL(LUCODE_SEL, SEL_UPL); 2767 tf->tf_eflags = PSL_USERSET; 2768 tf->tf_esp = stack; 2769 tf->tf_ss = LSEL(LUDATA_SEL, SEL_UPL); 2770 } 2771 2772 /* 2773 * Initialize segments and descriptor tables 2774 */ 2775 2776 union descriptor *idt, *gdt, *ldt; 2777 char idt_allocmap[NIDT]; 2778 struct simplelock idt_lock = SIMPLELOCK_INITIALIZER; 2779 #ifdef I586_CPU 2780 union descriptor *pentium_idt; 2781 #endif 2782 extern struct user *proc0paddr; 2783 2784 void 2785 setgate(gd, func, args, type, dpl, sel) 2786 struct gate_descriptor *gd; 2787 void *func; 2788 int args, type, dpl, sel; 2789 { 2790 2791 gd->gd_looffset = (int)func; 2792 gd->gd_selector = sel; 2793 gd->gd_stkcpy = args; 2794 gd->gd_xx = 0; 2795 gd->gd_type = type; 2796 gd->gd_dpl = dpl; 2797 gd->gd_p = 1; 2798 gd->gd_hioffset = (int)func >> 16; 2799 } 2800 2801 void 2802 unsetgate(gd) 2803 struct gate_descriptor *gd; 2804 { 2805 gd->gd_p = 0; 2806 gd->gd_hioffset = 0; 2807 gd->gd_looffset = 0; 2808 gd->gd_selector = 0; 2809 gd->gd_xx = 0; 2810 gd->gd_stkcpy = 0; 2811 gd->gd_type = 0; 2812 gd->gd_dpl = 0; 2813 } 2814 2815 2816 void 2817 setregion(rd, base, limit) 2818 struct region_descriptor *rd; 2819 void *base; 2820 size_t limit; 2821 { 2822 2823 rd->rd_limit = (int)limit; 2824 rd->rd_base = (int)base; 2825 } 2826 2827 void 2828 setsegment(sd, base, limit, type, dpl, def32, gran) 2829 struct segment_descriptor *sd; 2830 void *base; 2831 size_t limit; 2832 int type, dpl, def32, gran; 2833 { 2834 2835 sd->sd_lolimit = (int)limit; 2836 sd->sd_lobase = (int)base; 2837 sd->sd_type = type; 2838 sd->sd_dpl = dpl; 2839 sd->sd_p = 1; 2840 sd->sd_hilimit = (int)limit >> 16; 2841 sd->sd_xx = 0; 2842 sd->sd_def32 = def32; 2843 sd->sd_gran = gran; 2844 sd->sd_hibase = (int)base >> 24; 2845 } 2846 2847 #define IDTVEC(name) __CONCAT(X, name) 2848 typedef void (vector) __P((void)); 2849 extern vector IDTVEC(syscall); 2850 extern vector IDTVEC(osyscall); 2851 extern vector *IDTVEC(exceptions)[]; 2852 #ifdef COMPAT_SVR4 2853 extern vector IDTVEC(svr4_fasttrap); 2854 #endif /* COMPAT_SVR4 */ 2855 #ifdef COMPAT_MACH 2856 extern vector IDTVEC(mach_trap); 2857 #endif 2858 2859 #define KBTOB(x) ((size_t)(x) * 1024UL) 2860 2861 void cpu_init_idt() 2862 { 2863 struct region_descriptor region; 2864 #ifdef I586_CPU 2865 setregion(®ion, pentium_idt, NIDT * sizeof(idt[0]) - 1); 2866 #else 2867 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 2868 #endif 2869 lidt(®ion); 2870 } 2871 2872 #if !defined(REALBASEMEM) && !defined(REALEXTMEM) 2873 void 2874 add_mem_cluster(seg_start, seg_end, type) 2875 u_int64_t seg_start, seg_end; 2876 u_int32_t type; 2877 { 2878 extern struct extent *iomem_ex; 2879 int i; 2880 2881 if (seg_end > 0x100000000ULL) { 2882 printf("WARNING: skipping large " 2883 "memory map entry: " 2884 "0x%qx/0x%qx/0x%x\n", 2885 seg_start, 2886 (seg_end - seg_start), 2887 type); 2888 return; 2889 } 2890 2891 /* 2892 * XXX Chop the last page off the size so that 2893 * XXX it can fit in avail_end. 2894 */ 2895 if (seg_end == 0x100000000ULL) 2896 seg_end -= PAGE_SIZE; 2897 2898 if (seg_end <= seg_start) 2899 return; 2900 2901 for (i = 0; i < mem_cluster_cnt; i++) { 2902 if ((mem_clusters[i].start == round_page(seg_start)) 2903 && (mem_clusters[i].size 2904 == trunc_page(seg_end) - mem_clusters[i].start)) { 2905 #ifdef DEBUG_MEMLOAD 2906 printf("WARNING: skipping duplicate segment entry\n"); 2907 #endif 2908 return; 2909 } 2910 } 2911 2912 /* 2913 * Allocate the physical addresses used by RAM 2914 * from the iomem extent map. This is done before 2915 * the addresses are page rounded just to make 2916 * sure we get them all. 2917 */ 2918 if (extent_alloc_region(iomem_ex, seg_start, 2919 seg_end - seg_start, EX_NOWAIT)) { 2920 /* XXX What should we do? */ 2921 printf("WARNING: CAN'T ALLOCATE " 2922 "MEMORY SEGMENT " 2923 "(0x%qx/0x%qx/0x%x) FROM " 2924 "IOMEM EXTENT MAP!\n", 2925 seg_start, seg_end - seg_start, type); 2926 return; 2927 } 2928 2929 /* 2930 * If it's not free memory, skip it. 2931 */ 2932 if (type != BIM_Memory) 2933 return; 2934 2935 /* XXX XXX XXX */ 2936 if (mem_cluster_cnt >= VM_PHYSSEG_MAX) 2937 panic("init386: too many memory segments"); 2938 2939 seg_start = round_page(seg_start); 2940 seg_end = trunc_page(seg_end); 2941 2942 if (seg_start == seg_end) 2943 return; 2944 2945 mem_clusters[mem_cluster_cnt].start = seg_start; 2946 mem_clusters[mem_cluster_cnt].size = 2947 seg_end - seg_start; 2948 2949 if (avail_end < seg_end) 2950 avail_end = seg_end; 2951 physmem += atop(mem_clusters[mem_cluster_cnt].size); 2952 mem_cluster_cnt++; 2953 } 2954 #endif /* !defined(REALBASEMEM) && !defined(REALEXTMEM) */ 2955 2956 void 2957 initgdt(union descriptor *tgdt) 2958 { 2959 struct region_descriptor region; 2960 gdt = tgdt; 2961 memset(gdt, 0, NGDT*sizeof(*gdt)); 2962 /* make gdt gates and memory segments */ 2963 setsegment(&gdt[GCODE_SEL].sd, 0, 0xfffff, SDT_MEMERA, SEL_KPL, 1, 1); 2964 setsegment(&gdt[GDATA_SEL].sd, 0, 0xfffff, SDT_MEMRWA, SEL_KPL, 1, 1); 2965 setsegment(&gdt[GUCODE_SEL].sd, 0, i386_btop(VM_MAXUSER_ADDRESS) - 1, 2966 SDT_MEMERA, SEL_UPL, 1, 1); 2967 setsegment(&gdt[GUDATA_SEL].sd, 0, i386_btop(VM_MAXUSER_ADDRESS) - 1, 2968 SDT_MEMRWA, SEL_UPL, 1, 1); 2969 #ifdef COMPAT_MACH 2970 setgate(&gdt[GMACHCALLS_SEL].gd, &IDTVEC(mach_trap), 1, 2971 SDT_SYS386CGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL)); 2972 #endif 2973 #if NBIOSCALL > 0 2974 /* bios trampoline GDT entries */ 2975 setsegment(&gdt[GBIOSCODE_SEL].sd, 0, 0xfffff, SDT_MEMERA, SEL_KPL, 0, 2976 0); 2977 setsegment(&gdt[GBIOSDATA_SEL].sd, 0, 0xfffff, SDT_MEMRWA, SEL_KPL, 0, 2978 0); 2979 #endif 2980 setsegment(&gdt[GCPU_SEL].sd, &cpu_info_primary, 2981 sizeof(struct cpu_info)-1, SDT_MEMRWA, SEL_KPL, 1, 1); 2982 2983 setregion(®ion, gdt, NGDT * sizeof(gdt[0]) - 1); 2984 lgdt(®ion); 2985 } 2986 2987 void 2988 init386(first_avail) 2989 paddr_t first_avail; 2990 { 2991 union descriptor *tgdt; 2992 extern void consinit __P((void)); 2993 extern struct extent *iomem_ex; 2994 #if !defined(REALBASEMEM) && !defined(REALEXTMEM) 2995 struct btinfo_memmap *bim; 2996 #endif 2997 struct region_descriptor region; 2998 int x, first16q; 2999 u_int64_t seg_start, seg_end; 3000 u_int64_t seg_start1, seg_end1; 3001 paddr_t realmode_reserved_start; 3002 psize_t realmode_reserved_size; 3003 int needs_earlier_install_pte0; 3004 #if NBIOSCALL > 0 3005 extern int biostramp_image_size; 3006 extern u_char biostramp_image[]; 3007 #endif 3008 3009 cpu_probe_features(&cpu_info_primary); 3010 cpu_feature = cpu_info_primary.ci_feature_flags; 3011 3012 proc0.p_addr = proc0paddr; 3013 cpu_info_primary.ci_curpcb = &proc0.p_addr->u_pcb; 3014 3015 i386_bus_space_init(); 3016 consinit(); /* XXX SHOULD NOT BE DONE HERE */ 3017 /* 3018 * Initailize PAGE_SIZE-dependent variables. 3019 */ 3020 uvm_setpagesize(); 3021 /* 3022 * A quick sanity check. 3023 */ 3024 if (PAGE_SIZE != NBPG) 3025 panic("init386: PAGE_SIZE != NBPG"); 3026 3027 /* 3028 * Saving SSE registers won't work if the save area isn't 3029 * 16-byte aligned. 3030 */ 3031 if (offsetof(struct user, u_pcb.pcb_savefpu) & 0xf) 3032 panic("init386: pcb_savefpu not 16-byte aligned"); 3033 3034 /* 3035 * Start with 2 color bins -- this is just a guess to get us 3036 * started. We'll recolor when we determine the largest cache 3037 * sizes on the system. 3038 */ 3039 uvmexp.ncolors = 2; 3040 3041 /* 3042 * BIOS leaves data in physical page 0 3043 * Even if it didn't, our VM system doesn't like using zero as a 3044 * physical page number. 3045 * We may also need pages in low memory (one each) for secondary CPU 3046 * startup, for BIOS calls, and for ACPI, plus a page table page to map 3047 * them into the first few pages of the kernel's pmap. 3048 */ 3049 avail_start = PAGE_SIZE; 3050 3051 /* 3052 * reserve memory for real-mode call 3053 */ 3054 needs_earlier_install_pte0 = 0; 3055 realmode_reserved_start = 0; 3056 realmode_reserved_size = 0; 3057 #if NBIOSCALL > 0 3058 /* save us a page for trampoline code */ 3059 realmode_reserved_size += PAGE_SIZE; 3060 needs_earlier_install_pte0 = 1; 3061 #endif 3062 #ifdef MULTIPROCESSOR /* XXX */ 3063 KASSERT(avail_start == PAGE_SIZE); /* XXX */ 3064 if (realmode_reserved_size < MP_TRAMPOLINE) /* XXX */ 3065 realmode_reserved_size = MP_TRAMPOLINE; /* XXX */ 3066 needs_earlier_install_pte0 = 1; /* XXX */ 3067 #endif /* XXX */ 3068 #if NACPI > 0 3069 /* trampoline code for wake handler */ 3070 realmode_reserved_size += ptoa(acpi_md_get_npages_of_wakecode()+1); 3071 needs_earlier_install_pte0 = 1; 3072 #endif 3073 if (needs_earlier_install_pte0) { 3074 /* page table for directory entry 0 */ 3075 realmode_reserved_size += PAGE_SIZE; 3076 } 3077 if (realmode_reserved_size>0) { 3078 realmode_reserved_start = avail_start; 3079 avail_start += realmode_reserved_size; 3080 } 3081 3082 #ifdef DEBUG_MEMLOAD 3083 printf("mem_cluster_count: %d\n", mem_cluster_cnt); 3084 #endif 3085 3086 /* 3087 * Call pmap initialization to make new kernel address space. 3088 * We must do this before loading pages into the VM system. 3089 */ 3090 pmap_bootstrap((vaddr_t)atdevbase + IOM_SIZE); 3091 3092 #if !defined(REALBASEMEM) && !defined(REALEXTMEM) 3093 /* 3094 * Check to see if we have a memory map from the BIOS (passed 3095 * to us by the boot program. 3096 */ 3097 bim = lookup_bootinfo(BTINFO_MEMMAP); 3098 if (bim != NULL && bim->num > 0) { 3099 #ifdef DEBUG_MEMLOAD 3100 printf("BIOS MEMORY MAP (%d ENTRIES):\n", bim->num); 3101 #endif 3102 for (x = 0; x < bim->num; x++) { 3103 #ifdef DEBUG_MEMLOAD 3104 printf(" addr 0x%qx size 0x%qx type 0x%x\n", 3105 bim->entry[x].addr, 3106 bim->entry[x].size, 3107 bim->entry[x].type); 3108 #endif 3109 3110 /* 3111 * If the segment is not memory, skip it. 3112 */ 3113 switch (bim->entry[x].type) { 3114 case BIM_Memory: 3115 case BIM_ACPI: 3116 case BIM_NVS: 3117 break; 3118 default: 3119 continue; 3120 } 3121 3122 /* 3123 * Sanity check the entry. 3124 * XXX Need to handle uint64_t in extent code 3125 * XXX and 64-bit physical addresses in i386 3126 * XXX port. 3127 */ 3128 seg_start = bim->entry[x].addr; 3129 seg_end = bim->entry[x].addr + bim->entry[x].size; 3130 3131 /* 3132 * Avoid Compatibility Holes. 3133 * XXX Holes within memory space that allow access 3134 * XXX to be directed to the PC-compatible frame buffer 3135 * XXX (0xa0000-0xbffff),to adapter ROM space 3136 * XXX (0xc0000-0xdffff), and to system BIOS space 3137 * XXX (0xe0000-0xfffff). 3138 * XXX Some laptop(for example,Toshiba Satellite2550X) 3139 * XXX report this area and occurred problems, 3140 * XXX so we avoid this area. 3141 */ 3142 if (seg_start < 0x100000 && seg_end > 0xa0000) { 3143 printf("WARNING: memory map entry overlaps " 3144 "with ``Compatibility Holes'': " 3145 "0x%qx/0x%qx/0x%x\n", seg_start, 3146 seg_end - seg_start, bim->entry[x].type); 3147 add_mem_cluster(seg_start, 0xa0000, 3148 bim->entry[x].type); 3149 add_mem_cluster(0x100000, seg_end, 3150 bim->entry[x].type); 3151 } else 3152 add_mem_cluster(seg_start, seg_end, 3153 bim->entry[x].type); 3154 } 3155 } 3156 #endif /* ! REALBASEMEM && ! REALEXTMEM */ 3157 /* 3158 * If the loop above didn't find any valid segment, fall back to 3159 * former code. 3160 */ 3161 if (mem_cluster_cnt == 0) { 3162 /* 3163 * Allocate the physical addresses used by RAM from the iomem 3164 * extent map. This is done before the addresses are 3165 * page rounded just to make sure we get them all. 3166 */ 3167 if (extent_alloc_region(iomem_ex, 0, KBTOB(biosbasemem), 3168 EX_NOWAIT)) { 3169 /* XXX What should we do? */ 3170 printf("WARNING: CAN'T ALLOCATE BASE MEMORY FROM " 3171 "IOMEM EXTENT MAP!\n"); 3172 } 3173 mem_clusters[0].start = 0; 3174 mem_clusters[0].size = trunc_page(KBTOB(biosbasemem)); 3175 physmem += atop(mem_clusters[0].size); 3176 if (extent_alloc_region(iomem_ex, IOM_END, KBTOB(biosextmem), 3177 EX_NOWAIT)) { 3178 /* XXX What should we do? */ 3179 printf("WARNING: CAN'T ALLOCATE EXTENDED MEMORY FROM " 3180 "IOMEM EXTENT MAP!\n"); 3181 } 3182 #if NISADMA > 0 3183 /* 3184 * Some motherboards/BIOSes remap the 384K of RAM that would 3185 * normally be covered by the ISA hole to the end of memory 3186 * so that it can be used. However, on a 16M system, this 3187 * would cause bounce buffers to be allocated and used. 3188 * This is not desirable behaviour, as more than 384K of 3189 * bounce buffers might be allocated. As a work-around, 3190 * we round memory down to the nearest 1M boundary if 3191 * we're using any isadma devices and the remapped memory 3192 * is what puts us over 16M. 3193 */ 3194 if (biosextmem > (15*1024) && biosextmem < (16*1024)) { 3195 char pbuf[9]; 3196 3197 format_bytes(pbuf, sizeof(pbuf), 3198 biosextmem - (15*1024)); 3199 printf("Warning: ignoring %s of remapped memory\n", 3200 pbuf); 3201 biosextmem = (15*1024); 3202 } 3203 #endif 3204 mem_clusters[1].start = IOM_END; 3205 mem_clusters[1].size = trunc_page(KBTOB(biosextmem)); 3206 physmem += atop(mem_clusters[1].size); 3207 3208 mem_cluster_cnt = 2; 3209 3210 avail_end = IOM_END + trunc_page(KBTOB(biosextmem)); 3211 } 3212 /* 3213 * If we have 16M of RAM or less, just put it all on 3214 * the default free list. Otherwise, put the first 3215 * 16M of RAM on a lower priority free list (so that 3216 * all of the ISA DMA'able memory won't be eaten up 3217 * first-off). 3218 */ 3219 if (avail_end <= (16 * 1024 * 1024)) 3220 first16q = VM_FREELIST_DEFAULT; 3221 else 3222 first16q = VM_FREELIST_FIRST16; 3223 3224 /* Make sure the end of the space used by the kernel is rounded. */ 3225 first_avail = round_page(first_avail); 3226 3227 /* 3228 * Now, load the memory clusters (which have already been 3229 * rounded and truncated) into the VM system. 3230 * 3231 * NOTE: WE ASSUME THAT MEMORY STARTS AT 0 AND THAT THE KERNEL 3232 * IS LOADED AT IOM_END (1M). 3233 */ 3234 for (x = 0; x < mem_cluster_cnt; x++) { 3235 seg_start = mem_clusters[x].start; 3236 seg_end = mem_clusters[x].start + mem_clusters[x].size; 3237 seg_start1 = 0; 3238 seg_end1 = 0; 3239 3240 /* 3241 * Skip memory before our available starting point. 3242 */ 3243 if (seg_end <= avail_start) 3244 continue; 3245 3246 if (avail_start >= seg_start && avail_start < seg_end) { 3247 if (seg_start != 0) 3248 panic("init386: memory doesn't start at 0"); 3249 seg_start = avail_start; 3250 if (seg_start == seg_end) 3251 continue; 3252 } 3253 3254 /* 3255 * If this segment contains the kernel, split it 3256 * in two, around the kernel. 3257 */ 3258 if (seg_start <= IOM_END && first_avail <= seg_end) { 3259 seg_start1 = first_avail; 3260 seg_end1 = seg_end; 3261 seg_end = IOM_END; 3262 } 3263 3264 /* First hunk */ 3265 if (seg_start != seg_end) { 3266 if (seg_start < (16 * 1024 * 1024) && 3267 first16q != VM_FREELIST_DEFAULT) { 3268 u_int64_t tmp; 3269 3270 if (seg_end > (16 * 1024 * 1024)) 3271 tmp = (16 * 1024 * 1024); 3272 else 3273 tmp = seg_end; 3274 3275 if (tmp != seg_start) { 3276 #ifdef DEBUG_MEMLOAD 3277 printf("loading 0x%qx-0x%qx " 3278 "(0x%lx-0x%lx)\n", 3279 seg_start, tmp, 3280 atop(seg_start), atop(tmp)); 3281 #endif 3282 uvm_page_physload(atop(seg_start), 3283 atop(tmp), atop(seg_start), 3284 atop(tmp), first16q); 3285 } 3286 seg_start = tmp; 3287 } 3288 3289 if (seg_start != seg_end) { 3290 #ifdef DEBUG_MEMLOAD 3291 printf("loading 0x%qx-0x%qx (0x%lx-0x%lx)\n", 3292 seg_start, seg_end, 3293 atop(seg_start), atop(seg_end)); 3294 #endif 3295 uvm_page_physload(atop(seg_start), 3296 atop(seg_end), atop(seg_start), 3297 atop(seg_end), VM_FREELIST_DEFAULT); 3298 } 3299 } 3300 3301 /* Second hunk */ 3302 if (seg_start1 != seg_end1) { 3303 if (seg_start1 < (16 * 1024 * 1024) && 3304 first16q != VM_FREELIST_DEFAULT) { 3305 u_int64_t tmp; 3306 3307 if (seg_end1 > (16 * 1024 * 1024)) 3308 tmp = (16 * 1024 * 1024); 3309 else 3310 tmp = seg_end1; 3311 3312 if (tmp != seg_start1) { 3313 #ifdef DEBUG_MEMLOAD 3314 printf("loading 0x%qx-0x%qx " 3315 "(0x%lx-0x%lx)\n", 3316 seg_start1, tmp, 3317 atop(seg_start1), atop(tmp)); 3318 #endif 3319 uvm_page_physload(atop(seg_start1), 3320 atop(tmp), atop(seg_start1), 3321 atop(tmp), first16q); 3322 } 3323 seg_start1 = tmp; 3324 } 3325 3326 if (seg_start1 != seg_end1) { 3327 #ifdef DEBUG_MEMLOAD 3328 printf("loading 0x%qx-0x%qx (0x%lx-0x%lx)\n", 3329 seg_start1, seg_end1, 3330 atop(seg_start1), atop(seg_end1)); 3331 #endif 3332 uvm_page_physload(atop(seg_start1), 3333 atop(seg_end1), atop(seg_start1), 3334 atop(seg_end1), VM_FREELIST_DEFAULT); 3335 } 3336 } 3337 } 3338 3339 /* 3340 * Steal memory for the message buffer (at end of core). 3341 */ 3342 { 3343 struct vm_physseg *vps; 3344 psize_t sz = round_page(MSGBUFSIZE); 3345 psize_t reqsz = sz; 3346 3347 for (x = 0; x < vm_nphysseg; x++) { 3348 vps = &vm_physmem[x]; 3349 if (ptoa(vps->avail_end) == avail_end) 3350 break; 3351 } 3352 if (x == vm_nphysseg) 3353 panic("init386: can't find end of memory"); 3354 3355 /* Shrink so it'll fit in the last segment. */ 3356 if ((vps->avail_end - vps->avail_start) < atop(sz)) 3357 sz = ptoa(vps->avail_end - vps->avail_start); 3358 3359 vps->avail_end -= atop(sz); 3360 vps->end -= atop(sz); 3361 msgbuf_paddr = ptoa(vps->avail_end); 3362 3363 /* Remove the last segment if it now has no pages. */ 3364 if (vps->start == vps->end) { 3365 for (vm_nphysseg--; x < vm_nphysseg; x++) 3366 vm_physmem[x] = vm_physmem[x + 1]; 3367 } 3368 3369 /* Now find where the new avail_end is. */ 3370 for (avail_end = 0, x = 0; x < vm_nphysseg; x++) 3371 if (vm_physmem[x].avail_end > avail_end) 3372 avail_end = vm_physmem[x].avail_end; 3373 avail_end = ptoa(avail_end); 3374 3375 /* Warn if the message buffer had to be shrunk. */ 3376 if (sz != reqsz) 3377 printf("WARNING: %ld bytes not available for msgbuf " 3378 "in last cluster (%ld used)\n", reqsz, sz); 3379 } 3380 3381 /* 3382 * install PT page for the first 4M if needed. 3383 */ 3384 if (needs_earlier_install_pte0) { 3385 paddr_t paddr; 3386 #ifdef DIAGNOSTIC 3387 if (realmode_reserved_size < PAGE_SIZE) { 3388 panic("cannot steal memory for first 4M PT page."); 3389 } 3390 #endif 3391 paddr=realmode_reserved_start+realmode_reserved_size-PAGE_SIZE; 3392 pmap_enter(pmap_kernel(), (vaddr_t)vtopte(0), paddr, 3393 VM_PROT_READ|VM_PROT_WRITE, 3394 PMAP_WIRED|VM_PROT_READ|VM_PROT_WRITE); 3395 pmap_update(pmap_kernel()); 3396 /* make sure it is clean before using */ 3397 memset(vtopte(0), 0, PAGE_SIZE); 3398 realmode_reserved_size -= PAGE_SIZE; 3399 } 3400 3401 #if NBIOSCALL > 0 3402 /* 3403 * this should be caught at kernel build time, but put it here 3404 * in case someone tries to fake it out... 3405 */ 3406 #ifdef DIAGNOSTIC 3407 if (realmode_reserved_start > BIOSTRAMP_BASE || 3408 (realmode_reserved_start+realmode_reserved_size) < (BIOSTRAMP_BASE+ 3409 PAGE_SIZE)) { 3410 panic("cannot steal memory for PT page of bioscall."); 3411 } 3412 if (biostramp_image_size > PAGE_SIZE) 3413 panic("biostramp_image_size too big: %x vs. %x", 3414 biostramp_image_size, PAGE_SIZE); 3415 #endif 3416 pmap_kenter_pa((vaddr_t)BIOSTRAMP_BASE, /* virtual */ 3417 (paddr_t)BIOSTRAMP_BASE, /* physical */ 3418 VM_PROT_ALL); /* protection */ 3419 pmap_update(pmap_kernel()); 3420 memcpy((caddr_t)BIOSTRAMP_BASE, biostramp_image, biostramp_image_size); 3421 #ifdef DEBUG_BIOSCALL 3422 printf("biostramp installed @ %x\n", BIOSTRAMP_BASE); 3423 #endif 3424 realmode_reserved_size -= PAGE_SIZE; 3425 realmode_reserved_start += PAGE_SIZE; 3426 #endif 3427 3428 #if NACPI > 0 3429 /* 3430 * Steal memory for the acpi wake code 3431 */ 3432 { 3433 paddr_t paddr, p; 3434 psize_t sz; 3435 int npg; 3436 3437 paddr = realmode_reserved_start; 3438 npg = acpi_md_get_npages_of_wakecode(); 3439 sz = ptoa(npg); 3440 #ifdef DIAGNOSTIC 3441 if (realmode_reserved_size < sz) { 3442 panic("cannot steal memory for ACPI wake code."); 3443 } 3444 #endif 3445 3446 /* identical mapping */ 3447 p = paddr; 3448 for (x=0; x<npg; x++) { 3449 printf("kenter: 0x%08X\n", (unsigned)p); 3450 pmap_kenter_pa((vaddr_t)p, p, VM_PROT_ALL); 3451 p += PAGE_SIZE; 3452 } 3453 pmap_update(pmap_kernel()); 3454 3455 acpi_md_install_wakecode(paddr); 3456 3457 realmode_reserved_size -= sz; 3458 realmode_reserved_start += sz; 3459 } 3460 #endif 3461 3462 pmap_enter(pmap_kernel(), idt_vaddr, idt_paddr, 3463 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED|VM_PROT_READ|VM_PROT_WRITE); 3464 pmap_update(pmap_kernel()); 3465 memset((void *)idt_vaddr, 0, PAGE_SIZE); 3466 3467 idt = (union descriptor *)idt_vaddr; 3468 #ifdef I586_CPU 3469 pmap_enter(pmap_kernel(), pentium_idt_vaddr, idt_paddr, 3470 VM_PROT_READ, PMAP_WIRED|VM_PROT_READ); 3471 pentium_idt = (union descriptor *)pentium_idt_vaddr; 3472 #endif 3473 pmap_update(pmap_kernel()); 3474 3475 tgdt = gdt; 3476 gdt = idt + NIDT; 3477 ldt = gdt + NGDT; 3478 3479 memcpy(gdt, tgdt, NGDT*sizeof(*gdt)); 3480 3481 setsegment(&gdt[GLDT_SEL].sd, ldt, NLDT * sizeof(ldt[0]) - 1, 3482 SDT_SYSLDT, SEL_KPL, 0, 0); 3483 3484 /* make ldt gates and memory segments */ 3485 setgate(&ldt[LSYS5CALLS_SEL].gd, &IDTVEC(osyscall), 1, 3486 SDT_SYS386CGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL)); 3487 3488 ldt[LUCODE_SEL] = gdt[GUCODE_SEL]; 3489 ldt[LUDATA_SEL] = gdt[GUDATA_SEL]; 3490 ldt[LSOL26CALLS_SEL] = ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL]; 3491 3492 /* exceptions */ 3493 for (x = 0; x < 32; x++) { 3494 setgate(&idt[x].gd, IDTVEC(exceptions)[x], 0, SDT_SYS386TGT, 3495 (x == 3 || x == 4) ? SEL_UPL : SEL_KPL, 3496 GSEL(GCODE_SEL, SEL_KPL)); 3497 idt_allocmap[x] = 1; 3498 } 3499 3500 /* new-style interrupt gate for syscalls */ 3501 setgate(&idt[128].gd, &IDTVEC(syscall), 0, SDT_SYS386TGT, SEL_UPL, 3502 GSEL(GCODE_SEL, SEL_KPL)); 3503 idt_allocmap[128] = 1; 3504 #ifdef COMPAT_SVR4 3505 setgate(&idt[0xd2].gd, &IDTVEC(svr4_fasttrap), 0, SDT_SYS386TGT, 3506 SEL_UPL, GSEL(GCODE_SEL, SEL_KPL)); 3507 idt_allocmap[0xd2] = 1; 3508 #endif /* COMPAT_SVR4 */ 3509 3510 setregion(®ion, gdt, NGDT * sizeof(gdt[0]) - 1); 3511 lgdt(®ion); 3512 3513 cpu_init_idt(); 3514 3515 #ifdef DDB 3516 { 3517 extern int end; 3518 extern int *esym; 3519 struct btinfo_symtab *symtab; 3520 3521 db_machine_init(); 3522 3523 symtab = lookup_bootinfo(BTINFO_SYMTAB); 3524 3525 if (symtab) { 3526 symtab->ssym += KERNBASE; 3527 symtab->esym += KERNBASE; 3528 ddb_init(symtab->nsym, (int *)symtab->ssym, 3529 (int *)symtab->esym); 3530 } 3531 else 3532 ddb_init(*(int *)&end, ((int *)&end) + 1, esym); 3533 } 3534 if (boothowto & RB_KDB) 3535 Debugger(); 3536 #endif 3537 #ifdef IPKDB 3538 ipkdb_init(); 3539 if (boothowto & RB_KDB) 3540 ipkdb_connect(0); 3541 #endif 3542 #ifdef KGDB 3543 kgdb_port_init(); 3544 if (boothowto & RB_KDB) { 3545 kgdb_debug_init = 1; 3546 kgdb_connect(1); 3547 } 3548 #endif 3549 3550 #if NMCA > 0 3551 /* check for MCA bus, needed to be done before ISA stuff - if 3552 * MCA is detected, ISA needs to use level triggered interrupts 3553 * by default */ 3554 mca_busprobe(); 3555 #endif 3556 3557 intr_default_setup(); 3558 3559 /* Initialize software interrupts. */ 3560 softintr_init(); 3561 3562 splraise(IPL_IPI); 3563 enable_intr(); 3564 3565 if (physmem < btoc(2 * 1024 * 1024)) { 3566 printf("warning: too little memory available; " 3567 "have %lu bytes, want %lu bytes\n" 3568 "running in degraded mode\n" 3569 "press a key to confirm\n\n", 3570 ptoa(physmem), 2*1024*1024UL); 3571 cngetc(); 3572 } 3573 } 3574 3575 #ifdef COMPAT_NOMID 3576 static int 3577 exec_nomid(p, epp) 3578 struct proc *p; 3579 struct exec_package *epp; 3580 { 3581 int error; 3582 u_long midmag, magic; 3583 u_short mid; 3584 struct exec *execp = epp->ep_hdr; 3585 3586 /* check on validity of epp->ep_hdr performed by exec_out_makecmds */ 3587 3588 midmag = ntohl(execp->a_midmag); 3589 mid = (midmag >> 16) & 0xffff; 3590 magic = midmag & 0xffff; 3591 3592 if (magic == 0) { 3593 magic = (execp->a_midmag & 0xffff); 3594 mid = MID_ZERO; 3595 } 3596 3597 midmag = mid << 16 | magic; 3598 3599 switch (midmag) { 3600 case (MID_ZERO << 16) | ZMAGIC: 3601 /* 3602 * 386BSD's ZMAGIC format: 3603 */ 3604 error = exec_aout_prep_oldzmagic(p, epp); 3605 break; 3606 3607 case (MID_ZERO << 16) | QMAGIC: 3608 /* 3609 * BSDI's QMAGIC format: 3610 * same as new ZMAGIC format, but with different magic number 3611 */ 3612 error = exec_aout_prep_zmagic(p, epp); 3613 break; 3614 3615 case (MID_ZERO << 16) | NMAGIC: 3616 /* 3617 * BSDI's NMAGIC format: 3618 * same as NMAGIC format, but with different magic number 3619 * and with text starting at 0. 3620 */ 3621 error = exec_aout_prep_oldnmagic(p, epp); 3622 break; 3623 3624 case (MID_ZERO << 16) | OMAGIC: 3625 /* 3626 * BSDI's OMAGIC format: 3627 * same as OMAGIC format, but with different magic number 3628 * and with text starting at 0. 3629 */ 3630 error = exec_aout_prep_oldomagic(p, epp); 3631 break; 3632 3633 default: 3634 error = ENOEXEC; 3635 } 3636 3637 return error; 3638 } 3639 #endif 3640 3641 /* 3642 * cpu_exec_aout_makecmds(): 3643 * cpu-dependent a.out format hook for execve(). 3644 * 3645 * Determine of the given exec package refers to something which we 3646 * understand and, if so, set up the vmcmds for it. 3647 * 3648 * On the i386, old (386bsd) ZMAGIC binaries and BSDI QMAGIC binaries 3649 * if COMPAT_NOMID is given as a kernel option. 3650 */ 3651 int 3652 cpu_exec_aout_makecmds(p, epp) 3653 struct proc *p; 3654 struct exec_package *epp; 3655 { 3656 int error = ENOEXEC; 3657 3658 #ifdef COMPAT_NOMID 3659 if ((error = exec_nomid(p, epp)) == 0) 3660 return error; 3661 #endif /* ! COMPAT_NOMID */ 3662 3663 return error; 3664 } 3665 3666 void * 3667 lookup_bootinfo(type) 3668 int type; 3669 { 3670 struct btinfo_common *help; 3671 int n = *(int*)bootinfo; 3672 help = (struct btinfo_common *)(bootinfo + sizeof(int)); 3673 while(n--) { 3674 if(help->type == type) 3675 return(help); 3676 help = (struct btinfo_common *)((char*)help + help->len); 3677 } 3678 return(0); 3679 } 3680 3681 #include <dev/ic/mc146818reg.h> /* for NVRAM POST */ 3682 #include <i386/isa/nvram.h> /* for NVRAM POST */ 3683 3684 void 3685 cpu_reset() 3686 { 3687 3688 disable_intr(); 3689 3690 /* 3691 * Ensure the NVRAM reset byte contains something vaguely sane. 3692 */ 3693 3694 outb(IO_RTC, NVRAM_RESET); 3695 outb(IO_RTC+1, NVRAM_RESET_RST); 3696 3697 /* 3698 * The keyboard controller has 4 random output pins, one of which is 3699 * connected to the RESET pin on the CPU in many PCs. We tell the 3700 * keyboard controller to pulse this line a couple of times. 3701 */ 3702 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3703 delay(100000); 3704 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3705 delay(100000); 3706 3707 /* 3708 * Try to cause a triple fault and watchdog reset by making the IDT 3709 * invalid and causing a fault. 3710 */ 3711 memset((caddr_t)idt, 0, NIDT * sizeof(idt[0])); 3712 __asm __volatile("divl %0,%1" : : "q" (0), "a" (0)); 3713 3714 #if 0 3715 /* 3716 * Try to cause a triple fault and watchdog reset by unmapping the 3717 * entire address space and doing a TLB flush. 3718 */ 3719 memset((caddr_t)PTD, 0, PAGE_SIZE); 3720 tlbflush(); 3721 #endif 3722 3723 for (;;); 3724 } 3725 3726 void 3727 cpu_initclocks() 3728 { 3729 (*initclock_func)(); 3730 } 3731 3732 #ifdef MULTIPROCESSOR 3733 void 3734 need_resched(struct cpu_info *ci) 3735 { 3736 ci->ci_want_resched = 1; 3737 aston(ci); 3738 } 3739 #endif 3740 3741 /* 3742 * Allocate an IDT vector slot within the given range. 3743 * XXX needs locking to avoid MP allocation races. 3744 */ 3745 3746 int 3747 idt_vec_alloc(low, high) 3748 int low; 3749 int high; 3750 { 3751 int vec; 3752 3753 simple_lock(&idt_lock); 3754 for (vec = low; vec <= high; vec++) { 3755 if (idt_allocmap[vec] == 0) { 3756 idt_allocmap[vec] = 1; 3757 simple_unlock(&idt_lock); 3758 return vec; 3759 } 3760 } 3761 simple_unlock(&idt_lock); 3762 return 0; 3763 } 3764 3765 void 3766 idt_vec_set(vec, function) 3767 int vec; 3768 void (*function) __P((void)); 3769 { 3770 /* 3771 * Vector should be allocated, so no locking needed. 3772 */ 3773 KASSERT(idt_allocmap[vec] == 1); 3774 setgate(&idt[vec].gd, function, 0, SDT_SYS386IGT, SEL_KPL, 3775 GSEL(GCODE_SEL, SEL_KPL)); 3776 } 3777 3778 void 3779 idt_vec_free(vec) 3780 int vec; 3781 { 3782 simple_lock(&idt_lock); 3783 unsetgate(&idt[vec].gd); 3784 idt_allocmap[vec] = 0; 3785 simple_unlock(&idt_lock); 3786 } 3787