1 /* $NetBSD: cpufunc.h,v 1.22 2002/10/01 12:57:04 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _I386_CPUFUNC_H_ 40 #define _I386_CPUFUNC_H_ 41 42 /* 43 * Functions to provide access to i386-specific instructions. 44 */ 45 46 #include <sys/cdefs.h> 47 #include <sys/types.h> 48 49 #include <machine/specialreg.h> 50 51 #ifdef _KERNEL 52 53 static __inline void 54 invlpg(u_int addr) 55 { 56 __asm __volatile("invlpg (%0)" : : "r" (addr) : "memory"); 57 } 58 59 static __inline void 60 lidt(void *p) 61 { 62 __asm __volatile("lidt (%0)" : : "r" (p)); 63 } 64 65 static __inline void 66 lldt(u_short sel) 67 { 68 __asm __volatile("lldt %0" : : "r" (sel)); 69 } 70 71 static __inline void 72 ltr(u_short sel) 73 { 74 __asm __volatile("ltr %0" : : "r" (sel)); 75 } 76 77 static __inline void 78 lcr0(u_int val) 79 { 80 __asm __volatile("movl %0,%%cr0" : : "r" (val)); 81 } 82 83 static __inline u_int 84 rcr0(void) 85 { 86 u_int val; 87 __asm __volatile("movl %%cr0,%0" : "=r" (val)); 88 return val; 89 } 90 91 static __inline u_int 92 rcr2(void) 93 { 94 u_int val; 95 __asm __volatile("movl %%cr2,%0" : "=r" (val)); 96 return val; 97 } 98 99 static __inline void 100 lcr3(u_int val) 101 { 102 __asm __volatile("movl %0,%%cr3" : : "r" (val)); 103 } 104 105 static __inline u_int 106 rcr3(void) 107 { 108 u_int val; 109 __asm __volatile("movl %%cr3,%0" : "=r" (val)); 110 return val; 111 } 112 113 static __inline void 114 lcr4(u_int val) 115 { 116 __asm __volatile("movl %0,%%cr4" : : "r" (val)); 117 } 118 119 static __inline u_int 120 rcr4(void) 121 { 122 u_int val; 123 __asm __volatile("movl %%cr4,%0" : "=r" (val)); 124 return val; 125 } 126 127 static __inline void 128 tlbflush(void) 129 { 130 u_int val; 131 val = rcr3(); 132 lcr3(val); 133 } 134 135 static __inline void 136 tlbflushg(void) 137 { 138 /* 139 * Big hammer: flush all TLB entries, including ones from PTE's 140 * with the G bit set. This should only be necessary if TLB 141 * shootdown falls far behind. 142 * 143 * Intel Architecture Software Developer's Manual, Volume 3, 144 * System Programming, section 9.10, "Invalidating the 145 * Translation Lookaside Buffers (TLBS)": 146 * "The following operations invalidate all TLB entries, irrespective 147 * of the setting of the G flag: 148 * ... 149 * "(P6 family processors only): Writing to control register CR4 to 150 * modify the PSE, PGE, or PAE flag." 151 * 152 * (the alternatives not quoted above are not an option here.) 153 * 154 * If PGE is not in use, we reload CR3 for the benefit of 155 * pre-P6-family processors. 156 */ 157 158 #if defined(I686_CPU) 159 if (cpu_feature & CPUID_PGE) { 160 u_int cr4 = rcr4(); 161 lcr4(cr4 & ~CR4_PGE); 162 lcr4(cr4); 163 } else 164 #endif 165 tlbflush(); 166 } 167 168 169 #ifdef notyet 170 void setidt __P((int idx, /*XXX*/caddr_t func, int typ, int dpl)); 171 #endif 172 173 /* debug register */ 174 void dr0(caddr_t, u_int32_t, u_int32_t, u_int32_t); 175 176 static __inline u_int 177 rdr6(void) 178 { 179 u_int val; 180 181 __asm __volatile("movl %%dr6,%0" : "=r" (val)); 182 return val; 183 } 184 185 static __inline void 186 ldr6(u_int val) 187 { 188 189 __asm __volatile("movl %0,%%dr6" : : "r" (val)); 190 } 191 192 /* XXXX ought to be in psl.h with spl() functions */ 193 194 static __inline void 195 disable_intr(void) 196 { 197 __asm __volatile("cli"); 198 } 199 200 static __inline void 201 enable_intr(void) 202 { 203 __asm __volatile("sti"); 204 } 205 206 static __inline u_long 207 read_eflags(void) 208 { 209 u_long ef; 210 211 __asm __volatile("pushfl; popl %0" : "=r" (ef)); 212 return (ef); 213 } 214 215 static __inline void 216 write_eflags(u_long ef) 217 { 218 __asm __volatile("pushl %0; popfl" : : "r" (ef)); 219 } 220 221 static __inline u_int64_t 222 rdmsr(u_int msr) 223 { 224 u_int64_t rv; 225 226 __asm __volatile("rdmsr" : "=A" (rv) : "c" (msr)); 227 return (rv); 228 } 229 230 static __inline void 231 wrmsr(u_int msr, u_int64_t newval) 232 { 233 __asm __volatile("wrmsr" : : "A" (newval), "c" (msr)); 234 } 235 236 static __inline void 237 wbinvd(void) 238 { 239 __asm __volatile("wbinvd"); 240 } 241 242 static __inline u_int64_t 243 rdtsc(void) 244 { 245 u_int64_t rv; 246 247 __asm __volatile("rdtsc" : "=A" (rv)); 248 return (rv); 249 } 250 251 static __inline u_int64_t 252 rdpmc(u_int pmc) 253 { 254 u_int64_t rv; 255 256 __asm __volatile("rdpmc" : "=A" (rv) : "c" (pmc)); 257 return (rv); 258 } 259 260 /* Break into DDB/KGDB. */ 261 static __inline void 262 breakpoint(void) 263 { 264 __asm __volatile("int $3"); 265 } 266 267 /* 268 * XXX Maybe these don't belong here... 269 */ 270 271 extern int (*copyout_func)(const void *, void *, size_t); 272 extern int (*copyin_func)(const void *, void *, size_t); 273 274 int i386_copyout(const void *, void *, size_t); 275 int i486_copyout(const void *, void *, size_t); 276 277 int i386_copyin(const void *, void *, size_t); 278 279 #endif /* _KERNEL */ 280 281 #endif /* !_I386_CPUFUNC_H_ */ 282