xref: /netbsd/sys/arch/i386/include/intr.h (revision bf9ec67e)
1 /*	$NetBSD: intr.h,v 1.25 2002/05/12 23:16:52 matt Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Charles M. Hannum, and by Jason R. Thorpe.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #ifndef _I386_INTR_H_
40 #define _I386_INTR_H_
41 
42 /* Interrupt priority `levels'. */
43 #define	IPL_NONE	9	/* nothing */
44 #define	IPL_SOFTCLOCK	8	/* timeouts */
45 #define	IPL_SOFTNET	7	/* protocol stacks */
46 #define	IPL_BIO		6	/* block I/O */
47 #define	IPL_NET		5	/* network */
48 #define	IPL_SOFTSERIAL	4	/* serial */
49 #define	IPL_TTY		3	/* terminal */
50 #define	IPL_IMP		3	/* memory allocation */
51 #define	IPL_AUDIO	2	/* audio */
52 #define	IPL_CLOCK	1	/* clock */
53 #define	IPL_HIGH	1	/* everything */
54 #define	IPL_SERIAL	0	/* serial */
55 #define	NIPL		10
56 
57 /* Interrupt sharing types. */
58 #define	IST_NONE	0	/* none */
59 #define	IST_PULSE	1	/* pulsed */
60 #define	IST_EDGE	2	/* edge-triggered */
61 #define	IST_LEVEL	3	/* level-triggered */
62 
63 /* Soft interrupt masks. */
64 #define	SIR_CLOCK	31
65 #define	SIR_NET		30
66 #define	SIR_SERIAL	29
67 
68 /* Hack for CLKF_INTR(). */
69 #define	IPL_TAGINTR	28
70 
71 #ifndef _LOCORE
72 
73 extern volatile int cpl, ipending, astpending;
74 extern int imask[NIPL];
75 
76 void Xspllower __P((void));
77 
78 static __inline int splraise __P((int));
79 static __inline void spllower __P((int));
80 static __inline void softintr __P((int));
81 
82 /*
83  * compiler barrier: prevent reordering of instructions.
84  * XXX something similar will move to <sys/cdefs.h>
85  * or thereabouts.
86  * This prevents the compiler from reordering code around
87  * this "instruction", acting as a sequence point for code generation.
88  */
89 
90 #define	__splbarrier() __asm __volatile("":::"memory")
91 
92 /*
93  * Add a mask to cpl, and return the old value of cpl.
94  */
95 static __inline int
96 splraise(ncpl)
97 	register int ncpl;
98 {
99 	register int ocpl = cpl;
100 
101 	cpl = ocpl | ncpl;
102 	__splbarrier();
103 	return (ocpl);
104 }
105 
106 /*
107  * Restore a value to cpl (unmasking interrupts).  If any unmasked
108  * interrupts are pending, call Xspllower() to process them.
109  */
110 static __inline void
111 spllower(ncpl)
112 	register int ncpl;
113 {
114 
115 	__splbarrier();
116 	cpl = ncpl;
117 	if (ipending & ~ncpl)
118 		Xspllower();
119 }
120 
121 /*
122  * Hardware interrupt masks
123  */
124 #define	splbio()	splraise(imask[IPL_BIO])
125 #define	splnet()	splraise(imask[IPL_NET])
126 #define	spltty()	splraise(imask[IPL_TTY])
127 #define	splaudio()	splraise(imask[IPL_AUDIO])
128 #define	splclock()	splraise(imask[IPL_CLOCK])
129 #define	splstatclock()	splclock()
130 #define	splserial()	splraise(imask[IPL_SERIAL])
131 
132 #define	spllpt()	spltty()
133 
134 /*
135  * Software interrupt masks
136  *
137  * NOTE: splsoftclock() is used by hardclock() to lower the priority from
138  * clock to softclock before it calls softclock().
139  */
140 #define	spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
141 #define	splsoftclock()	splraise(imask[IPL_SOFTCLOCK])
142 #define	splsoftnet()	splraise(imask[IPL_SOFTNET])
143 #define	splsoftserial()	splraise(imask[IPL_SOFTSERIAL])
144 
145 /*
146  * Miscellaneous
147  */
148 #define	splvm()		splraise(imask[IPL_IMP])
149 #define	splhigh()	splraise(imask[IPL_HIGH])
150 #define	splsched()	splhigh()
151 #define	spllock()	splhigh()
152 #define	spl0()		spllower(0)
153 #define	splx(x)		spllower(x)
154 
155 /*
156  * Software interrupt registration
157  *
158  * We hand-code this to ensure that it's atomic.
159  */
160 static __inline void
161 softintr(mask)
162 	register int mask;
163 {
164 	__asm __volatile("orl %1, %0" : "=m"(ipending) : "ir" (1 << mask));
165 }
166 
167 #define	setsoftast()	(astpending = 1)
168 #define	setsoftnet()	softintr(SIR_NET)
169 
170 #endif /* !_LOCORE */
171 
172 /*
173  * Generic software interrupt support.
174  */
175 
176 #define	I386_SOFTINTR_SOFTCLOCK		0
177 #define	I386_SOFTINTR_SOFTNET		1
178 #define	I386_SOFTINTR_SOFTSERIAL	2
179 #define	I386_NSOFTINTR			3
180 
181 #ifndef _LOCORE
182 #include <sys/queue.h>
183 
184 struct i386_soft_intrhand {
185 	TAILQ_ENTRY(i386_soft_intrhand)
186 		sih_q;
187 	struct i386_soft_intr *sih_intrhead;
188 	void	(*sih_fn)(void *);
189 	void	*sih_arg;
190 	int	sih_pending;
191 };
192 
193 struct i386_soft_intr {
194 	TAILQ_HEAD(, i386_soft_intrhand)
195 		softintr_q;
196 	int softintr_ssir;
197 };
198 
199 #define	i386_softintr_lock(si, s)					\
200 do {									\
201 	/* XXX splhigh braindamage on i386 */				\
202 	(s) = splserial();						\
203 } while (/*CONSTCOND*/ 0)
204 
205 #define	i386_softintr_unlock(si, s)					\
206 do {									\
207 	splx((s));							\
208 } while (/*CONSTCOND*/ 0)
209 
210 void	*softintr_establish(int, void (*)(void *), void *);
211 void	softintr_disestablish(void *);
212 void	softintr_init(void);
213 void	softintr_dispatch(int);
214 
215 #define	softintr_schedule(arg)						\
216 do {									\
217 	struct i386_soft_intrhand *__sih = (arg);			\
218 	struct i386_soft_intr *__si = __sih->sih_intrhead;		\
219 	int __s;							\
220 									\
221 	i386_softintr_lock(__si, __s);					\
222 	if (__sih->sih_pending == 0) {					\
223 		TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q);	\
224 		__sih->sih_pending = 1;					\
225 		softintr(__si->softintr_ssir);				\
226 	}								\
227 	i386_softintr_unlock(__si, __s);				\
228 } while (/*CONSTCOND*/ 0)
229 #endif /* _LOCORE */
230 
231 #endif /* !_I386_INTR_H_ */
232