1 /* $NetBSD: intr.h,v 1.34 2002/12/01 00:15:37 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _I386_INTR_H_ 40 #define _I386_INTR_H_ 41 42 #include <machine/intrdefs.h> 43 44 #ifndef _LOCORE 45 #include <machine/cpu.h> 46 #include <machine/pic.h> 47 48 /* 49 * Struct describing an interrupt source for a CPU. struct cpu_info 50 * has an array of MAX_INTR_SOURCES of these. The index in the array 51 * is equal to the stub number of the stubcode as present in vector.s 52 * 53 * The primary CPU's array of interrupt sources has its first 16 54 * entries reserved for legacy ISA irq handlers. This means that 55 * they have a 1:1 mapping for arrayindex:irq_num. This is not 56 * true for interrupts that come in through IO APICs, to find 57 * their source, go through ci->ci_isources[index].is_pic 58 * 59 * It's possible to always maintain a 1:1 mapping, but that means 60 * limiting the total number of interrupt sources to MAX_INTR_SOURCES 61 * (32), instead of 32 per CPU. It also would mean that having multiple 62 * IO APICs which deliver interrupts from an equal pin number would 63 * overlap if they were to be sent to the same CPU. 64 */ 65 66 struct intrstub { 67 void *ist_entry; 68 void *ist_recurse; 69 void *ist_resume; 70 }; 71 72 struct intrsource { 73 int is_maxlevel; /* max. IPL for this source */ 74 int is_pin; /* IRQ for legacy; pin for IO APIC */ 75 struct intrhand *is_handlers; /* handler chain */ 76 struct pic *is_pic; /* originating PIC */ 77 void *is_recurse; /* entry for spllower */ 78 void *is_resume; /* entry for doreti */ 79 struct evcnt is_evcnt; /* interrupt counter */ 80 char is_evname[32]; /* event counter name */ 81 int is_flags; /* see below */ 82 int is_type; /* level, edge */ 83 int is_idtvec; 84 int is_minlevel; 85 }; 86 87 #define IS_LEGACY 0x0001 /* legacy ISA irq source */ 88 #define IS_IPI 0x0002 89 #define IS_LOG 0x0004 90 91 92 /* 93 * Interrupt handler chains. *_intr_establish() insert a handler into 94 * the list. The handler is called with its (single) argument. 95 */ 96 97 struct intrhand { 98 int (*ih_fun)(void *); 99 void *ih_arg; 100 int ih_level; 101 struct intrhand *ih_next; 102 int ih_pin; 103 int ih_slot; 104 struct cpu_info *ih_cpu; 105 }; 106 107 #define IMASK(ci,level) (ci)->ci_imask[(level)] 108 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] 109 110 extern void Xspllower __P((void)); 111 112 static __inline int splraise __P((int)); 113 static __inline void spllower __P((int)); 114 static __inline void softintr __P((int)); 115 116 /* 117 * Convert spl level to local APIC level 118 */ 119 #define APIC_LEVEL(l) ((l) << 4) 120 121 /* 122 * compiler barrier: prevent reordering of instructions. 123 * XXX something similar will move to <sys/cdefs.h> 124 * or thereabouts. 125 * This prevents the compiler from reordering code around 126 * this "instruction", acting as a sequence point for code generation. 127 */ 128 129 #define __splbarrier() __asm __volatile("":::"memory") 130 131 /* 132 * Add a mask to cpl, and return the old value of cpl. 133 */ 134 static __inline int 135 splraise(int nlevel) 136 { 137 int olevel; 138 struct cpu_info *ci = curcpu(); 139 140 olevel = ci->ci_ilevel; 141 if (nlevel > olevel) 142 ci->ci_ilevel = nlevel; 143 __splbarrier(); 144 return (olevel); 145 } 146 147 void cpu_Debugger(void); 148 void printf(const char *, ...) 149 __attribute__((__format__(__printf__,1,2))); 150 151 /* 152 * Restore a value to cpl (unmasking interrupts). If any unmasked 153 * interrupts are pending, call Xspllower() to process them. 154 */ 155 static __inline void 156 spllower(int nlevel) 157 { 158 struct cpu_info *ci = curcpu(); 159 160 __splbarrier(); 161 ci->ci_ilevel = nlevel; 162 /* 163 * Since this should only lower the interrupt level, 164 * the XOR below should only show interrupts that 165 * are being unmasked. 166 */ 167 if (ci->ci_ipending & IUNMASK(ci,nlevel)) 168 Xspllower(); 169 } 170 171 /* 172 * Hardware interrupt masks 173 */ 174 #define splbio() splraise(IPL_BIO) 175 #define splnet() splraise(IPL_NET) 176 #define spltty() splraise(IPL_TTY) 177 #define splaudio() splraise(IPL_AUDIO) 178 #define splclock() splraise(IPL_CLOCK) 179 #define splstatclock() splclock() 180 #define splserial() splraise(IPL_SERIAL) 181 #define splipi() splraise(IPL_IPI) 182 183 #define spllpt() spltty() 184 185 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) 186 #define spllpt() spltty() 187 188 /* 189 * Software interrupt masks 190 * 191 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 192 * clock to softclock before it calls softclock(). 193 */ 194 #define spllowersoftclock() spllower(IPL_SOFTCLOCK) 195 196 #define splsoftclock() splraise(IPL_SOFTCLOCK) 197 #define splsoftnet() splraise(IPL_SOFTNET) 198 #define splsoftserial() splraise(IPL_SOFTSERIAL) 199 200 /* 201 * Miscellaneous 202 */ 203 #define splvm() splraise(IPL_IMP) 204 #define splhigh() splraise(IPL_HIGH) 205 #define spl0() spllower(IPL_NONE) 206 #define splsched() splraise(IPL_SCHED) 207 #define spllock() splhigh() 208 #define splx(x) spllower(x) 209 210 /* 211 * Software interrupt registration 212 * 213 * We hand-code this to ensure that it's atomic. 214 * 215 * XXX always scheduled on the current CPU. 216 */ 217 static __inline void 218 softintr(int sir) 219 { 220 struct cpu_info *ci = curcpu(); 221 222 __asm __volatile("lock ; orl %1, %0" : 223 "=m"(ci->ci_ipending) : "ir" (1 << sir)); 224 } 225 226 /* 227 * XXX 228 */ 229 #define setsoftnet() softintr(SIR_NET) 230 231 /* 232 * Stub declarations. 233 */ 234 235 extern void Xsoftclock(void); 236 extern void Xsoftnet(void); 237 extern void Xsoftserial(void); 238 239 extern struct intrstub i8259_stubs[]; 240 extern struct intrstub ioapic_stubs[]; 241 242 struct cpu_info; 243 244 extern char idt_allocmap[]; 245 246 void intr_default_setup(void); 247 int i386_nmi(void); 248 void intr_calculatemasks(struct cpu_info *); 249 int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *); 250 int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *, 251 int *); 252 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *); 253 void intr_disestablish(struct intrhand *); 254 void cpu_intr_init(struct cpu_info *); 255 int intr_find_mpmapping(int bus, int pin, int *handle); 256 #ifdef INTRDEBUG 257 void intr_printconfig(void); 258 #endif 259 260 #ifdef MULTIPROCESSOR 261 int i386_send_ipi(struct cpu_info *, int); 262 void i386_broadcast_ipi(int); 263 void i386_multicast_ipi(int, int); 264 void i386_ipi_handler(void); 265 void i386_intlock(struct intrframe); 266 void i386_intunlock(struct intrframe); 267 void i386_softintlock(void); 268 void i386_softintunlock(void); 269 #endif 270 271 #endif /* !_LOCORE */ 272 273 /* 274 * Generic software interrupt support. 275 */ 276 277 #define I386_SOFTINTR_SOFTCLOCK 0 278 #define I386_SOFTINTR_SOFTNET 1 279 #define I386_SOFTINTR_SOFTSERIAL 2 280 #define I386_NSOFTINTR 3 281 282 #ifndef _LOCORE 283 #include <sys/queue.h> 284 285 struct i386_soft_intrhand { 286 TAILQ_ENTRY(i386_soft_intrhand) 287 sih_q; 288 struct i386_soft_intr *sih_intrhead; 289 void (*sih_fn)(void *); 290 void *sih_arg; 291 int sih_pending; 292 }; 293 294 struct i386_soft_intr { 295 TAILQ_HEAD(, i386_soft_intrhand) 296 softintr_q; 297 int softintr_ssir; 298 struct simplelock softintr_slock; 299 }; 300 301 #define i386_softintr_lock(si, s) \ 302 do { \ 303 (s) = splhigh(); \ 304 simple_lock(&si->softintr_slock); \ 305 } while (/*CONSTCOND*/ 0) 306 307 #define i386_softintr_unlock(si, s) \ 308 do { \ 309 simple_unlock(&si->softintr_slock); \ 310 splx((s)); \ 311 } while (/*CONSTCOND*/ 0) 312 313 void *softintr_establish(int, void (*)(void *), void *); 314 void softintr_disestablish(void *); 315 void softintr_init(void); 316 void softintr_dispatch(int); 317 318 #define softintr_schedule(arg) \ 319 do { \ 320 struct i386_soft_intrhand *__sih = (arg); \ 321 struct i386_soft_intr *__si = __sih->sih_intrhead; \ 322 int __s; \ 323 \ 324 i386_softintr_lock(__si, __s); \ 325 if (__sih->sih_pending == 0) { \ 326 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 327 __sih->sih_pending = 1; \ 328 softintr(__si->softintr_ssir); \ 329 } \ 330 i386_softintr_unlock(__si, __s); \ 331 } while (/*CONSTCOND*/ 0) 332 #endif /* _LOCORE */ 333 334 #endif /* !_I386_INTR_H_ */ 335