1 /* $NetBSD: elan520reg.h,v 1.1 2002/08/12 01:03:14 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Register definitions for the AMD Elan SC520 System Controller. 41 */ 42 43 #ifndef _I386_PCI_ELAN520REG_H_ 44 #define _I386_PCI_ELAN520REG_H_ 45 46 #define MMCR_BASE_ADDR 0xfffef000 47 48 /* 49 * Am5x86 CPU Registers. 50 */ 51 #define MMCR_REVID 0x0000 52 #define MMCR_CPUCTL 0x0002 53 54 #define REVID_PRODID 0xff00 /* product ID */ 55 #define REVID_PRODID_SHIFT 8 56 #define REVID_MAJSTEP 0x00f0 /* stepping major */ 57 #define REVID_MAJSTEP_SHIFT 4 58 #define REVID_MINSTEP 0x000f /* stepping minor */ 59 60 #define PRODID_ELAN_SC520 0x00 /* Elan SC520 */ 61 62 #define CPUCTL_CPU_CLK_SPD_MASK 0x03 /* CPU clock speed */ 63 #define CPUCTL_CACHE_WR_MODE 0x10 /* cache mode (0 = wb, 1 = wt) */ 64 65 /* 66 * General Purpose Bus Registers 67 */ 68 #define MMCR_GPECHO 0x0c00 /* GP echo mode */ 69 #define MMCR_GPCSDW 0x0c01 /* GP chip sel data width */ 70 #define MMCR_CPCSQUAL 0x0c02 /* GP chip sel qualification */ 71 #define MMCR_GPCSRT 0x0c08 /* GP chip sel recovery time */ 72 #define MMCR_GPCSPW 0x0c09 /* GP chip sel pulse width */ 73 #define MMCR_GPCSOFF 0x0c0a /* GP chip sel offset */ 74 #define MMCR_GPRDW 0x0c0b /* GP read pulse width */ 75 #define MMCR_GPRDOFF 0x0c0c /* GP read offset */ 76 #define MMCR_GPWRW 0x0c0d /* GP write pulse width */ 77 #define MMCR_GPWROFF 0x0c0e /* GP write offset */ 78 #define MMCR_GPALEW 0x0c0f /* GPALE pulse width */ 79 #define MMCR_GPALEOFF 0x0c10 /* GPALE offset */ 80 81 #define GPECHO_GP_ECHO_ENB 0x01 /* GP bus echo mode enable */ 82 83 /* 84 * Programmable Input/Output Registers 85 */ 86 #define MMCR_PIOPFS15_0 0x0c20 /* PIO15-PIO0 pin func sel */ 87 #define MMCR_PIOPFS31_16 0x0c22 /* PIO31-PIO16 pin func sel */ 88 #define MMCR_CSPFS 0x0c24 /* chip sel pin func sel */ 89 #define MMCR_CLKSEL 0x0c26 /* clock select */ 90 #define MMCR_DSCTL 0x0c28 /* drive strength control */ 91 #define MMCR_PIODIR15_0 0x0c2a /* PIO15-PIO0 direction */ 92 #define MMCR_PIODIR31_16 0x0c2c /* PIO31-PIO16 direction */ 93 #define MMCR_PIODATA15_0 0x0c30 /* PIO15-PIO0 data */ 94 #define MMCR_PIODATA31_16 0x0c32 /* PIO31-PIO16 data */ 95 #define MMCR_PIOSET15_0 0x0c34 /* PIO15-PIO0 set */ 96 #define MMCR_PIOSET31_16 0x0c36 /* PIO31-PIO16 set */ 97 #define MMCR_PIOCLR15_0 0x0c38 /* PIO15-PIO0 clear */ 98 #define MMCR_PIOCLR31_16 0x0c3a /* PIO31-PIO16 clear */ 99 100 /* 101 * Watchdog Timer Registers. 102 */ 103 #define MMCR_WDTMRCTL 0x0cb0 /* watchdog timer control */ 104 #define MMCR_WDTMRCNTL 0x0cb2 /* watchdog timer count low */ 105 #define MMCR_WDTMRCNTH 0x0cb4 /* watchdog timer count high */ 106 107 #define WDTMRCTL_EXP_SEL_MASK 0x00ff /* exponent select */ 108 #define WDTMRCTL_EXP_SEL14 0x0001 /* 496us/492us */ 109 #define WDTMRCTL_EXP_SEL24 0x0002 /* 508ms/503ms */ 110 #define WDTMRCTL_EXP_SEL25 0x0004 /* 1.02s/1.01s */ 111 #define WDTMRCTL_EXP_SEL26 0x0008 /* 2.03s/2.01s */ 112 #define WDTMRCTL_EXP_SEL27 0x0010 /* 4.07s/4.03s */ 113 #define WDTMRCTL_EXP_SEL28 0x0020 /* 8.13s/8.05s */ 114 #define WDTMRCTL_EXP_SEL29 0x0040 /* 16.27s/16.11s */ 115 #define WDTMRCTL_EXP_SEL30 0x0080 /* 32.54s/32.21s */ 116 #define WDTMRCTL_IRQ_FLG 0x1000 /* interrupt request */ 117 #define WDTMRCTL_WRST_ENB 0x4000 /* watchdog timer reset enable */ 118 #define WDTMRCTL_ENB 0x8000 /* watchdog timer enable */ 119 120 #define WDTMRCTL_UNLOCK1 0x3333 121 #define WDTMRCTL_UNLOCK2 0xcccc 122 123 #define WDTMRCTL_RESET1 0xaaaa 124 #define WDTMRCTL_RESET2 0x5555 125 126 /* 127 * Reset Generation Registers. 128 */ 129 #define MMCR_SYSINFO 0x0d70 /* system board information */ 130 #define MMCR_RESCFG 0x0d72 /* reset configuration */ 131 #define MMCR_RESSTA 0x0d74 /* reset status */ 132 133 #define RESCFG_SYS_RST 0x01 /* software system reset */ 134 #define RESCFG_GP_RST 0x02 /* assert GP bus reset */ 135 #define RESCFG_PRG_RST_ENB 0x04 /* programmable reset enable */ 136 #define RESCFG_ICE_ON_RST 0x08 /* enter AMDebug(tm) on reset */ 137 138 #define RESSTA_PWRGOOD_DET 0x01 /* POWERGOOD reset detect */ 139 #define RESSTA_PRGRST_DET 0x02 /* programmable reset detect */ 140 #define RESSTA_SD_RST_DET 0x04 /* CPU shutdown reset detect */ 141 #define RESSTA_WDT_RST_DET 0x08 /* watchdog timer reset detect */ 142 #define RESSTA_ICE_SRST_DET 0x10 /* AMDebug(tm) soft reset detect */ 143 #define RESSTA_ICE_HRST_DET 0x20 /* AMDebug(tm) soft reset detect */ 144 #define RESSTA_SCP_RST 0x40 /* SCP reset detect */ 145 146 #endif /* _I386_PCI_ELAN520REG_H_ */ 147