1 /* $NetBSD: opti82c558reg.h,v 1.1 1999/11/17 01:21:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Register definitions for the Opti 82c558 PCI-ISA bridge interrupt 30 * controller. 31 */ 32 33 /* 34 * PCI IRQ Select Register 35 */ 36 37 #define VIPER_CFG_PIRQ 0x40 /* PCI configuration space */ 38 39 /* 40 * Trigger setting: 41 * 42 * [1:7]=>5,9,10,11,12,14,15 Edge = 0 Level = 1 43 */ 44 #define VIPER_CFG_TRIGGER_SHIFT 16 45 46 #define VIPER_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3) 47 48 #define VIPER_PIRQ_MASK 0xde20 49 #define VIPER_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ 50 ((1 << (irq)) & VIPER_PIRQ_MASK) != 0) 51 52 #define VIPER_PIRQ_NONE 0 53 #define VIPER_PIRQ_5 1 54 #define VIPER_PIRQ_9 2 55 #define VIPER_PIRQ_10 3 56 #define VIPER_PIRQ_11 4 57 #define VIPER_PIRQ_12 5 58 #define VIPER_PIRQ_14 6 59 #define VIPER_PIRQ_15 7 60 61 #define VIPER_PIRQ_SELECT_MASK 0x07 62 #define VIPER_PIRQ_SELECT_SHIFT 3 63 64 #define VIPER_PIRQ(reg, x) (((reg) >> ((x) * VIPER_PIRQ_SELECT_SHIFT)) \ 65 & VIPER_PIRQ_SELECT_MASK) 66