1 /* $NetBSD: piixpcib.c,v 1.19 2010/07/26 22:33:23 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto, Matthew R. Green, and Jared D. McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel PIIX4 PCI-ISA bridge device driver with CPU frequency scaling support 34 * 35 * Based on the FreeBSD 'smist' cpufreq driver by Bruno Ducrot 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: piixpcib.c,v 1.19 2010/07/26 22:33:23 jym Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/sysctl.h> 46 #include <machine/bus.h> 47 48 #include <machine/frame.h> 49 #include <machine/bioscall.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 55 #include <i386/pci/piixreg.h> 56 #include <x86/pci/pcibvar.h> 57 58 #define PIIX4_PIRQRC 0x60 59 60 struct piixpcib_softc { 61 /* we call pcibattach() which assumes our softc starts like this: */ 62 63 struct pcib_softc sc_pcib; 64 65 device_t sc_dev; 66 67 int sc_smi_cmd; 68 int sc_smi_data; 69 int sc_command; 70 int sc_flags; 71 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_ioh; 74 75 pcireg_t sc_pirqrc; 76 uint8_t sc_elcr[2]; 77 }; 78 79 static int piixpcibmatch(device_t, cfdata_t, void *); 80 static void piixpcibattach(device_t, device_t, void *); 81 82 static bool piixpcib_suspend(device_t, const pmf_qual_t *); 83 static bool piixpcib_resume(device_t, const pmf_qual_t *); 84 85 static void speedstep_configure(struct piixpcib_softc *, 86 struct pci_attach_args *); 87 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 88 89 static struct piixpcib_softc *speedstep_cookie; /* XXX */ 90 91 CFATTACH_DECL_NEW(piixpcib, sizeof(struct piixpcib_softc), 92 piixpcibmatch, piixpcibattach, NULL, NULL); 93 94 /* 95 * Autoconf callbacks. 96 */ 97 static int 98 piixpcibmatch(device_t parent, cfdata_t match, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 102 /* We are ISA bridge, of course */ 103 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 104 (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA && 105 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_MISC)) { 106 return 0; 107 } 108 109 /* Matches only Intel PIIX4 */ 110 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 111 switch (PCI_PRODUCT(pa->pa_id)) { 112 case PCI_PRODUCT_INTEL_82371AB_ISA: /* PIIX4 */ 113 case PCI_PRODUCT_INTEL_82440MX_PMC: /* PIIX4 in MX440 */ 114 return 10; 115 } 116 } 117 118 return 0; 119 } 120 121 static void 122 piixpcibattach(device_t parent, device_t self, void *aux) 123 { 124 struct pci_attach_args *pa = aux; 125 struct piixpcib_softc *sc = device_private(self); 126 127 sc->sc_dev = self; 128 sc->sc_iot = pa->pa_iot; 129 130 pcibattach(parent, self, aux); 131 132 /* Set up SpeedStep. */ 133 speedstep_configure(sc, pa); 134 135 /* Map edge/level control registers */ 136 if (bus_space_map(sc->sc_iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 137 &sc->sc_ioh)) { 138 aprint_error_dev(self, "can't map edge/level control registers\n"); 139 return; 140 } 141 142 if (!pmf_device_register(self, piixpcib_suspend, piixpcib_resume)) 143 aprint_error_dev(self, "couldn't establish power handler\n"); 144 } 145 146 static bool 147 piixpcib_suspend(device_t dv, const pmf_qual_t *qual) 148 { 149 struct piixpcib_softc *sc = device_private(dv); 150 151 /* capture PIRQX route control registers */ 152 sc->sc_pirqrc = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 153 PIIX4_PIRQRC); 154 155 /* capture edge/level control registers */ 156 sc->sc_elcr[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0); 157 sc->sc_elcr[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 1); 158 159 return true; 160 } 161 162 static bool 163 piixpcib_resume(device_t dv, const pmf_qual_t *qual) 164 { 165 struct piixpcib_softc *sc = device_private(dv); 166 167 /* restore PIRQX route control registers */ 168 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, PIIX4_PIRQRC, 169 sc->sc_pirqrc); 170 171 /* restore edge/level control registers */ 172 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, sc->sc_elcr[0]); 173 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1, sc->sc_elcr[1]); 174 175 return true; 176 } 177 178 /* 179 * Intel PIIX4 (SMI) SpeedStep support. 180 */ 181 182 #define PIIXPCIB_GSIC 0x47534943 183 #define PIIXPCIB_GETOWNER 0 184 #define PIIXPCIB_GETSTATE 1 185 #define PIIXPCIB_SETSTATE 2 186 #define PIIXPCIB_GETFREQS 4 187 188 #define PIIXPCIB_SPEEDSTEP_HIGH 0 189 #define PIIXPCIB_SPEEDSTEP_LOW 1 190 191 static void 192 piixpcib_int15_gsic_call(int *sig, int *smicmd, int *cmd, int *smidata, int *flags) 193 { 194 struct bioscallregs regs; 195 196 memset(®s, 0, sizeof(struct bioscallregs)); 197 regs.EAX = 0x0000e980; /* IST support */ 198 regs.EDX = PIIXPCIB_GSIC; 199 bioscall(0x15, ®s); 200 201 if (regs.EAX == PIIXPCIB_GSIC) { 202 *sig = regs.EAX; 203 *smicmd = regs.EBX & 0xff; 204 *cmd = (regs.EBX >> 16) & 0xff; 205 *smidata = regs.ECX; 206 *flags = regs.EDX; 207 } else 208 *sig = *smicmd = *cmd = *smidata = *flags = -1; 209 210 return; 211 } 212 213 static int 214 piixpcib_set_ownership(struct piixpcib_softc *sc) 215 { 216 int rv; 217 u_long pmagic; 218 static char magic[] = "Copyright (c) 1999 Intel Corporation"; 219 220 pmagic = vtophys((vaddr_t)magic); 221 222 __asm__ __volatile__( 223 "movl $0, %%edi\n\t" 224 "out %%al, (%%dx)\n" 225 : "=D" (rv) 226 : "a" (sc->sc_command), 227 "b" (0), 228 "c" (0), 229 "d" (sc->sc_smi_cmd), 230 "S" (pmagic) 231 ); 232 233 return (rv ? ENXIO : 0); 234 } 235 236 static int 237 piixpcib_getset_state(struct piixpcib_softc *sc, int *state, int function) 238 { 239 int new; 240 int rv; 241 int eax; 242 243 #ifdef DIAGNOSTIC 244 if (function != PIIXPCIB_GETSTATE && 245 function != PIIXPCIB_SETSTATE) { 246 aprint_error_dev(sc->sc_dev, "GSI called with invalid function %d\n", 247 function); 248 return EINVAL; 249 } 250 #endif 251 252 __asm__ __volatile__( 253 "movl $0, %%edi\n\t" 254 "out %%al, (%%dx)\n" 255 : "=a" (eax), 256 "=b" (new), 257 "=D" (rv) 258 : "a" (sc->sc_command), 259 "b" (function), 260 "c" (*state), 261 "d" (sc->sc_smi_cmd), 262 "S" (0) 263 ); 264 265 *state = new & 1; 266 267 switch (function) { 268 case PIIXPCIB_GETSTATE: 269 if (eax) 270 return ENXIO; 271 break; 272 case PIIXPCIB_SETSTATE: 273 if (rv) 274 return ENXIO; 275 break; 276 } 277 278 return 0; 279 } 280 281 static int 282 piixpcib_get(struct piixpcib_softc *sc) 283 { 284 int rv; 285 int state; 286 287 state = 0; /* XXX gcc */ 288 289 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_GETSTATE); 290 if (rv) 291 return rv; 292 293 return state & 1; 294 } 295 296 static int 297 piixpcib_set(struct piixpcib_softc *sc, int state) 298 { 299 int rv, s; 300 int try; 301 302 if (state != PIIXPCIB_SPEEDSTEP_HIGH && 303 state != PIIXPCIB_SPEEDSTEP_LOW) 304 return ENXIO; 305 if (piixpcib_get(sc) == state) 306 return 0; 307 308 try = 5; 309 310 s = splhigh(); 311 312 do { 313 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_SETSTATE); 314 if (rv) 315 delay(200); 316 } while (rv && --try); 317 318 splx(s); 319 320 return rv; 321 } 322 323 static void 324 speedstep_configure(struct piixpcib_softc *sc, 325 struct pci_attach_args *pa) 326 { 327 const struct sysctlnode *node, *ssnode; 328 int sig, smicmd, cmd, smidata, flags; 329 int rv; 330 331 piixpcib_int15_gsic_call(&sig, &smicmd, &cmd, &smidata, &flags); 332 333 if (sig != -1) { 334 sc->sc_smi_cmd = smicmd; 335 sc->sc_smi_data = smidata; 336 if (cmd == 0x80) { 337 aprint_debug_dev(sc->sc_dev, "GSIC returned cmd 0x80, should be 0x82\n"); 338 cmd = 0x82; 339 } 340 sc->sc_command = (sig & 0xffffff00) | (cmd & 0xff); 341 sc->sc_flags = flags; 342 } else { 343 /* setup some defaults */ 344 sc->sc_smi_cmd = 0xb2; 345 sc->sc_smi_data = 0xb3; 346 sc->sc_command = 0x47534982; 347 sc->sc_flags = 0; 348 } 349 350 if (piixpcib_set_ownership(sc) != 0) { 351 aprint_error_dev(sc->sc_dev, "unable to claim ownership from the BIOS\n"); 352 return; /* If we can't claim ownership from the BIOS, bail */ 353 } 354 355 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 356 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 357 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 358 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 359 goto err; 360 361 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 362 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 363 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 364 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 365 CTL_EOL)) != 0) 366 goto err; 367 368 /* XXX save the sc for IO tag/handle */ 369 speedstep_cookie = sc; 370 371 aprint_verbose_dev(sc->sc_dev, "SpeedStep SMI enabled\n"); 372 return; 373 374 err: 375 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 376 } 377 378 /* 379 * get/set the SpeedStep state: 0 == low power, 1 == high power. 380 */ 381 static int 382 speedstep_sysctl_helper(SYSCTLFN_ARGS) 383 { 384 struct sysctlnode node; 385 struct piixpcib_softc *sc; 386 uint8_t state, state2; 387 int ostate, nstate, error; 388 389 sc = speedstep_cookie; 390 error = 0; 391 392 state = piixpcib_get(sc); 393 if (state == PIIXPCIB_SPEEDSTEP_HIGH) 394 ostate = 1; 395 else 396 ostate = 0; 397 nstate = ostate; 398 399 node = *rnode; 400 node.sysctl_data = &nstate; 401 402 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 403 if (error || newp == NULL) 404 goto out; 405 406 /* Only two states are available */ 407 if (nstate != 0 && nstate != 1) { 408 error = EINVAL; 409 goto out; 410 } 411 412 state2 = piixpcib_get(sc); 413 if (state2 == PIIXPCIB_SPEEDSTEP_HIGH) 414 ostate = 1; 415 else 416 ostate = 0; 417 418 if (ostate != nstate) 419 { 420 if (nstate == 0) 421 state2 = PIIXPCIB_SPEEDSTEP_LOW; 422 else 423 state2 = PIIXPCIB_SPEEDSTEP_HIGH; 424 425 error = piixpcib_set(sc, state2); 426 } 427 out: 428 return (error); 429 } 430