1 /* $NetBSD: via82c586.c,v 1.4 2001/11/15 07:03:35 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Support for the VIA 82c586 PCI-ISA bridge interrupt controller. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: via82c586.c,v 1.4 2001/11/15 07:03:35 lukem Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/device.h> 75 76 #include <machine/intr.h> 77 #include <machine/bus.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <i386/pci/pci_intr_fixup.h> 84 #include <i386/pci/via82c586reg.h> 85 #include <i386/pci/piixvar.h> 86 87 int via82c586_getclink __P((pciintr_icu_handle_t, int, int *)); 88 int via82c586_get_intr __P((pciintr_icu_handle_t, int, int *)); 89 int via82c586_set_intr __P((pciintr_icu_handle_t, int, int)); 90 int via82c586_get_trigger __P((pciintr_icu_handle_t, int, int *)); 91 int via82c586_set_trigger __P((pciintr_icu_handle_t, int, int)); 92 93 const struct pciintr_icu via82c586_pci_icu = { 94 via82c586_getclink, 95 via82c586_get_intr, 96 via82c586_set_intr, 97 via82c586_get_trigger, 98 via82c586_set_trigger, 99 }; 100 101 const int vp3_cfg_trigger_shift[] = { 102 VP3_CFG_TRIGGER_SHIFT_PIRQA, 103 VP3_CFG_TRIGGER_SHIFT_PIRQB, 104 VP3_CFG_TRIGGER_SHIFT_PIRQC, 105 VP3_CFG_TRIGGER_SHIFT_PIRQD, 106 }; 107 108 #define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \ 109 VP3_CFG_TRIGGER_MASK) 110 111 const int vp3_cfg_intr_shift[] = { 112 VP3_CFG_INTR_SHIFT_PIRQA, 113 VP3_CFG_INTR_SHIFT_PIRQB, 114 VP3_CFG_INTR_SHIFT_PIRQC, 115 VP3_CFG_INTR_SHIFT_PIRQD, 116 }; 117 118 #define VP3_PIRQ(reg, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \ 119 VP3_CFG_INTR_MASK) 120 121 int 122 via82c586_init(pc, iot, tag, ptagp, phandp) 123 pci_chipset_tag_t pc; 124 bus_space_tag_t iot; 125 pcitag_t tag; 126 pciintr_icu_tag_t *ptagp; 127 pciintr_icu_handle_t *phandp; 128 { 129 pcireg_t reg; 130 131 if (piix_init(pc, iot, tag, ptagp, phandp) == 0) { 132 *ptagp = &via82c586_pci_icu; 133 134 /* 135 * Enable EISA ELCR. 136 */ 137 reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG); 138 reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE << 139 VP3_CFG_MISCCTRL2_SHIFT; 140 pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg); 141 142 return (0); 143 } 144 145 return (1); 146 } 147 148 int 149 via82c586_getclink(v, link, clinkp) 150 pciintr_icu_handle_t v; 151 int link, *clinkp; 152 { 153 154 if (VP3_LEGAL_LINK(link - 1)) { 155 *clinkp = link - 1; 156 return (0); 157 } 158 159 return (1); 160 } 161 162 int 163 via82c586_get_intr(v, clink, irqp) 164 pciintr_icu_handle_t v; 165 int clink, *irqp; 166 { 167 struct piix_handle *ph = v; 168 pcireg_t reg; 169 int val; 170 171 if (VP3_LEGAL_LINK(clink) == 0) 172 return (1); 173 174 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); 175 val = VP3_PIRQ(reg, clink); 176 *irqp = (val == VP3_PIRQ_NONE) ? 177 I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val; 178 179 return (0); 180 } 181 182 int 183 via82c586_set_intr(v, clink, irq) 184 pciintr_icu_handle_t v; 185 int clink, irq; 186 { 187 struct piix_handle *ph = v; 188 int shift, val; 189 pcireg_t reg; 190 191 if (VP3_LEGAL_LINK(clink) == 0 || VP3_LEGAL_IRQ(irq) == 0) 192 return (1); 193 194 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); 195 via82c586_get_intr(v, clink, &val); 196 shift = vp3_cfg_intr_shift[clink]; 197 reg &= ~(VP3_CFG_INTR_MASK << shift); 198 reg |= (irq << shift); 199 pci_conf_write(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG, reg); 200 if (via82c586_get_intr(v, clink, &val) != 0 || 201 val != irq) 202 return (1); 203 204 return (0); 205 } 206 207 int 208 via82c586_get_trigger(v, irq, triggerp) 209 pciintr_icu_handle_t v; 210 int irq, *triggerp; 211 { 212 struct piix_handle *ph = v; 213 int i, error, check_consistency, pciirq, pcitrigger = IST_NONE; 214 pcireg_t reg; 215 216 if (VP3_LEGAL_IRQ(irq) == 0) 217 return (1); 218 219 check_consistency = 0; 220 for (i = 0; i <= 3; i++) { 221 via82c586_get_intr(v, i, &pciirq); 222 if (pciirq == irq) { 223 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, 224 VP3_CFG_PIRQ_REG); 225 if (VP3_TRIGGER(reg, i) == VP3_CFG_TRIGGER_EDGE) 226 pcitrigger = IST_EDGE; 227 else 228 pcitrigger = IST_LEVEL; 229 check_consistency = 1; 230 break; 231 } 232 } 233 234 error = piix_get_trigger(v, irq, triggerp); 235 if (error == 0 && check_consistency && pcitrigger != *triggerp) 236 return (1); 237 return (error); 238 } 239 240 int 241 via82c586_set_trigger(v, irq, trigger) 242 pciintr_icu_handle_t v; 243 int irq, trigger; 244 { 245 struct piix_handle *ph = v; 246 int i, pciirq, shift, testtrig; 247 pcireg_t reg; 248 249 if (VP3_LEGAL_IRQ(irq) == 0) 250 return (1); 251 252 for (i = 0; i <= 3; i++) { 253 via82c586_get_intr(v, i, &pciirq); 254 if (pciirq == irq) { 255 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, 256 VP3_CFG_PIRQ_REG); 257 shift = vp3_cfg_trigger_shift[i]; 258 if (trigger == IST_LEVEL) 259 reg &= ~(VP3_CFG_TRIGGER_MASK << shift); 260 else 261 reg |= (VP3_CFG_TRIGGER_EDGE << shift); 262 pci_conf_write(ph->ph_pc, ph->ph_tag, 263 VP3_CFG_PIRQ_REG, reg); 264 break; 265 } 266 } 267 268 if (piix_set_trigger(v, irq, trigger) != 0 || 269 via82c586_get_trigger(v, irq, &testtrig) != 0 || 270 testtrig != trigger) 271 return (1); 272 273 return (0); 274 } 275