1 /* $NetBSD: fpu_explode.c,v 1.3 1999/05/30 20:17:48 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `explode' the machine's `packed binary' format numbers 49 * into our internal format. 50 */ 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include "ieee.h" 56 #include <machine/reg.h> 57 58 #include "fpu_arith.h" 59 #include "fpu_emulate.h" 60 61 62 /* Conversion to internal format -- note asymmetry. */ 63 static int fpu_itof __P((struct fpn *fp, u_int i)); 64 static int fpu_stof __P((struct fpn *fp, u_int i)); 65 static int fpu_dtof __P((struct fpn *fp, u_int i, u_int j)); 66 static int fpu_xtof __P((struct fpn *fp, u_int i, u_int j, u_int k)); 67 68 /* 69 * N.B.: in all of the following, we assume the FP format is 70 * 71 * --------------------------- 72 * | s | exponent | fraction | 73 * --------------------------- 74 * 75 * (which represents -1**s * 1.fraction * 2**exponent), so that the 76 * sign bit is way at the top (bit 31), the exponent is next, and 77 * then the remaining bits mark the fraction. A zero exponent means 78 * zero or denormalized (0.fraction rather than 1.fraction), and the 79 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 80 * 81 * Since the sign bit is always the topmost bit---this holds even for 82 * integers---we set that outside all the *tof functions. Each function 83 * returns the class code for the new number (but note that we use 84 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 85 */ 86 87 /* 88 * int -> fpn. 89 */ 90 static int 91 fpu_itof(fp, i) 92 register struct fpn *fp; 93 register u_int i; 94 { 95 96 if (i == 0) 97 return (FPC_ZERO); 98 /* 99 * The value FP_1 represents 2^FP_LG, so set the exponent 100 * there and let normalization fix it up. Convert negative 101 * numbers to sign-and-magnitude. Note that this relies on 102 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 103 */ 104 fp->fp_exp = FP_LG; 105 fp->fp_mant[0] = (int)i < 0 ? -i : i; 106 fp->fp_mant[1] = 0; 107 fp->fp_mant[2] = 0; 108 fpu_norm(fp); 109 return (FPC_NUM); 110 } 111 112 #define mask(nbits) ((1 << (nbits)) - 1) 113 114 /* 115 * All external floating formats convert to internal in the same manner, 116 * as defined here. Note that only normals get an implied 1.0 inserted. 117 */ 118 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 119 if (exp == 0) { \ 120 if (allfrac == 0) \ 121 return (FPC_ZERO); \ 122 fp->fp_exp = 1 - expbias; \ 123 fp->fp_mant[0] = f0; \ 124 fp->fp_mant[1] = f1; \ 125 fp->fp_mant[2] = f2; \ 126 fpu_norm(fp); \ 127 return (FPC_NUM); \ 128 } \ 129 if (exp == (2 * expbias + 1)) { \ 130 if (allfrac == 0) \ 131 return (FPC_INF); \ 132 fp->fp_mant[0] = f0; \ 133 fp->fp_mant[1] = f1; \ 134 fp->fp_mant[2] = f2; \ 135 return (FPC_QNAN); \ 136 } \ 137 fp->fp_exp = exp - expbias; \ 138 fp->fp_mant[0] = FP_1 | f0; \ 139 fp->fp_mant[1] = f1; \ 140 fp->fp_mant[2] = f2; \ 141 return (FPC_NUM) 142 143 /* 144 * 32-bit single precision -> fpn. 145 * We assume a single occupies at most (64-FP_LG) bits in the internal 146 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 147 */ 148 static int 149 fpu_stof(fp, i) 150 register struct fpn *fp; 151 register u_int i; 152 { 153 register int exp; 154 register u_int frac, f0, f1; 155 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 156 157 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 158 frac = i & mask(SNG_FRACBITS); 159 f0 = frac >> SNG_SHIFT; 160 f1 = frac << (32 - SNG_SHIFT); 161 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 162 } 163 164 /* 165 * 64-bit double -> fpn. 166 * We assume this uses at most (96-FP_LG) bits. 167 */ 168 static int 169 fpu_dtof(fp, i, j) 170 register struct fpn *fp; 171 register u_int i, j; 172 { 173 register int exp; 174 register u_int frac, f0, f1, f2; 175 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 176 177 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 178 frac = i & mask(DBL_FRACBITS - 32); 179 f0 = frac >> DBL_SHIFT; 180 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 181 f2 = j << (32 - DBL_SHIFT); 182 frac |= j; 183 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 184 } 185 186 /* 187 * 96-bit extended -> fpn. 188 */ 189 static int 190 fpu_xtof(fp, i, j, k) 191 register struct fpn *fp; 192 register u_int i, j, k; 193 { 194 register int exp; 195 register u_int frac, f0, f1, f2; 196 #define EXT_SHIFT (EXT_FRACBITS - 1 - 32 - FP_LG) 197 198 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 199 f0 = j >> EXT_SHIFT; 200 f1 = (j << (32 - EXT_SHIFT)) | (k >> EXT_SHIFT); 201 f2 = k << (32 - EXT_SHIFT); 202 frac = j | k; 203 204 /* m68k extended does not imply denormal by exp==0 */ 205 if (exp == 0) { 206 if (frac == 0) 207 return (FPC_ZERO); 208 fp->fp_exp = - EXT_EXP_BIAS; 209 fp->fp_mant[0] = f0; 210 fp->fp_mant[1] = f1; 211 fp->fp_mant[2] = f2; 212 fpu_norm(fp); 213 return (FPC_NUM); 214 } 215 if (exp == (2 * EXT_EXP_BIAS + 1)) { 216 if (frac == 0) 217 return (FPC_INF); 218 fp->fp_mant[0] = f0; 219 fp->fp_mant[1] = f1; 220 fp->fp_mant[2] = f2; 221 return (FPC_QNAN); 222 } 223 fp->fp_exp = exp - EXT_EXP_BIAS; 224 fp->fp_mant[0] = FP_1 | f0; 225 fp->fp_mant[1] = f1; 226 fp->fp_mant[2] = f2; 227 return (FPC_NUM); 228 } 229 230 /* 231 * Explode the contents of a memory operand. 232 */ 233 void 234 fpu_explode(fe, fp, type, space) 235 register struct fpemu *fe; 236 register struct fpn *fp; 237 int type; 238 register u_int *space; 239 { 240 register u_int s; 241 242 s = space[0]; 243 fp->fp_sign = s >> 31; 244 fp->fp_sticky = 0; 245 switch (type) { 246 247 case FTYPE_BYT: 248 s >>= 8; 249 case FTYPE_WRD: 250 s >>= 16; 251 case FTYPE_LNG: 252 s = fpu_itof(fp, s); 253 break; 254 255 case FTYPE_SNG: 256 s = fpu_stof(fp, s); 257 break; 258 259 case FTYPE_DBL: 260 s = fpu_dtof(fp, s, space[1]); 261 break; 262 263 case FTYPE_EXT: 264 s = fpu_xtof(fp, s, space[1], space[2]); 265 break; 266 267 default: 268 panic("fpu_explode"); 269 } 270 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 271 /* 272 * Input is a signalling NaN. All operations that return 273 * an input NaN operand put it through a ``NaN conversion'', 274 * which basically just means ``turn on the quiet bit''. 275 * We do this here so that all NaNs internally look quiet 276 * (we can tell signalling ones by their class). 277 */ 278 fp->fp_mant[0] |= FP_QUIETBIT; 279 fe->fe_fpsr |= FPSR_SNAN; /* assert SNAN exception */ 280 s = FPC_SNAN; 281 } 282 fp->fp_class = s; 283 } 284