1 /* $NetBSD: fpu_fscale.c,v 1.13 2009/03/14 15:36:09 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Ken Nakata 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 4. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Gordon Ross 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * FSCALE - separated from the other type0 arithmetic instructions 35 * for performance reason; maybe unnecessary, but FSCALE assumes 36 * the source operand be an integer. It performs type conversion 37 * only if the source operand is *not* an integer. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: fpu_fscale.c,v 1.13 2009/03/14 15:36:09 dsl Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/signal.h> 45 #include <sys/systm.h> 46 #include <machine/frame.h> 47 48 #include "fpu_emulate.h" 49 50 int 51 fpu_emul_fscale(struct fpemu *fe, struct instruction *insn) 52 { 53 struct frame *frame; 54 u_int *fpregs; 55 int word1, sig; 56 int regnum, format; 57 int scale, sign, exp; 58 u_int m0, m1; 59 u_int buf[3], fpsr; 60 #if DEBUG_FPE 61 int flags; 62 char regname; 63 #endif 64 65 scale = sig = 0; 66 frame = fe->fe_frame; 67 fpregs = &(fe->fe_fpframe->fpf_regs[0]); 68 /* clear all exceptions and conditions */ 69 fpsr = fe->fe_fpsr & ~FPSR_EXCP & ~FPSR_CCB; 70 #if DEBUG_FPE 71 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", fpsr, fe->fe_fpcr); 72 #endif 73 74 word1 = insn->is_word1; 75 format = (word1 >> 10) & 7; 76 regnum = (word1 >> 7) & 7; 77 78 fe->fe_fpcr &= FPCR_ROUND; 79 fe->fe_fpcr |= FPCR_ZERO; 80 81 /* get the source operand */ 82 if ((word1 & 0x4000) == 0) { 83 #if DEBUG_FPE 84 printf("fpu_emul_fscale: FP%d op FP%d => FP%d\n", 85 format, regnum, regnum); 86 /* the operand is an FP reg */ 87 printf("fpu_emul_scale: src opr FP%d=%08x%08x%08x\n", 88 format, fpregs[format*3], fpregs[format*3+1], 89 fpregs[format*3+2]); 90 #endif 91 fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]); 92 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 93 scale = buf[0]; 94 } else { 95 /* the operand is in memory */ 96 if (format == FTYPE_DBL) { 97 insn->is_datasize = 8; 98 } else if (format == FTYPE_SNG || format == FTYPE_LNG) { 99 insn->is_datasize = 4; 100 } else if (format == FTYPE_WRD) { 101 insn->is_datasize = 2; 102 } else if (format == FTYPE_BYT) { 103 insn->is_datasize = 1; 104 } else if (format == FTYPE_EXT) { 105 insn->is_datasize = 12; 106 } else { 107 /* invalid or unsupported operand format */ 108 sig = SIGFPE; 109 return sig; 110 } 111 112 /* Get effective address. (modreg=opcode&077) */ 113 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 114 if (sig) { 115 #if DEBUG_FPE 116 printf("fpu_emul_fscale: error in decode_ea\n"); 117 #endif 118 return sig; 119 } 120 121 #if DEBUG_FPE 122 printf("fpu_emul_fscale: addr mode = "); 123 flags = insn->is_ea.ea_flags; 124 regname = (insn->is_ea.ea_regnum & 8) ? 'a' : 'd'; 125 126 if (flags & EA_DIRECT) { 127 printf("%c%d\n", regname, insn->is_ea.ea_regnum & 7); 128 } else if (flags & EA_PREDECR) { 129 printf("%c%d@-\n", regname, insn->is_ea.ea_regnum & 7); 130 } else if (flags & EA_POSTINCR) { 131 printf("%c%d@+\n", regname, insn->is_ea.ea_regnum & 7); 132 } else if (flags & EA_OFFSET) { 133 printf("%c%d@(%d)\n", regname, insn->is_ea.ea_regnum & 7, 134 insn->is_ea.ea_offset); 135 } else if (flags & EA_INDEXED) { 136 printf("%c%d@(...)\n", regname, insn->is_ea.ea_regnum & 7); 137 } else if (flags & EA_ABS) { 138 printf("0x%08x\n", insn->is_ea.ea_absaddr); 139 } else if (flags & EA_PC_REL) { 140 printf("pc@(%d)\n", insn->is_ea.ea_offset); 141 } else if (flags & EA_IMMED) { 142 printf("#0x%08x%08x%08x\n", 143 insn->is_ea.ea_immed[0], insn->is_ea.ea_immed[1], 144 insn->is_ea.ea_immed[2]); 145 } else { 146 printf("%c%d@\n", regname, insn->is_ea.ea_regnum & 7); 147 } 148 #endif 149 fpu_load_ea(frame, insn, &insn->is_ea, (char*)buf); 150 151 #if DEBUG_FPE 152 printf("fpu_emul_fscale: src = %08x%08x%08x, siz = %d\n", 153 buf[0], buf[1], buf[2], insn->is_datasize); 154 #endif 155 if (format == FTYPE_LNG) { 156 /* nothing */ 157 scale = buf[0]; 158 } else if (format == FTYPE_WRD) { 159 /* sign-extend */ 160 scale = buf[0] & 0xffff; 161 if (scale & 0x8000) { 162 scale |= 0xffff0000; 163 } 164 } else if (format == FTYPE_BYT) { 165 /* sign-extend */ 166 scale = buf[0] & 0xff; 167 if (scale & 0x80) { 168 scale |= 0xffffff00; 169 } 170 } else if (format == FTYPE_DBL || format == FTYPE_SNG || 171 format == FTYPE_EXT) { 172 fpu_explode(fe, &fe->fe_f2, format, buf); 173 fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf); 174 scale = buf[0]; 175 } 176 /* make it look like we've got an FP oprand */ 177 fe->fe_f2.fp_class = (buf[0] == 0) ? FPC_ZERO : FPC_NUM; 178 } 179 180 /* assume there's no exception */ 181 sig = 0; 182 183 /* it's barbaric but we're going to operate directly on 184 * the dst operand's bit pattern */ 185 sign = fpregs[regnum * 3] & 0x80000000; 186 exp = (fpregs[regnum * 3] & 0x7fff0000) >> 16; 187 m0 = fpregs[regnum * 3 + 1]; 188 m1 = fpregs[regnum * 3 + 2]; 189 190 switch (fe->fe_f2.fp_class) { 191 case FPC_SNAN: 192 fpsr |= FPSR_SNAN; 193 case FPC_QNAN: 194 /* dst = NaN */ 195 exp = 0x7fff; 196 m0 = m1 = 0xffffffff; 197 break; 198 case FPC_ZERO: 199 case FPC_NUM: 200 if ((0 < exp && exp < 0x7fff) || 201 (exp == 0 && (m0 | m1) != 0)) { 202 /* normal or denormal */ 203 exp += scale; 204 if (exp < 0) { 205 /* underflow */ 206 u_int grs; /* guard, round and sticky */ 207 208 exp = 0; 209 grs = m1 << (32 + exp); 210 m1 = m0 << (32 + exp) | m1 >> -exp; 211 m0 >>= -exp; 212 if (grs != 0) { 213 fpsr |= FPSR_INEX2; 214 215 switch (fe->fe_fpcr & 0x30) { 216 case FPCR_MINF: 217 if (sign != 0) { 218 if (++m1 == 0 && 219 ++m0 == 0) { 220 m0 = 0x80000000; 221 exp++; 222 } 223 } 224 break; 225 case FPCR_NEAR: 226 if (grs == 0x80000000) { 227 /* tie */ 228 if ((m1 & 1) && 229 ++m1 == 0 && 230 ++m0 == 0) { 231 m0 = 0x80000000; 232 exp++; 233 } 234 } else if (grs & 0x80000000) { 235 if (++m1 == 0 && 236 ++m0 == 0) { 237 m0 = 0x80000000; 238 exp++; 239 } 240 } 241 break; 242 case FPCR_PINF: 243 if (sign == 0) { 244 if (++m1 == 0 && 245 ++m0 == 0) { 246 m0 = 0x80000000; 247 exp++; 248 } 249 } 250 break; 251 case FPCR_ZERO: 252 break; 253 } 254 } 255 if (exp == 0 && (m0 & 0x80000000) == 0) { 256 fpsr |= FPSR_UNFL; 257 if ((m0 | m1) == 0) { 258 fpsr |= FPSR_ZERO; 259 } 260 } 261 } else if (exp >= 0x7fff) { 262 /* overflow --> result = Inf */ 263 /* but first, try to normalize in case it's an unnormalized */ 264 while ((m0 & 0x80000000) == 0) { 265 exp--; 266 m0 = (m0 << 1) | (m1 >> 31); 267 m1 = m1 << 1; 268 } 269 /* if it's still too large, then return Inf */ 270 if (exp >= 0x7fff) { 271 exp = 0x7fff; 272 m0 = m1 = 0; 273 fpsr |= FPSR_OVFL | FPSR_INF; 274 } 275 } else if ((m0 & 0x80000000) == 0) { 276 /* 277 * it's a denormal; we try to normalize but 278 * result may and may not be a normal. 279 */ 280 while (exp > 0 && (m0 & 0x80000000) == 0) { 281 exp--; 282 m0 = (m0 << 1) | (m1 >> 31); 283 m1 = m1 << 1; 284 } 285 if ((m0 & 0x80000000) == 0) { 286 fpsr |= FPSR_UNFL; 287 } 288 } /* exp in range and mantissa normalized */ 289 } else if (exp == 0 && m0 == 0 && m1 == 0) { 290 /* dst is Zero */ 291 fpsr |= FPSR_ZERO; 292 } /* else we know exp == 0x7fff */ 293 else if ((m0 | m1) == 0) { 294 fpsr |= FPSR_INF; 295 } else if ((m0 & 0x40000000) == 0) { 296 /* a signaling NaN */ 297 fpsr |= FPSR_NAN | FPSR_SNAN; 298 } else { 299 /* a quiet NaN */ 300 fpsr |= FPSR_NAN; 301 } 302 break; 303 case FPC_INF: 304 /* dst = NaN */ 305 exp = 0x7fff; 306 m0 = m1 = 0xffffffff; 307 fpsr |= FPSR_OPERR | FPSR_NAN; 308 break; 309 default: 310 #ifdef DEBUG 311 panic("fpu_emul_fscale: invalid fp class"); 312 #endif 313 break; 314 } 315 316 /* store the result */ 317 fpregs[regnum * 3] = sign | (exp << 16); 318 fpregs[regnum * 3 + 1] = m0; 319 fpregs[regnum * 3 + 2] = m1; 320 321 if (sign) { 322 fpsr |= FPSR_NEG; 323 } 324 325 /* update fpsr according to the result of operation */ 326 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 327 328 #if DEBUG_FPE 329 printf("fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", 330 fe->fe_fpsr, fe->fe_fpcr); 331 #endif 332 333 return (fpsr & fe->fe_fpcr & FPSR_EXCP) ? SIGFPE : sig; 334 } 335