1 /* $NetBSD: fpu_implode.c,v 1.5 2001/02/18 20:05:58 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `implode' internal format numbers into the machine's 49 * `packed binary' format. 50 */ 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include "ieee.h" 56 #include <machine/reg.h> 57 58 #include "fpu_emulate.h" 59 #include "fpu_arith.h" 60 61 /* Conversion from internal format -- note asymmetry. */ 62 static u_int fpu_ftoi __P((struct fpemu *fe, struct fpn *fp)); 63 static u_int fpu_ftos __P((struct fpemu *fe, struct fpn *fp)); 64 static u_int fpu_ftod __P((struct fpemu *fe, struct fpn *fp, u_int *)); 65 static u_int fpu_ftox __P((struct fpemu *fe, struct fpn *fp, u_int *)); 66 67 /* 68 * Round a number (algorithm from Motorola MC68882 manual, modified for 69 * our internal format). Set inexact exception if rounding is required. 70 * Return true iff we rounded up. 71 * 72 * After rounding, we discard the guard and round bits by shifting right 73 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 74 * This saves effort later. 75 * 76 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 77 * responsibility to fix this if necessary. 78 */ 79 int 80 fpu_round(register struct fpemu *fe, register struct fpn *fp) 81 { 82 register u_int m0, m1, m2; 83 register int gr, s; 84 85 m0 = fp->fp_mant[0]; 86 m1 = fp->fp_mant[1]; 87 m2 = fp->fp_mant[2]; 88 gr = m2 & 3; 89 s = fp->fp_sticky; 90 91 /* mant >>= FP_NG */ 92 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 93 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 94 m0 >>= FP_NG; 95 96 if ((gr | s) == 0) /* result is exact: no rounding needed */ 97 goto rounddown; 98 99 fe->fe_fpsr |= FPSR_INEX2; /* inexact */ 100 101 /* Go to rounddown to round down; break to round up. */ 102 switch (fe->fe_fpcr & FPCR_ROUND) { 103 104 case FPCR_NEAR: 105 default: 106 /* 107 * Round only if guard is set (gr & 2). If guard is set, 108 * but round & sticky both clear, then we want to round 109 * but have a tie, so round to even, i.e., add 1 iff odd. 110 */ 111 if ((gr & 2) == 0) 112 goto rounddown; 113 if ((gr & 1) || fp->fp_sticky || (m2 & 1)) 114 break; 115 goto rounddown; 116 117 case FPCR_ZERO: 118 /* Round towards zero, i.e., down. */ 119 goto rounddown; 120 121 case FPCR_MINF: 122 /* Round towards -Inf: up if negative, down if positive. */ 123 if (fp->fp_sign) 124 break; 125 goto rounddown; 126 127 case FPCR_PINF: 128 /* Round towards +Inf: up if positive, down otherwise. */ 129 if (!fp->fp_sign) 130 break; 131 goto rounddown; 132 } 133 134 /* Bump low bit of mantissa, with carry. */ 135 if (++m2 == 0 && ++m1 == 0) 136 m0++; 137 fp->fp_sticky = 0; 138 fp->fp_mant[0] = m0; 139 fp->fp_mant[1] = m1; 140 fp->fp_mant[2] = m2; 141 return (1); 142 143 rounddown: 144 fp->fp_sticky = 0; 145 fp->fp_mant[0] = m0; 146 fp->fp_mant[1] = m1; 147 fp->fp_mant[2] = m2; 148 return (0); 149 } 150 151 /* 152 * For overflow: return true if overflow is to go to +/-Inf, according 153 * to the sign of the overflowing result. If false, overflow is to go 154 * to the largest magnitude value instead. 155 */ 156 static int 157 toinf(struct fpemu *fe, int sign) 158 { 159 int inf; 160 161 /* look at rounding direction */ 162 switch (fe->fe_fpcr & FPCR_ROUND) { 163 164 default: 165 case FPCR_NEAR: /* the nearest value is always Inf */ 166 inf = 1; 167 break; 168 169 case FPCR_ZERO: /* toward 0 => never towards Inf */ 170 inf = 0; 171 break; 172 173 case FPCR_PINF: /* toward +Inf iff positive */ 174 inf = (sign == 0); 175 break; 176 177 case FPCR_MINF: /* toward -Inf iff negative */ 178 inf = sign; 179 break; 180 } 181 return (inf); 182 } 183 184 /* 185 * fpn -> int (int value returned as return value). 186 * 187 * N.B.: this conversion always rounds towards zero (this is a peculiarity 188 * of the SPARC instruction set). 189 */ 190 static u_int 191 fpu_ftoi(fe, fp) 192 struct fpemu *fe; 193 register struct fpn *fp; 194 { 195 register u_int i; 196 register int sign, exp; 197 198 sign = fp->fp_sign; 199 switch (fp->fp_class) { 200 201 case FPC_ZERO: 202 return (0); 203 204 case FPC_NUM: 205 /* 206 * If exp >= 2^32, overflow. Otherwise shift value right 207 * into last mantissa word (this will not exceed 0xffffffff), 208 * shifting any guard and round bits out into the sticky 209 * bit. Then ``round'' towards zero, i.e., just set an 210 * inexact exception if sticky is set (see fpu_round()). 211 * If the result is > 0x80000000, or is positive and equals 212 * 0x80000000, overflow; otherwise the last fraction word 213 * is the result. 214 */ 215 if ((exp = fp->fp_exp) >= 32) 216 break; 217 /* NB: the following includes exp < 0 cases */ 218 if (fpu_shr(fp, FP_NMANT - 1 - FP_NG - exp) != 0) 219 /* m68881/2 do not underflow when 220 converting to integer */; 221 fpu_round(fe, fp); 222 i = fp->fp_mant[2]; 223 if (i >= ((u_int)0x80000000 + sign)) 224 break; 225 return (sign ? -i : i); 226 227 default: /* Inf, qNaN, sNaN */ 228 break; 229 } 230 /* overflow: replace any inexact exception with invalid */ 231 fe->fe_fpsr = (fe->fe_fpsr & ~FPSR_INEX2) | FPSR_OPERR; 232 return (0x7fffffff + sign); 233 } 234 235 /* 236 * fpn -> single (32 bit single returned as return value). 237 * We assume <= 29 bits in a single-precision fraction (1.f part). 238 */ 239 static u_int 240 fpu_ftos(fe, fp) 241 struct fpemu *fe; 242 register struct fpn *fp; 243 { 244 register u_int sign = fp->fp_sign << 31; 245 register int exp; 246 247 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 248 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 249 250 /* Take care of non-numbers first. */ 251 if (ISNAN(fp)) { 252 /* 253 * Preserve upper bits of NaN, per SPARC V8 appendix N. 254 * Note that fp->fp_mant[0] has the quiet bit set, 255 * even if it is classified as a signalling NaN. 256 */ 257 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 258 exp = SNG_EXP_INFNAN; 259 goto done; 260 } 261 if (ISINF(fp)) 262 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 263 if (ISZERO(fp)) 264 return (sign); 265 266 /* 267 * Normals (including subnormals). Drop all the fraction bits 268 * (including the explicit ``implied'' 1 bit) down into the 269 * single-precision range. If the number is subnormal, move 270 * the ``implied'' 1 into the explicit range as well, and shift 271 * right to introduce leading zeroes. Rounding then acts 272 * differently for normals and subnormals: the largest subnormal 273 * may round to the smallest normal (1.0 x 2^minexp), or may 274 * remain subnormal. In the latter case, signal an underflow 275 * if the result was inexact or if underflow traps are enabled. 276 * 277 * Rounding a normal, on the other hand, always produces another 278 * normal (although either way the result might be too big for 279 * single precision, and cause an overflow). If rounding a 280 * normal produces 2.0 in the fraction, we need not adjust that 281 * fraction at all, since both 1.0 and 2.0 are zero under the 282 * fraction mask. 283 * 284 * Note that the guard and round bits vanish from the number after 285 * rounding. 286 */ 287 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 288 fe->fe_fpsr |= FPSR_UNFL; 289 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 290 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 291 if (fpu_round(fe, fp) && fp->fp_mant[2] == SNG_EXP(1)) 292 return (sign | SNG_EXP(1) | 0); 293 if (fe->fe_fpsr & FPSR_INEX2) 294 fe->fe_fpsr |= FPSR_UNFL 295 /* mc68881/2 don't underflow when converting */; 296 return (sign | SNG_EXP(0) | fp->fp_mant[2]); 297 } 298 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 299 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 300 #ifdef DIAGNOSTIC 301 if ((fp->fp_mant[2] & SNG_EXP(1 << FP_NG)) == 0) 302 panic("fpu_ftos"); 303 #endif 304 if (fpu_round(fe, fp) && fp->fp_mant[2] == SNG_EXP(2)) 305 exp++; 306 if (exp >= SNG_EXP_INFNAN) { 307 /* overflow to inf or to max single */ 308 fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2 | FPSR_OVFL; 309 if (toinf(fe, sign)) 310 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 311 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 312 } 313 done: 314 /* phew, made it */ 315 return (sign | SNG_EXP(exp) | (fp->fp_mant[2] & SNG_MASK)); 316 } 317 318 /* 319 * fpn -> double (32 bit high-order result returned; 32-bit low order result 320 * left in res[1]). Assumes <= 61 bits in double precision fraction. 321 * 322 * This code mimics fpu_ftos; see it for comments. 323 */ 324 static u_int 325 fpu_ftod(fe, fp, res) 326 struct fpemu *fe; 327 register struct fpn *fp; 328 u_int *res; 329 { 330 register u_int sign = fp->fp_sign << 31; 331 register int exp; 332 333 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 334 #define DBL_MASK (DBL_EXP(1) - 1) 335 336 if (ISNAN(fp)) { 337 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 338 exp = DBL_EXP_INFNAN; 339 goto done; 340 } 341 if (ISINF(fp)) { 342 sign |= DBL_EXP(DBL_EXP_INFNAN); 343 res[1] = 0; 344 return (sign); 345 } 346 if (ISZERO(fp)) { 347 res[1] = 0; 348 return (sign); 349 } 350 351 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 352 fe->fe_fpsr |= FPSR_UNFL; 353 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 354 if (fpu_round(fe, fp) && fp->fp_mant[1] == DBL_EXP(1)) { 355 res[1] = 0; 356 return (sign | DBL_EXP(1) | 0); 357 } 358 if (fe->fe_fpsr & FPSR_INEX2) 359 fe->fe_fpsr |= FPSR_UNFL 360 /* mc68881/2 don't underflow when converting */; 361 exp = 0; 362 goto done; 363 } 364 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 365 if (fpu_round(fe, fp) && fp->fp_mant[1] == DBL_EXP(2)) 366 exp++; 367 if (exp >= DBL_EXP_INFNAN) { 368 fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2 | FPSR_OVFL; 369 if (toinf(fe, sign)) { 370 res[1] = 0; 371 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 372 } 373 res[1] = ~0; 374 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 375 } 376 done: 377 res[1] = fp->fp_mant[2]; 378 return (sign | DBL_EXP(exp) | (fp->fp_mant[1] & DBL_MASK)); 379 } 380 381 /* 382 * fpn -> 68k extended (32 bit high-order result returned; two 32-bit low 383 * order result left in res[1] & res[2]). Assumes == 64 bits in extended 384 * precision fraction. 385 * 386 * This code mimics fpu_ftos; see it for comments. 387 */ 388 static u_int 389 fpu_ftox(fe, fp, res) 390 struct fpemu *fe; 391 register struct fpn *fp; 392 u_int *res; 393 { 394 register u_int sign = fp->fp_sign << 31; 395 register int exp; 396 397 #define EXT_EXP(e) ((e) << 16) 398 /* 399 * on m68k extended prec, significand does not share the same long 400 * word with exponent 401 */ 402 #define EXT_MASK 0 403 #define EXT_EXPLICIT1 (1UL << (63 & 31)) 404 #define EXT_EXPLICIT2 (1UL << (64 & 31)) 405 406 if (ISNAN(fp)) { 407 (void) fpu_shr(fp, FP_NMANT - EXT_FRACBITS); 408 exp = EXT_EXP_INFNAN; 409 goto done; 410 } 411 if (ISINF(fp)) { 412 sign |= EXT_EXP(EXT_EXP_INFNAN); 413 res[1] = res[2] = 0; 414 return (sign); 415 } 416 if (ISZERO(fp)) { 417 res[1] = res[2] = 0; 418 return (sign); 419 } 420 421 if ((exp = fp->fp_exp + EXT_EXP_BIAS) < 0) { 422 fe->fe_fpsr |= FPSR_UNFL; 423 /* I'm not sure about this <=... exp==0 doesn't mean 424 it's a denormal in extended format */ 425 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 426 if (fpu_round(fe, fp) && fp->fp_mant[1] == EXT_EXPLICIT1) { 427 res[1] = res[2] = 0; 428 return (sign | EXT_EXP(1) | 0); 429 } 430 if (fe->fe_fpsr & FPSR_INEX2) 431 fe->fe_fpsr |= FPSR_UNFL 432 /* mc68881/2 don't underflow */; 433 exp = 0; 434 goto done; 435 } 436 #if (FP_NMANT - FP_NG - EXT_FRACBITS) > 0 437 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS); 438 #endif 439 if (fpu_round(fe, fp) && fp->fp_mant[0] == EXT_EXPLICIT2) 440 exp++; 441 if (exp >= EXT_EXP_INFNAN) { 442 fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2 | FPSR_OVFL; 443 if (toinf(fe, sign)) { 444 res[1] = res[2] = 0; 445 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 446 } 447 res[1] = res[2] = ~0; 448 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 449 } 450 done: 451 res[1] = fp->fp_mant[1]; 452 res[2] = fp->fp_mant[2]; 453 return (sign | EXT_EXP(exp)); 454 } 455 456 /* 457 * Implode an fpn, writing the result into the given space. 458 */ 459 void 460 fpu_implode(fe, fp, type, space) 461 struct fpemu *fe; 462 register struct fpn *fp; 463 int type; 464 register u_int *space; 465 { 466 /* XXX Dont delete exceptions set here: fe->fe_fpsr &= ~FPSR_EXCP; */ 467 468 switch (type) { 469 case FTYPE_LNG: 470 space[0] = fpu_ftoi(fe, fp); 471 break; 472 473 case FTYPE_SNG: 474 space[0] = fpu_ftos(fe, fp); 475 break; 476 477 case FTYPE_DBL: 478 space[0] = fpu_ftod(fe, fp, space); 479 break; 480 481 case FTYPE_EXT: 482 /* funky rounding precision options ?? */ 483 space[0] = fpu_ftox(fe, fp, space); 484 break; 485 486 default: 487 panic("fpu_implode"); 488 } 489 } 490