1 /* $NetBSD: fpu_subr.c,v 1.3 1999/05/30 20:17:49 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_subr.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 54 #include <machine/reg.h> 55 56 #include "fpu_emulate.h" 57 #include "fpu_arith.h" 58 59 /* 60 * Shift the given number right rsh bits. Any bits that `fall off' will get 61 * shoved into the sticky field; we return the resulting sticky. Note that 62 * shifting NaNs is legal (this will never shift all bits out); a NaN's 63 * sticky field is ignored anyway. 64 */ 65 int 66 fpu_shr(register struct fpn *fp, register int rsh) 67 { 68 register u_int m0, m1, m2, s; 69 register int lsh; 70 71 #ifdef DIAGNOSTIC 72 if (rsh < 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp))) 73 panic("fpu_rightshift 1"); 74 #endif 75 76 m0 = fp->fp_mant[0]; 77 m1 = fp->fp_mant[1]; 78 m2 = fp->fp_mant[2]; 79 80 /* If shifting all the bits out, take a shortcut. */ 81 if (rsh >= FP_NMANT) { 82 #ifdef DIAGNOSTIC 83 if ((m0 | m1 | m2) == 0) 84 panic("fpu_rightshift 2"); 85 #endif 86 fp->fp_mant[0] = 0; 87 fp->fp_mant[1] = 0; 88 fp->fp_mant[2] = 0; 89 #ifdef notdef 90 if ((m0 | m1 | m2) == 0) 91 fp->fp_class = FPC_ZERO; 92 else 93 #endif 94 fp->fp_sticky = 1; 95 return (1); 96 } 97 98 /* Squish out full words. */ 99 s = fp->fp_sticky; 100 if (rsh >= 32 * 2) { 101 s |= m2 | m1; 102 m2 = m0, m1 = 0, m0 = 0; 103 } else if (rsh >= 32) { 104 s |= m2; 105 m2 = m1, m1 = m0, m0 = 0; 106 } 107 108 /* Handle any remaining partial word. */ 109 if ((rsh &= 31) != 0) { 110 lsh = 32 - rsh; 111 s |= m2 << lsh; 112 m2 = (m2 >> rsh) | (m1 << lsh); 113 m1 = (m1 >> rsh) | (m0 << lsh); 114 m0 >>= rsh; 115 } 116 fp->fp_mant[0] = m0; 117 fp->fp_mant[1] = m1; 118 fp->fp_mant[2] = m2; 119 fp->fp_sticky = s; 120 return (s); 121 } 122 123 /* 124 * Force a number to be normal, i.e., make its fraction have all zero 125 * bits before FP_1, then FP_1, then all 1 bits. This is used for denorms 126 * and (sometimes) for intermediate results. 127 * 128 * Internally, this may use a `supernormal' -- a number whose fp_mant 129 * is greater than or equal to 2.0 -- so as a side effect you can hand it 130 * a supernormal and it will fix it (provided fp->fp_mant[2] == 0). 131 */ 132 void 133 fpu_norm(register struct fpn *fp) 134 { 135 register u_int m0, m1, m2, sup, nrm; 136 register int lsh, rsh, exp; 137 138 exp = fp->fp_exp; 139 m0 = fp->fp_mant[0]; 140 m1 = fp->fp_mant[1]; 141 m2 = fp->fp_mant[2]; 142 143 /* Handle severe subnormals with 32-bit moves. */ 144 if (m0 == 0) { 145 if (m1) { 146 m0 = m1; 147 m1 = m2; 148 m2 = 0; 149 exp -= 32; 150 } else if (m2) { 151 m0 = m2; 152 m1 = 0; 153 m2 = 0; 154 exp -= 2 * 32; 155 } else { 156 fp->fp_class = FPC_ZERO; 157 return; 158 } 159 } 160 161 /* Now fix any supernormal or remaining subnormal. */ 162 nrm = FP_1; 163 sup = nrm << 1; 164 if (m0 >= sup) { 165 /* 166 * We have a supernormal number. We need to shift it right. 167 * We may assume m2==0. 168 */ 169 asm volatile("bfffo %1{#0:#32},%0" : "=d"(rsh) : "g"(m0)); 170 rsh = 31 - rsh - FP_LG; 171 exp += rsh; 172 lsh = 32 - rsh; 173 m2 = m1 << lsh; 174 m1 = (m1 >> rsh) | (m0 << lsh); 175 m0 = (m0 >> rsh); 176 } else if (m0 < nrm) { 177 /* 178 * We have a regular denorm (a subnormal number), and need 179 * to shift it left. 180 */ 181 asm volatile("bfffo %1{#0:#32},%0" : "=d"(lsh) : "g"(m0)); 182 lsh = FP_LG - 31 + lsh; 183 exp -= lsh; 184 rsh = 32 - lsh; 185 m0 = (m0 << lsh) | (m1 >> rsh); 186 m1 = (m1 << lsh) | (m2 >> rsh); 187 m2 <<= lsh; 188 } 189 190 fp->fp_exp = exp; 191 fp->fp_mant[0] = m0; 192 fp->fp_mant[1] = m1; 193 fp->fp_mant[2] = m2; 194 } 195 196 /* 197 * Concoct a `fresh' Quiet NaN per Appendix N. 198 * As a side effect, we set OPERR for the current exceptions. 199 */ 200 struct fpn * 201 fpu_newnan(register struct fpemu *fe) 202 { 203 register struct fpn *fp; 204 205 fe->fe_fpsr |= FPSR_OPERR; 206 fp = &fe->fe_f3; 207 fp->fp_class = FPC_QNAN; 208 fp->fp_sign = 0; 209 fp->fp_mant[0] = FP_1 - 1; 210 fp->fp_mant[1] = fp->fp_mant[2] = ~0; 211 return (fp); 212 } 213