1* $NetBSD: x_ovfl.sa,v 1.3 2001/09/16 16:34:32 wiz Exp $ 2 3* MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP 4* M68000 Hi-Performance Microprocessor Division 5* M68040 Software Package 6* 7* M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc. 8* All rights reserved. 9* 10* THE SOFTWARE is provided on an "AS IS" basis and without warranty. 11* To the maximum extent permitted by applicable law, 12* MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, 13* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A 14* PARTICULAR PURPOSE and any warranty against infringement with 15* regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) 16* and any accompanying written materials. 17* 18* To the maximum extent permitted by applicable law, 19* IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER 20* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS 21* PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR 22* OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE 23* SOFTWARE. Motorola assumes no responsibility for the maintenance 24* and support of the SOFTWARE. 25* 26* You are hereby granted a copyright license to use, modify, and 27* distribute the SOFTWARE so long as this entire notice is retained 28* without alteration in any modified and/or redistributed versions, 29* and that such modified versions are clearly identified as such. 30* No licenses are granted by implication, estoppel or otherwise 31* under any patents or trademarks of Motorola, Inc. 32 33* 34* x_ovfl.sa 3.5 7/1/91 35* 36* fpsp_ovfl --- FPSP handler for overflow exception 37* 38* Overflow occurs when a floating-point intermediate result is 39* too large to be represented in a floating-point data register, 40* or when storing to memory, the contents of a floating-point 41* data register are too large to be represented in the 42* destination format. 43* 44* Trap disabled results 45* 46* If the instruction is move_out, then garbage is stored in the 47* destination. If the instruction is not move_out, then the 48* destination is not affected. For 68881 compatibility, the 49* following values should be stored at the destination, based 50* on the current rounding mode: 51* 52* RN Infinity with the sign of the intermediate result. 53* RZ Largest magnitude number, with the sign of the 54* intermediate result. 55* RM For pos overflow, the largest pos number. For neg overflow, 56* -infinity 57* RP For pos overflow, +infinity. For neg overflow, the largest 58* neg number 59* 60* Trap enabled results 61* All trap disabled code applies. In addition the exceptional 62* operand needs to be made available to the users exception handler 63* with a bias of $6000 subtracted from the exponent. 64* 65 66X_OVFL IDNT 2,1 Motorola 040 Floating Point Software Package 67 68 section 8 69 70 include fpsp.h 71 72 xref ovf_r_x2 73 xref ovf_r_x3 74 xref store 75 xref real_ovfl 76 xref real_inex 77 xref fpsp_done 78 xref g_opcls 79 xref b1238_fix 80 81 xdef fpsp_ovfl 82fpsp_ovfl: 83 link a6,#-LOCAL_SIZE 84 fsave -(a7) 85 movem.l d0-d1/a0-a1,USER_DA(a6) 86 fmovem.x fp0-fp3,USER_FP0(a6) 87 fmovem.l fpcr/fpsr/fpiar,USER_FPCR(a6) 88 89* 90* The 040 doesn't set the AINEX bit in the FPSR, the following 91* line temporarily rectifies this error. 92* 93 bset.b #ainex_bit,FPSR_AEXCEPT(a6) 94* 95 bsr.l ovf_adj ;denormalize, round & store interm op 96* 97* if overflow traps not enabled check for inexact exception 98* 99 btst.b #ovfl_bit,FPCR_ENABLE(a6) 100 beq.b ck_inex 101* 102 btst.b #E3,E_BYTE(a6) 103 beq.b no_e3_1 104 bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no 105 bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit 106 bsr.l b1238_fix 107 move.l USER_FPSR(a6),FPSR_SHADOW(a6) 108 or.l #sx_mask,E_BYTE(a6) 109no_e3_1: 110 movem.l USER_DA(a6),d0-d1/a0-a1 111 fmovem.x USER_FP0(a6),fp0-fp3 112 fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 113 frestore (a7)+ 114 unlk a6 115 bra.l real_ovfl 116* 117* It is possible to have either inex2 or inex1 exceptions with the 118* ovfl. If the inex enable bit is set in the FPCR, and either 119* inex2 or inex1 occurred, we must clean up and branch to the 120* real inex handler. 121* 122ck_inex: 123* move.b FPCR_ENABLE(a6),d0 124* and.b FPSR_EXCEPT(a6),d0 125* andi.b #$3,d0 126 btst.b #inex2_bit,FPCR_ENABLE(a6) 127 beq.b ovfl_exit 128* 129* Inexact enabled and reported, and we must take an inexact exception. 130* 131take_inex: 132 btst.b #E3,E_BYTE(a6) 133 beq.b no_e3_2 134 bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no 135 bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit 136 bsr.l b1238_fix 137 move.l USER_FPSR(a6),FPSR_SHADOW(a6) 138 or.l #sx_mask,E_BYTE(a6) 139no_e3_2: 140 move.b #INEX_VEC,EXC_VEC+1(a6) 141 movem.l USER_DA(a6),d0-d1/a0-a1 142 fmovem.x USER_FP0(a6),fp0-fp3 143 fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 144 frestore (a7)+ 145 unlk a6 146 bra.l real_inex 147 148ovfl_exit: 149 bclr.b #E3,E_BYTE(a6) ;test and clear E3 bit 150 beq.b e1_set 151* 152* Clear dirty bit on dest resister in the frame before branching 153* to b1238_fix. 154* 155 bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no 156 bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit 157 bsr.l b1238_fix ;test for bug1238 case 158 159 move.l USER_FPSR(a6),FPSR_SHADOW(a6) 160 or.l #sx_mask,E_BYTE(a6) 161 movem.l USER_DA(a6),d0-d1/a0-a1 162 fmovem.x USER_FP0(a6),fp0-fp3 163 fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 164 frestore (a7)+ 165 unlk a6 166 bra.l fpsp_done 167e1_set: 168 movem.l USER_DA(a6),d0-d1/a0-a1 169 fmovem.x USER_FP0(a6),fp0-fp3 170 fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar 171 unlk a6 172 bra.l fpsp_done 173 174* 175* ovf_adj 176* 177ovf_adj: 178* 179* Have a0 point to the correct operand. 180* 181 btst.b #E3,E_BYTE(a6) ;test E3 bit 182 beq.b ovf_e1 183 184 lea WBTEMP(a6),a0 185 bra.b ovf_com 186ovf_e1: 187 lea ETEMP(a6),a0 188 189ovf_com: 190 bclr.b #sign_bit,LOCAL_EX(a0) 191 sne LOCAL_SGN(a0) 192 193 bsr.l g_opcls ;returns opclass in d0 194 cmpi.w #3,d0 ;check for opclass3 195 bne.b not_opc011 196 197* 198* FPSR_CC is saved and restored because ovf_r_x3 affects it. The 199* CCs are defined to be 'not affected' for the opclass3 instruction. 200* 201 move.b FPSR_CC(a6),L_SCR1(a6) 202 bsr.l ovf_r_x3 ;returns a0 pointing to result 203 move.b L_SCR1(a6),FPSR_CC(a6) 204 bra.l store ;stores to memory or register 205 206not_opc011: 207 bsr.l ovf_r_x2 ;returns a0 pointing to result 208 bra.l store ;stores to memory or register 209 210 end 211