1 /* $NetBSD: cacheops_30.h,v 1.6 2002/11/03 01:34:42 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Invalidate entire TLB. 41 */ 42 static __inline void __attribute__((__unused__)) 43 TBIA_30(void) 44 { 45 int tmp = DC_CLEAR; 46 47 __asm __volatile (" pflusha;" 48 " movc %0,%%cacr" : : "d" (tmp)); 49 } 50 51 /* 52 * Invalidate any TLB entry for given VA (TB Invalidate Single) 53 */ 54 static __inline void __attribute__((__unused__)) 55 TBIS_30(vaddr_t va) 56 { 57 __asm __volatile (" pflush #0,#0,%0@;" 58 " movc %1,%%cacr" : : "a" (va), "d" (DC_CLEAR)); 59 } 60 61 /* 62 * Invalidate supervisor side of TLB 63 */ 64 static __inline void __attribute__((__unused__)) 65 TBIAS_30(void) 66 { 67 __asm __volatile (" pflush #4,#4;" 68 " movc %0,%%cacr;" :: "d" (DC_CLEAR)); 69 } 70 71 /* 72 * Invalidate user side of TLB 73 */ 74 static __inline void __attribute__((__unused__)) 75 TBIAU_30(void) 76 { 77 __asm __volatile (" pflush #0,#4;" 78 " movc %0,%%cacr;" :: "d" (DC_CLEAR)); 79 } 80 81 /* 82 * Invalidate instruction cache 83 */ 84 static __inline void __attribute__((__unused__)) 85 ICIA_30(void) 86 { 87 __asm __volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR)); 88 } 89 90 static __inline void __attribute__((__unused__)) 91 ICPA_30(void) 92 { 93 __asm __volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR)); 94 } 95 96 /* 97 * Invalidate data cache. 98 * NOTE: we do not flush 68030/20 on-chip cache as there are no aliasing 99 * problems with DC_WA. The only cases we have to worry about are context 100 * switch and TLB changes, both of which are handled "in-line" in resume 101 * and TBI*. 102 */ 103 #define DCIA_30() 104 #define DCIS_30() 105 #define DCIU_30() 106 #define DCIAS_30(va) 107 #define DCFA_30() 108 #define DCPA_30() 109 110 static __inline void __attribute__((__unused__)) 111 PCIA_30(void) 112 { 113 __asm __volatile (" movc %0,%%cacr;" : : "d" (DC_CLEAR)); 114 } 115