1 /* $NetBSD: cacheops_40.h,v 1.5 1999/11/06 17:42:32 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Invalidate entire TLB. 41 */ 42 void TBIA_40 __P((void)); 43 extern __inline void 44 TBIA_40() 45 { 46 __asm __volatile (" .word 0xf518" ); /* pflusha */ 47 } 48 49 /* 50 * Invalidate any TLB entry for given VA (TB Invalidate Single) 51 */ 52 void TBIS_40 __P((vaddr_t)); 53 extern __inline void 54 TBIS_40(va) 55 vaddr_t va; 56 { 57 register vaddr_t r_va __asm("%a0") = va; 58 int tmp; 59 60 __asm __volatile (" movc %1, %%dfc;" /* select supervisor */ 61 " .word 0xf508;" /* pflush %a0@ */ 62 " moveq %3, %1;" /* select user */ 63 " movc %1, %%dfc;" 64 " .word 0xf508;" : "=d" (tmp) : 65 "0" (FC_SUPERD), "a" (r_va), "i" (FC_USERD)); 66 } 67 68 /* 69 * Invalidate supervisor side of TLB 70 */ 71 void TBIAS_40 __P((void)); 72 extern __inline void 73 TBIAS_40() 74 { 75 /* 76 * Cannot specify supervisor/user on pflusha, so we flush all 77 */ 78 __asm __volatile (" .word 0xf518;"); 79 } 80 81 /* 82 * Invalidate user side of TLB 83 */ 84 void TBIAU_40 __P((void)); 85 extern __inline void 86 TBIAU_40() 87 { 88 /* 89 * Cannot specify supervisor/user on pflusha, so we flush all 90 */ 91 __asm __volatile (" .word 0xf518;"); 92 } 93 94 /* 95 * Invalidate instruction cache 96 */ 97 void ICIA_40 __P((void)); 98 extern __inline void 99 ICIA_40() 100 { 101 __asm __volatile (" .word 0xf498;"); /* cinva ic */ 102 } 103 104 void ICPA_40 __P((void)); 105 extern __inline void 106 ICPA_40() 107 { 108 __asm __volatile (" .word 0xf498;"); /* cinva ic */ 109 } 110 111 /* 112 * Invalidate data cache. 113 */ 114 void DCIA_40 __P((void)); 115 extern __inline void 116 DCIA_40() 117 { 118 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 119 } 120 121 void DCIS_40 __P((void)); 122 extern __inline void 123 DCIS_40() 124 { 125 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 126 } 127 128 void DCIU_40 __P((void)); 129 extern __inline void 130 DCIU_40() 131 { 132 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 133 } 134 135 void DCIAS_40 __P((paddr_t)); 136 extern __inline void 137 DCIAS_40(pa) 138 paddr_t pa; 139 { 140 register paddr_t r_pa __asm("%a0") = pa; 141 142 __asm __volatile (" .word 0xf468;" : : "a" (r_pa)); /* cpushl dc,%a0@ */ 143 } 144 145 void PCIA_40 __P((void)); 146 extern __inline void 147 PCIA_40() 148 { 149 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 150 } 151 152 void DCFA_40 __P((void)); 153 extern __inline void 154 DCFA_40() 155 { 156 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 157 } 158 159 /* invalidate instruction physical cache line */ 160 void ICPL_40 __P((paddr_t)); 161 extern __inline void 162 ICPL_40(pa) 163 paddr_t pa; 164 { 165 register paddr_t r_pa __asm("%a0") = pa; 166 167 __asm __volatile (" .word 0xf488;" : : "a" (r_pa)); /* cinvl ic,%a0@ */ 168 } 169 170 /* invalidate instruction physical cache page */ 171 void ICPP_40 __P((paddr_t)); 172 extern __inline void 173 ICPP_40(pa) 174 paddr_t pa; 175 { 176 register paddr_t r_pa __asm("%a0") = pa; 177 178 __asm __volatile (" .word 0xf490;" : : "a" (r_pa)); /* cinvp ic,%a0@ */ 179 } 180 181 /* invalidate data physical cache line */ 182 void DCPL_40 __P((paddr_t)); 183 extern __inline void 184 DCPL_40(pa) 185 paddr_t pa; 186 { 187 register paddr_t r_pa __asm("%a0") = pa; 188 189 __asm __volatile (" .word 0xf448;" : : "a" (r_pa)); /* cinvl dc,%a0@ */ 190 } 191 192 /* invalidate data physical cache page */ 193 void DCPP_40 __P((paddr_t)); 194 extern __inline void 195 DCPP_40(pa) 196 paddr_t pa; 197 { 198 register paddr_t r_pa __asm("%a0") = pa; 199 200 __asm __volatile (" .word 0xf450;" : : "a" (r_pa)); /* cinvp dc,%a0@ */ 201 } 202 203 /* invalidate data physical all */ 204 void DCPA_40 __P((void)); 205 extern __inline void 206 DCPA_40() 207 { 208 __asm __volatile (" .word 0xf458;"); /* cinva dc */ 209 } 210 211 /* data cache flush line */ 212 void DCFL_40 __P((paddr_t)); 213 extern __inline void 214 DCFL_40(pa) 215 paddr_t pa; 216 { 217 register paddr_t r_pa __asm("%a0") = pa; 218 219 __asm __volatile (" .word 0xf468;" : : "a" (r_pa)); /* cpushl dc,%a0@ */ 220 } 221 222 /* data cache flush page */ 223 void DCFP_40 __P((paddr_t)); 224 extern __inline void 225 DCFP_40(pa) 226 paddr_t pa; 227 { 228 register paddr_t r_pa __asm("%a0") = pa; 229 230 __asm __volatile (" .word 0xf470;" : : "a" (r_pa)); /* cpushp dc,%a0@ */ 231 } 232