1 /* $NetBSD: cacheops_60.h,v 1.4 1999/11/06 17:42:33 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Invalidate entire TLB. 41 */ 42 void TBIA_60 __P((void)); 43 extern __inline void 44 TBIA_60() 45 { 46 __asm __volatile (" .word 0xf518" ); /* pflusha */ 47 } 48 49 /* 50 * Invalidate any TLB entry for given VA (TB Invalidate Single) 51 */ 52 void TBIS_60 __P((vaddr_t)); 53 extern __inline void 54 TBIS_60(va) 55 vaddr_t va; 56 { 57 register vaddr_t r_va __asm("%a0") = va; 58 int tmp; 59 60 __asm __volatile (" movc %1, %%dfc;" /* select supervisor */ 61 " .word 0xf508;" /* pflush %a0@ */ 62 " moveq %3, %1;" /* select user */ 63 " movc %1, %%dfc;" 64 " .word 0xf508;" /* pflush %a0@ */ 65 " movc %%cacr,%1;" 66 " orl %4,%1;" 67 " movc %1,%%cacr" : "=d" (tmp) : 68 "0" (FC_SUPERD), "a" (r_va), "i" (FC_USERD), 69 "i" (IC60_CABC)); 70 } 71 72 /* 73 * Invalidate supervisor side of TLB 74 */ 75 void TBIAS_60 __P((void)); 76 extern __inline void 77 TBIAS_60() 78 { 79 int tmp; 80 /* 81 * Cannot specify supervisor/user on pflusha, so we flush all 82 */ 83 __asm __volatile (" .word 0xf518;" 84 " movc %%cacr,%0;" 85 " orl %1,%0;" 86 " movc %0,%%cacr" /* clear all branch cache 87 entries */ 88 : "=d" (tmp) : "i" (IC60_CABC) ); 89 } 90 91 /* 92 * Invalidate user side of TLB 93 */ 94 void TBIAU_60 __P((void)); 95 extern __inline void 96 TBIAU_60() 97 { 98 int tmp; 99 /* 100 * Cannot specify supervisor/user on pflusha, so we flush all 101 */ 102 __asm __volatile (" .word 0xf518;" 103 " movc %%cacr,%0;" 104 " orl %1,%0;" 105 " movc %0,%%cacr" /* clear all branch cache 106 entries */ 107 : "=d" (tmp) : "i" (IC60_CUBC) ); 108 } 109 110 /* 111 * Invalidate instruction cache 112 */ 113 void ICIA_60 __P((void)); 114 extern __inline void 115 ICIA_60() 116 { 117 /* inva ic (also clears branch cache) */ 118 __asm __volatile (" .word 0xf498;"); 119 } 120 121 void ICPA_60 __P((void)); 122 extern __inline void 123 ICPA_60() 124 { 125 /* inva ic (also clears branch cache) */ 126 __asm __volatile (" .word 0xf498;"); 127 } 128 129 /* 130 * Invalidate data cache. 131 */ 132 void DCIA_60 __P((void)); 133 extern __inline void 134 DCIA_60() 135 { 136 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 137 } 138 139 void DCIS_60 __P((void)); 140 extern __inline void 141 DCIS_60() 142 { 143 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 144 } 145 146 void DCIU_60 __P((void)); 147 extern __inline void 148 DCIU_60() 149 { 150 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 151 } 152 153 void DCIAS_60 __P((paddr_t)); 154 extern __inline void 155 DCIAS_60(pa) 156 paddr_t pa; 157 { 158 register paddr_t r_pa __asm("%a0") = pa; 159 160 __asm __volatile (" .word 0xf468;" : : "a" (r_pa)); /* cpushl dc,%a0@ */ 161 } 162 163 void PCIA_60 __P((void)); 164 extern __inline void 165 PCIA_60() 166 { 167 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 168 } 169 170 void DCFA_60 __P((void)); 171 extern __inline void 172 DCFA_60() 173 { 174 __asm __volatile (" .word 0xf478;"); /* cpusha dc */ 175 } 176 177 /* invalidate instruction physical cache line */ 178 void ICPL_60 __P((paddr_t)); 179 extern __inline void 180 ICPL_60(pa) 181 paddr_t pa; 182 { 183 register paddr_t r_pa __asm("%a0") = pa; 184 185 __asm __volatile (" .word 0xf488;" : : "a" (r_pa)); /* cinvl ic,%a0@ */ 186 } 187 188 /* invalidate instruction physical cache page */ 189 void ICPP_60 __P((paddr_t)); 190 extern __inline void 191 ICPP_60(pa) 192 paddr_t pa; 193 { 194 register paddr_t r_pa __asm("%a0") = pa; 195 196 __asm __volatile (" .word 0xf490;" : : "a" (r_pa)); /* cinvp ic,%a0@ */ 197 } 198 199 /* invalidate data physical cache line */ 200 void DCPL_60 __P((paddr_t)); 201 extern __inline void 202 DCPL_60(pa) 203 paddr_t pa; 204 { 205 register paddr_t r_pa __asm("%a0") = pa; 206 207 __asm __volatile (" .word 0xf448;" : : "a" (r_pa)); /* cinvl dc,%a0@ */ 208 } 209 210 /* invalidate data physical cache page */ 211 void DCPP_60 __P((paddr_t)); 212 extern __inline void 213 DCPP_60(pa) 214 paddr_t pa; 215 { 216 register paddr_t r_pa __asm("%a0") = pa; 217 218 __asm __volatile (" .word 0xf450;" : : "a" (r_pa)); /* cinvp dc,%a0@ */ 219 } 220 221 /* invalidate data physical all */ 222 void DCPA_60 __P((void)); 223 extern __inline void 224 DCPA_60() 225 { 226 __asm __volatile (" .word 0xf458;"); /* cinva dc */ 227 } 228 229 /* data cache flush line */ 230 void DCFL_60 __P((paddr_t)); 231 extern __inline void 232 DCFL_60(pa) 233 paddr_t pa; 234 { 235 register paddr_t r_pa __asm("%a0") = pa; 236 237 __asm __volatile (" .word 0xf468;" : : "a" (r_pa)); /* cpushl dc,%a0@ */ 238 } 239 240 /* data cache flush page */ 241 void DCFP_60 __P((paddr_t)); 242 extern __inline void 243 DCFP_60(pa) 244 paddr_t pa; 245 { 246 register paddr_t r_pa __asm("%a0") = pa; 247 248 __asm __volatile (" .word 0xf470;" : : "a" (r_pa)); /* cpushp dc,%a0@ */ 249 } 250