1 /* $NetBSD: cpu.h,v 1.7 2001/06/14 22:56:57 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 #ifndef _M68K_CPU_H_ 46 #define _M68K_CPU_H_ 47 48 /* 49 * Exported definitions common to Motorola m68k-based ports. 50 * 51 * Note that are some port-specific definitions here, such as 52 * HP and Sun MMU types. These facilitate adding very small 53 * amounts of port-specific code to what would otherwise be 54 * identical. The is especially true in the case of the HP 55 * and other m68k pmaps. 56 * 57 * Individual ports are expected to define the following CPP symbols 58 * in <machine/cpu.h> to enable conditional code: 59 * 60 * M68K_MMU_MOTOROLA Machine has a Motorola MMU (incl. 61 * 68851, 68030, 68040, 68060) 62 * 63 * M68K_MMU_HP Machine has an HP MMU. 64 * 65 * Note also that while m68k-generic code conditionalizes on the 66 * M68K_MMU_HP CPP symbol, none of the HP MMU defintions are in this 67 * file (since none are used in otherwise sharable code). 68 */ 69 70 /* 71 * XXX The remaining contents of this file should be split out 72 * XXX into separate files (like m68k.h) and then this file 73 * XXX should go away. Furthermore, most of the stuff defined 74 * XXX here does NOT belong in <machine/cpu.h>, and the ports 75 * XXX using this file should remove <m68k/cpu.h> from there. 76 */ 77 78 #include <m68k/m68k.h> 79 80 /* XXX - Move this stuff into <m68k/mmu030.h> maybe? */ 81 82 /* 83 * 68851 and 68030 MMU 84 */ 85 #define PMMU_LVLMASK 0x0007 86 #define PMMU_INV 0x0400 87 #define PMMU_WP 0x0800 88 #define PMMU_ALV 0x1000 89 #define PMMU_SO 0x2000 90 #define PMMU_LV 0x4000 91 #define PMMU_BE 0x8000 92 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 93 94 /* XXX - Move this stuff into <m68k/mmu040.h> maybe? */ 95 96 /* 97 * 68040 MMU 98 */ 99 #define MMU40_RES 0x001 100 #define MMU40_TTR 0x002 101 #define MMU40_WP 0x004 102 #define MMU40_MOD 0x010 103 #define MMU40_CMMASK 0x060 104 #define MMU40_SUP 0x080 105 #define MMU40_U0 0x100 106 #define MMU40_U1 0x200 107 #define MMU40_GLB 0x400 108 #define MMU40_BE 0x800 109 110 /* XXX - Move this stuff into <m68k/fcode.h> maybe? */ 111 112 /* 680X0 function codes */ 113 #define FC_USERD 1 /* user data space */ 114 #define FC_USERP 2 /* user program space */ 115 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 116 #define FC_SUPERD 5 /* supervisor data space */ 117 #define FC_SUPERP 6 /* supervisor program space */ 118 #define FC_CPU 7 /* CPU space */ 119 120 /* XXX - Move this stuff into <m68k/cacr.h> maybe? */ 121 122 /* fields in the 68020 cache control register */ 123 #define IC_ENABLE 0x0001 /* enable instruction cache */ 124 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 125 #define IC_CE 0x0004 /* clear instruction cache entry */ 126 #define IC_CLR 0x0008 /* clear entire instruction cache */ 127 128 /* additional fields in the 68030 cache control register */ 129 #define IC_BE 0x0010 /* instruction burst enable */ 130 #define DC_ENABLE 0x0100 /* data cache enable */ 131 #define DC_FREEZE 0x0200 /* data cache freeze */ 132 #define DC_CE 0x0400 /* clear data cache entry */ 133 #define DC_CLR 0x0800 /* clear entire data cache */ 134 #define DC_BE 0x1000 /* data burst enable */ 135 #define DC_WA 0x2000 /* write allocate */ 136 137 /* fields in the 68040 cache control register */ 138 #define IC40_ENABLE 0x00008000 /* instruction cache enable bit */ 139 #define DC40_ENABLE 0x80000000 /* data cache enable bit */ 140 141 /* additional fields in the 68060 cache control register */ 142 #define DC60_NAD 0x40000000 /* no allocate mode, data cache */ 143 #define DC60_ESB 0x20000000 /* enable store buffer */ 144 #define DC60_DPI 0x10000000 /* disable CPUSH invalidation */ 145 #define DC60_FOC 0x08000000 /* four kB data cache mode (else 8) */ 146 147 #define IC60_EBC 0x00800000 /* enable branch cache */ 148 #define IC60_CABC 0x00400000 /* clear all branch cache entries */ 149 #define IC60_CUBC 0x00200000 /* clear user branch cache entries */ 150 151 #define IC60_NAI 0x00004000 /* no allocate mode, instr. cache */ 152 #define IC60_FIC 0x00002000 /* four kB instr. cache (else 8) */ 153 154 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 155 #define CACHE_OFF (DC_CLR|IC_CLR) 156 #define CACHE_CLR (CACHE_ON) 157 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 158 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 159 160 #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE) 161 #define CACHE40_OFF (0x00000000) 162 163 #define CACHE60_ON (CACHE40_ON|IC60_CABC|IC60_EBC|DC60_ESB) 164 #define CACHE60_OFF (CACHE40_OFF|IC60_CABC) 165 166 #ifdef _KERNEL 167 /* 168 * From m68k/syscall.c 169 */ 170 /* extern void syscall(register_t, struct frame); Only called from locore.s */ 171 #endif /* _KERNEL */ 172 173 #endif /* _M68K_CPU_H_ */ 174