1 /* $NetBSD: cacheops.c,v 1.6 2000/04/15 20:31:27 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 #include <sys/types.h> 41 #include <machine/cpu.h> 42 #include <m68k/cpu.h> 43 #include <m68k/cacheops.h> 44 45 #if defined(_MULTI_CPU) 46 47 void _TBIA() 48 { 49 switch (cputype) { 50 default: 51 #ifdef M68020 52 case CPU_68020: 53 TBIA_20(); 54 break; 55 #endif 56 #ifdef M68030 57 case CPU_68030: 58 TBIA_30(); 59 break; 60 #endif 61 #ifdef M68040 62 case CPU_68040: 63 TBIA_40(); 64 break; 65 #endif 66 #ifdef M68060 67 case CPU_68060: 68 TBIA_60(); 69 break; 70 #endif 71 } 72 } 73 74 void _TBIAS() 75 { 76 switch (cputype) { 77 default: 78 #ifdef M68020 79 case CPU_68020: 80 TBIAS_20(); 81 break; 82 #endif 83 #ifdef M68030 84 case CPU_68030: 85 TBIAS_30(); 86 break; 87 #endif 88 #ifdef M68040 89 case CPU_68040: 90 TBIAS_40(); 91 break; 92 #endif 93 #ifdef M68060 94 case CPU_68060: 95 TBIAS_60(); 96 break; 97 #endif 98 } 99 } 100 101 void _TBIAU() 102 { 103 switch (cputype) { 104 default: 105 #ifdef M68020 106 case CPU_68020: 107 TBIAU_20(); 108 break; 109 #endif 110 #ifdef M68030 111 case CPU_68030: 112 TBIAU_30(); 113 break; 114 #endif 115 #ifdef M68040 116 case CPU_68040: 117 TBIAU_40(); 118 break; 119 #endif 120 #ifdef M68060 121 case CPU_68060: 122 TBIAU_60(); 123 break; 124 #endif 125 } 126 } 127 128 void _ICIA() 129 { 130 switch (cputype) { 131 default: 132 #ifdef M68020 133 case CPU_68020: 134 ICIA_20(); 135 break; 136 #endif 137 #ifdef M68030 138 case CPU_68030: 139 ICIA_30(); 140 break; 141 #endif 142 #ifdef M68040 143 case CPU_68040: 144 ICIA_40(); 145 break; 146 #endif 147 #ifdef M68060 148 case CPU_68060: 149 ICIA_60(); 150 break; 151 #endif 152 } 153 } 154 155 void _ICPA() 156 { 157 switch (cputype) { 158 default: 159 #ifdef M68020 160 case CPU_68020: 161 ICPA_20(); 162 break; 163 #endif 164 #ifdef M68030 165 case CPU_68030: 166 ICPA_30(); 167 break; 168 #endif 169 #ifdef M68040 170 case CPU_68040: 171 ICPA_40(); 172 break; 173 #endif 174 #ifdef M68060 175 case CPU_68060: 176 ICPA_60(); 177 break; 178 #endif 179 } 180 } 181 182 void _DCIA() 183 { 184 switch (cputype) { 185 default: 186 #ifdef M68020 187 case CPU_68020: 188 DCIA_20(); 189 break; 190 #endif 191 #ifdef M68030 192 case CPU_68030: 193 DCIA_30(); 194 break; 195 #endif 196 #ifdef M68040 197 case CPU_68040: 198 DCIA_40(); 199 break; 200 #endif 201 #ifdef M68060 202 case CPU_68060: 203 DCIA_60(); 204 break; 205 #endif 206 } 207 } 208 209 void _DCIS() 210 { 211 switch (cputype) { 212 default: 213 #ifdef M68020 214 case CPU_68020: 215 DCIS_20(); 216 break; 217 #endif 218 #ifdef M68030 219 case CPU_68030: 220 DCIS_30(); 221 break; 222 #endif 223 #ifdef M68040 224 case CPU_68040: 225 DCIS_40(); 226 break; 227 #endif 228 #ifdef M68060 229 case CPU_68060: 230 DCIS_60(); 231 break; 232 #endif 233 } 234 } 235 236 void _DCIU() 237 { 238 switch (cputype) { 239 default: 240 #ifdef M68020 241 case CPU_68020: 242 DCIU_20(); 243 break; 244 #endif 245 #ifdef M68030 246 case CPU_68030: 247 DCIU_30(); 248 break; 249 #endif 250 #ifdef M68040 251 case CPU_68040: 252 DCIU_40(); 253 break; 254 #endif 255 #ifdef M68060 256 case CPU_68060: 257 DCIU_60(); 258 break; 259 #endif 260 } 261 } 262 263 void _PCIA() 264 { 265 switch (cputype) { 266 default: 267 #ifdef M68020 268 case CPU_68020: 269 PCIA_20(); 270 break; 271 #endif 272 #ifdef M68030 273 case CPU_68030: 274 PCIA_30(); 275 break; 276 #endif 277 #ifdef M68040 278 case CPU_68040: 279 PCIA_40(); 280 break; 281 #endif 282 #ifdef M68060 283 case CPU_68060: 284 PCIA_60(); 285 break; 286 #endif 287 } 288 } 289 290 #if defined(M68040) || defined(M68060) 291 void _DCFA() 292 { 293 switch (cputype) { 294 #ifdef M68040 295 case CPU_68040: 296 DCFA_40(); 297 break; 298 #endif 299 #ifdef M68060 300 case CPU_68060: 301 DCFA_60(); 302 break; 303 #endif 304 } 305 } 306 #endif /* M68040 || M68060 */ 307 308 void _TBIS(va) 309 vaddr_t va; 310 { 311 switch (cputype) { 312 default: 313 #ifdef M68020 314 case CPU_68020: 315 TBIS_20(va); 316 break; 317 #endif 318 #ifdef M68030 319 case CPU_68030: 320 TBIS_30(va); 321 break; 322 #endif 323 #ifdef M68040 324 case CPU_68040: 325 TBIS_40(va); 326 break; 327 #endif 328 #ifdef M68060 329 case CPU_68060: 330 TBIS_60(va); 331 break; 332 #endif 333 } 334 } 335 336 void _DCIAS(pa) 337 paddr_t pa; 338 { 339 switch (cputype) { 340 default: 341 #ifdef M68020 342 case CPU_68020: 343 DCIAS_20(pa); 344 break; 345 #endif 346 #ifdef M68030 347 case CPU_68030: 348 DCIAS_30(pa); 349 break; 350 #endif 351 #ifdef M68040 352 case CPU_68040: 353 DCIAS_40(pa); 354 break; 355 #endif 356 #ifdef M68060 357 case CPU_68060: 358 DCIAS_60(pa); 359 break; 360 #endif 361 } 362 } 363 364 #if defined(M68040) || defined(M68060) 365 void _DCPA() 366 { 367 switch (cputype) { 368 default: 369 #ifdef M68040 370 case CPU_68040: 371 DCPA_40(); 372 break; 373 #endif 374 #ifdef M68060 375 case CPU_68060: 376 DCPA_60(); 377 break; 378 #endif 379 } 380 } 381 382 void _ICPL(pa) 383 paddr_t pa; 384 { 385 switch (cputype) { 386 default: 387 #ifdef M68040 388 case CPU_68040: 389 ICPL_40(pa); 390 break; 391 #endif 392 #ifdef M68060 393 case CPU_68060: 394 ICPL_60(pa); 395 break; 396 #endif 397 } 398 } 399 400 void _ICPP(pa) 401 paddr_t pa; 402 { 403 switch (cputype) { 404 default: 405 #ifdef M68040 406 case CPU_68040: 407 ICPP_40(pa); 408 break; 409 #endif 410 #ifdef M68060 411 case CPU_68060: 412 ICPP_60(pa); 413 break; 414 #endif 415 } 416 } 417 418 void _DCPL(pa) 419 paddr_t pa; 420 { 421 switch (cputype) { 422 default: 423 #ifdef M68040 424 case CPU_68040: 425 DCPL_40(pa); 426 break; 427 #endif 428 #ifdef M68060 429 case CPU_68060: 430 DCPL_60(pa); 431 break; 432 #endif 433 } 434 } 435 436 void _DCPP(pa) 437 paddr_t pa; 438 { 439 switch (cputype) { 440 default: 441 #ifdef M68040 442 case CPU_68040: 443 DCPP_40(pa); 444 break; 445 #endif 446 #ifdef M68060 447 case CPU_68060: 448 DCPP_60(pa); 449 break; 450 #endif 451 } 452 } 453 454 void _DCFL(pa) 455 paddr_t pa; 456 { 457 switch (cputype) { 458 default: 459 #ifdef M68040 460 case CPU_68040: 461 DCFL_40(pa); 462 break; 463 #endif 464 #ifdef M68060 465 case CPU_68060: 466 DCFL_60(pa); 467 break; 468 #endif 469 } 470 } 471 472 void _DCFP(pa) 473 paddr_t pa; 474 { 475 switch (cputype) { 476 default: 477 #ifdef M68040 478 case CPU_68040: 479 DCFP_40(pa); 480 break; 481 #endif 482 #ifdef M68060 483 case CPU_68060: 484 DCFP_60(pa); 485 break; 486 #endif 487 } 488 } 489 #endif /* M68040 || M68060 */ 490 491 #endif /* defined(_MULTI_CPU) */ 492