1 /* $NetBSD: pmap_motorola.c,v 1.60 2011/01/14 02:06:27 rmind Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991, 1993 34 * The Regents of the University of California. All rights reserved. 35 * 36 * This code is derived from software contributed to Berkeley by 37 * the Systems Programming Group of the University of Utah Computer 38 * Science Department. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * @(#)pmap.c 8.6 (Berkeley) 5/27/94 65 */ 66 67 /* 68 * Motorola m68k-family physical map management code. 69 * 70 * Supports: 71 * 68020 with 68851 MMU 72 * 68030 with on-chip MMU 73 * 68040 with on-chip MMU 74 * 68060 with on-chip MMU 75 * 76 * Notes: 77 * Don't even pay lip service to multiprocessor support. 78 * 79 * We assume TLB entries don't have process tags (except for the 80 * supervisor/user distinction) so we only invalidate TLB entries 81 * when changing mappings for the current (or kernel) pmap. This is 82 * technically not true for the 68851 but we flush the TLB on every 83 * context switch, so it effectively winds up that way. 84 * 85 * Bitwise and/or operations are significantly faster than bitfield 86 * references so we use them when accessing STE/PTEs in the pmap_pte_* 87 * macros. Note also that the two are not always equivalent; e.g.: 88 * (*pte & PG_PROT) [4] != pte->pg_prot [1] 89 * and a couple of routines that deal with protection and wiring take 90 * some shortcuts that assume the and/or definitions. 91 */ 92 93 /* 94 * Manages physical address maps. 95 * 96 * In addition to hardware address maps, this 97 * module is called upon to provide software-use-only 98 * maps which may or may not be stored in the same 99 * form as hardware maps. These pseudo-maps are 100 * used to store intermediate results from copy 101 * operations to and from address spaces. 102 * 103 * Since the information managed by this module is 104 * also stored by the logical address mapping module, 105 * this module may throw away valid virtual-to-physical 106 * mappings at almost any time. However, invalidations 107 * of virtual-to-physical mappings must be done as 108 * requested. 109 * 110 * In order to cope with hardware architectures which 111 * make virtual-to-physical map invalidates expensive, 112 * this module may delay invalidate or reduced protection 113 * operations until such time as they are actually 114 * necessary. This module is given full information as 115 * to which processors are currently using which maps, 116 * and to when physical maps must be made correct. 117 */ 118 119 #include "opt_m68k_arch.h" 120 121 #include <sys/cdefs.h> 122 __KERNEL_RCSID(0, "$NetBSD: pmap_motorola.c,v 1.60 2011/01/14 02:06:27 rmind Exp $"); 123 124 #include <sys/param.h> 125 #include <sys/systm.h> 126 #include <sys/proc.h> 127 #include <sys/malloc.h> 128 #include <sys/pool.h> 129 #include <sys/cpu.h> 130 131 #include <machine/pte.h> 132 #include <machine/pcb.h> 133 134 #include <uvm/uvm.h> 135 136 #include <m68k/cacheops.h> 137 138 #ifdef DEBUG 139 #define PDB_FOLLOW 0x0001 140 #define PDB_INIT 0x0002 141 #define PDB_ENTER 0x0004 142 #define PDB_REMOVE 0x0008 143 #define PDB_CREATE 0x0010 144 #define PDB_PTPAGE 0x0020 145 #define PDB_CACHE 0x0040 146 #define PDB_BITS 0x0080 147 #define PDB_COLLECT 0x0100 148 #define PDB_PROTECT 0x0200 149 #define PDB_SEGTAB 0x0400 150 #define PDB_MULTIMAP 0x0800 151 #define PDB_PARANOIA 0x2000 152 #define PDB_WIRING 0x4000 153 #define PDB_PVDUMP 0x8000 154 155 int debugmap = 0; 156 int pmapdebug = PDB_PARANOIA; 157 158 #define PMAP_DPRINTF(l, x) if (pmapdebug & (l)) printf x 159 #else /* ! DEBUG */ 160 #define PMAP_DPRINTF(l, x) /* nothing */ 161 #endif /* DEBUG */ 162 163 /* 164 * Get STEs and PTEs for user/kernel address space 165 */ 166 #if defined(M68040) || defined(M68060) 167 #define pmap_ste1(m, v) \ 168 (&((m)->pm_stab[(vaddr_t)(v) >> SG4_SHIFT1])) 169 /* XXX assumes physically contiguous ST pages (if more than one) */ 170 #define pmap_ste2(m, v) \ 171 (&((m)->pm_stab[(st_entry_t *)(*(u_int *)pmap_ste1(m, v) & SG4_ADDR1) \ 172 - (m)->pm_stpa + (((v) & SG4_MASK2) >> SG4_SHIFT2)])) 173 #if defined(M68020) || defined(M68030) 174 #define pmap_ste(m, v) \ 175 (&((m)->pm_stab[(vaddr_t)(v) \ 176 >> (mmutype == MMU_68040 ? SG4_SHIFT1 : SG_ISHIFT)])) 177 #define pmap_ste_v(m, v) \ 178 (mmutype == MMU_68040 \ 179 ? ((*pmap_ste1(m, v) & SG_V) && \ 180 (*pmap_ste2(m, v) & SG_V)) \ 181 : (*pmap_ste(m, v) & SG_V)) 182 #else 183 #define pmap_ste(m, v) \ 184 (&((m)->pm_stab[(vaddr_t)(v) >> SG4_SHIFT1])) 185 #define pmap_ste_v(m, v) \ 186 ((*pmap_ste1(m, v) & SG_V) && (*pmap_ste2(m, v) & SG_V)) 187 #endif 188 #else 189 #define pmap_ste(m, v) (&((m)->pm_stab[(vaddr_t)(v) >> SG_ISHIFT])) 190 #define pmap_ste_v(m, v) (*pmap_ste(m, v) & SG_V) 191 #endif 192 193 #define pmap_pte(m, v) (&((m)->pm_ptab[(vaddr_t)(v) >> PG_SHIFT])) 194 #define pmap_pte_pa(pte) (*(pte) & PG_FRAME) 195 #define pmap_pte_w(pte) (*(pte) & PG_W) 196 #define pmap_pte_ci(pte) (*(pte) & PG_CI) 197 #define pmap_pte_m(pte) (*(pte) & PG_M) 198 #define pmap_pte_u(pte) (*(pte) & PG_U) 199 #define pmap_pte_prot(pte) (*(pte) & PG_PROT) 200 #define pmap_pte_v(pte) (*(pte) & PG_V) 201 202 #define pmap_pte_set_w(pte, v) \ 203 if (v) *(pte) |= PG_W; else *(pte) &= ~PG_W 204 #define pmap_pte_set_prot(pte, v) \ 205 if (v) *(pte) |= PG_PROT; else *(pte) &= ~PG_PROT 206 #define pmap_pte_w_chg(pte, nw) ((nw) ^ pmap_pte_w(pte)) 207 #define pmap_pte_prot_chg(pte, np) ((np) ^ pmap_pte_prot(pte)) 208 209 /* 210 * Given a map and a machine independent protection code, 211 * convert to an m68k protection code. 212 */ 213 #define pte_prot(m, p) (protection_codes[p]) 214 u_int protection_codes[8]; 215 216 /* 217 * Kernel page table page management. 218 */ 219 struct kpt_page { 220 struct kpt_page *kpt_next; /* link on either used or free list */ 221 vaddr_t kpt_va; /* always valid kernel VA */ 222 paddr_t kpt_pa; /* PA of this page (for speed) */ 223 }; 224 struct kpt_page *kpt_free_list, *kpt_used_list; 225 struct kpt_page *kpt_pages; 226 227 /* 228 * Kernel segment/page table and page table map. 229 * The page table map gives us a level of indirection we need to dynamically 230 * expand the page table. It is essentially a copy of the segment table 231 * with PTEs instead of STEs. All are initialized in locore at boot time. 232 * Sysmap will initially contain VM_KERNEL_PT_PAGES pages of PTEs. 233 * Segtabzero is an empty segment table which all processes share til they 234 * reference something. 235 */ 236 paddr_t Sysseg_pa; 237 st_entry_t *Sysseg; 238 pt_entry_t *Sysmap, *Sysptmap; 239 st_entry_t *Segtabzero, *Segtabzeropa; 240 vsize_t Sysptsize = VM_KERNEL_PT_PAGES; 241 242 static struct pmap kernel_pmap_store; 243 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 244 struct vm_map *st_map, *pt_map; 245 struct vm_map_kernel st_map_store, pt_map_store; 246 247 vaddr_t lwp0uarea; /* lwp0 u-area VA, initialized in bootstrap */ 248 249 paddr_t avail_start; /* PA of first available physical page */ 250 paddr_t avail_end; /* PA of last available physical page */ 251 vsize_t mem_size; /* memory size in bytes */ 252 vaddr_t virtual_avail; /* VA of first avail page (after kernel bss)*/ 253 vaddr_t virtual_end; /* VA of last avail page (end of kernel AS) */ 254 int page_cnt; /* number of pages managed by VM system */ 255 256 bool pmap_initialized = false; /* Has pmap_init completed? */ 257 258 struct pv_header { 259 struct pv_entry pvh_first; /* first PV entry */ 260 uint16_t pvh_attrs; /* attributes: 261 bits 0-7: PTE bits 262 bits 8-15: flags */ 263 uint16_t pvh_cimappings; /* # caller-specified CI 264 mappings */ 265 }; 266 267 #define PVH_CI 0x10 /* all entries are cache-inhibited */ 268 #define PVH_PTPAGE 0x20 /* entry maps a page table page */ 269 270 struct pv_header *pv_table; 271 TAILQ_HEAD(pv_page_list, pv_page) pv_page_freelist; 272 int pv_nfree; 273 274 #ifdef CACHE_HAVE_VAC 275 u_int pmap_aliasmask; /* seperation at which VA aliasing ok */ 276 #endif 277 #if defined(M68040) || defined(M68060) 278 u_int protostfree; /* prototype (default) free ST map */ 279 #endif 280 281 pt_entry_t *caddr1_pte; /* PTE for CADDR1 */ 282 pt_entry_t *caddr2_pte; /* PTE for CADDR2 */ 283 284 struct pool pmap_pmap_pool; /* memory pool for pmap structures */ 285 286 struct pv_entry *pmap_alloc_pv(void); 287 void pmap_free_pv(struct pv_entry *); 288 289 #define PAGE_IS_MANAGED(pa) (pmap_initialized && uvm_pageismanaged(pa)) 290 291 static inline struct pv_header * 292 pa_to_pvh(paddr_t pa) 293 { 294 int bank, pg = 0; /* XXX gcc4 -Wuninitialized */ 295 296 bank = vm_physseg_find(atop((pa)), &pg); 297 return &VM_PHYSMEM_PTR(bank)->pmseg.pvheader[pg]; 298 } 299 300 /* 301 * Internal routines 302 */ 303 void pmap_remove_mapping(pmap_t, vaddr_t, pt_entry_t *, int); 304 bool pmap_testbit(paddr_t, int); 305 bool pmap_changebit(paddr_t, int, int); 306 int pmap_enter_ptpage(pmap_t, vaddr_t, bool); 307 void pmap_ptpage_addref(vaddr_t); 308 int pmap_ptpage_delref(vaddr_t); 309 void pmap_pinit(pmap_t); 310 void pmap_release(pmap_t); 311 312 #ifdef DEBUG 313 void pmap_pvdump(paddr_t); 314 void pmap_check_wiring(const char *, vaddr_t); 315 #endif 316 317 /* pmap_remove_mapping flags */ 318 #define PRM_TFLUSH 0x01 319 #define PRM_CFLUSH 0x02 320 #define PRM_KEEPPTPAGE 0x04 321 322 /* 323 * pmap_bootstrap_finalize: [ INTERFACE ] 324 * 325 * Initialize lwp0 uarea, curlwp, and curpcb after MMU is turned on, 326 * using lwp0uarea variable saved during pmap_bootstrap(). 327 */ 328 void 329 pmap_bootstrap_finalize(void) 330 { 331 332 #if !defined(amiga) && !defined(atari) 333 /* 334 * XXX 335 * amiga and atari have different pmap initialization functions 336 * and they require this earlier. 337 */ 338 uvmexp.pagesize = NBPG; 339 uvm_setpagesize(); 340 #endif 341 342 /* 343 * Initialize protection array. 344 * XXX: Could this have port specific values? Can't this be static? 345 */ 346 protection_codes[VM_PROT_NONE|VM_PROT_NONE|VM_PROT_NONE] = 0; 347 protection_codes[VM_PROT_READ|VM_PROT_NONE|VM_PROT_NONE] = PG_RO; 348 protection_codes[VM_PROT_READ|VM_PROT_NONE|VM_PROT_EXECUTE] = PG_RO; 349 protection_codes[VM_PROT_NONE|VM_PROT_NONE|VM_PROT_EXECUTE] = PG_RO; 350 protection_codes[VM_PROT_NONE|VM_PROT_WRITE|VM_PROT_NONE] = PG_RW; 351 protection_codes[VM_PROT_NONE|VM_PROT_WRITE|VM_PROT_EXECUTE] = PG_RW; 352 protection_codes[VM_PROT_READ|VM_PROT_WRITE|VM_PROT_NONE] = PG_RW; 353 protection_codes[VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE] = PG_RW; 354 355 /* 356 * Initialize pmap_kernel(). 357 */ 358 pmap_kernel()->pm_stpa = (st_entry_t *)Sysseg_pa; 359 pmap_kernel()->pm_stab = Sysseg; 360 pmap_kernel()->pm_ptab = Sysmap; 361 #if defined(M68040) || defined(M68060) 362 if (mmutype == MMU_68040) 363 pmap_kernel()->pm_stfree = protostfree; 364 #endif 365 simple_lock_init(&pmap_kernel()->pm_lock); 366 pmap_kernel()->pm_count = 1; 367 368 /* 369 * Initialize lwp0 uarea, curlwp, and curpcb. 370 */ 371 memset((void *)lwp0uarea, 0, USPACE); 372 uvm_lwp_setuarea(&lwp0, lwp0uarea); 373 curlwp = &lwp0; 374 curpcb = lwp_getpcb(&lwp0); 375 } 376 377 /* 378 * pmap_virtual_space: [ INTERFACE ] 379 * 380 * Report the range of available kernel virtual address 381 * space to the VM system during bootstrap. 382 * 383 * This is only an interface function if we do not use 384 * pmap_steal_memory()! 385 * 386 * Note: no locking is necessary in this function. 387 */ 388 void 389 pmap_virtual_space(vaddr_t *vstartp, vaddr_t *vendp) 390 { 391 392 *vstartp = virtual_avail; 393 *vendp = virtual_end; 394 } 395 396 /* 397 * pmap_init: [ INTERFACE ] 398 * 399 * Initialize the pmap module. Called by vm_init(), to initialize any 400 * structures that the pmap system needs to map virtual memory. 401 * 402 * Note: no locking is necessary in this function. 403 */ 404 void 405 pmap_init(void) 406 { 407 vaddr_t addr, addr2; 408 vsize_t s; 409 struct pv_header *pvh; 410 int rv; 411 int npages; 412 int bank; 413 414 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_init()\n")); 415 416 /* 417 * Before we do anything else, initialize the PTE pointers 418 * used by pmap_zero_page() and pmap_copy_page(). 419 */ 420 caddr1_pte = pmap_pte(pmap_kernel(), CADDR1); 421 caddr2_pte = pmap_pte(pmap_kernel(), CADDR2); 422 423 PMAP_DPRINTF(PDB_INIT, 424 ("pmap_init: Sysseg %p, Sysmap %p, Sysptmap %p\n", 425 Sysseg, Sysmap, Sysptmap)); 426 PMAP_DPRINTF(PDB_INIT, 427 (" pstart %lx, pend %lx, vstart %lx, vend %lx\n", 428 avail_start, avail_end, virtual_avail, virtual_end)); 429 430 /* 431 * Allocate memory for random pmap data structures. Includes the 432 * initial segment table, pv_head_table and pmap_attributes. 433 */ 434 for (page_cnt = 0, bank = 0; bank < vm_nphysseg; bank++) 435 page_cnt += VM_PHYSMEM_PTR(bank)->end - VM_PHYSMEM_PTR(bank)->start; 436 s = M68K_STSIZE; /* Segtabzero */ 437 s += page_cnt * sizeof(struct pv_header); /* pv table */ 438 s = round_page(s); 439 addr = uvm_km_alloc(kernel_map, s, 0, UVM_KMF_WIRED | UVM_KMF_ZERO); 440 if (addr == 0) 441 panic("pmap_init: can't allocate data structures"); 442 443 Segtabzero = (st_entry_t *)addr; 444 (void)pmap_extract(pmap_kernel(), addr, 445 (paddr_t *)(void *)&Segtabzeropa); 446 addr += M68K_STSIZE; 447 448 pv_table = (struct pv_header *) addr; 449 addr += page_cnt * sizeof(struct pv_header); 450 451 PMAP_DPRINTF(PDB_INIT, ("pmap_init: %lx bytes: page_cnt %x s0 %p(%p) " 452 "tbl %p\n", 453 s, page_cnt, Segtabzero, Segtabzeropa, 454 pv_table)); 455 456 /* 457 * Now that the pv and attribute tables have been allocated, 458 * assign them to the memory segments. 459 */ 460 pvh = pv_table; 461 for (bank = 0; bank < vm_nphysseg; bank++) { 462 npages = VM_PHYSMEM_PTR(bank)->end - VM_PHYSMEM_PTR(bank)->start; 463 VM_PHYSMEM_PTR(bank)->pmseg.pvheader = pvh; 464 pvh += npages; 465 } 466 467 /* 468 * Allocate physical memory for kernel PT pages and their management. 469 * We need 1 PT page per possible task plus some slop. 470 */ 471 npages = min(atop(M68K_MAX_KPTSIZE), maxproc+16); 472 s = ptoa(npages) + round_page(npages * sizeof(struct kpt_page)); 473 474 /* 475 * Verify that space will be allocated in region for which 476 * we already have kernel PT pages. 477 */ 478 addr = 0; 479 rv = uvm_map(kernel_map, &addr, s, NULL, UVM_UNKNOWN_OFFSET, 0, 480 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 481 UVM_ADV_RANDOM, UVM_FLAG_NOMERGE)); 482 if (rv != 0 || (addr + s) >= (vaddr_t)Sysmap) 483 panic("pmap_init: kernel PT too small"); 484 uvm_unmap(kernel_map, addr, addr + s); 485 486 /* 487 * Now allocate the space and link the pages together to 488 * form the KPT free list. 489 */ 490 addr = uvm_km_alloc(kernel_map, s, 0, UVM_KMF_WIRED | UVM_KMF_ZERO); 491 if (addr == 0) 492 panic("pmap_init: cannot allocate KPT free list"); 493 s = ptoa(npages); 494 addr2 = addr + s; 495 kpt_pages = &((struct kpt_page *)addr2)[npages]; 496 kpt_free_list = NULL; 497 do { 498 addr2 -= PAGE_SIZE; 499 (--kpt_pages)->kpt_next = kpt_free_list; 500 kpt_free_list = kpt_pages; 501 kpt_pages->kpt_va = addr2; 502 (void) pmap_extract(pmap_kernel(), addr2, 503 (paddr_t *)&kpt_pages->kpt_pa); 504 } while (addr != addr2); 505 506 PMAP_DPRINTF(PDB_INIT, ("pmap_init: KPT: %ld pages from %lx to %lx\n", 507 atop(s), addr, addr + s)); 508 509 /* 510 * Allocate the segment table map and the page table map. 511 */ 512 s = maxproc * M68K_STSIZE; 513 st_map = uvm_km_suballoc(kernel_map, &addr, &addr2, s, 0, false, 514 &st_map_store); 515 516 addr = M68K_PTBASE; 517 if ((M68K_PTMAXSIZE / M68K_MAX_PTSIZE) < maxproc) { 518 s = M68K_PTMAXSIZE; 519 /* 520 * XXX We don't want to hang when we run out of 521 * page tables, so we lower maxproc so that fork() 522 * will fail instead. Note that root could still raise 523 * this value via sysctl(3). 524 */ 525 maxproc = (M68K_PTMAXSIZE / M68K_MAX_PTSIZE); 526 } else 527 s = (maxproc * M68K_MAX_PTSIZE); 528 pt_map = uvm_km_suballoc(kernel_map, &addr, &addr2, s, 0, 529 true, &pt_map_store); 530 531 #if defined(M68040) || defined(M68060) 532 if (mmutype == MMU_68040) { 533 protostfree = ~l2tobm(0); 534 for (rv = MAXUL2SIZE; rv < sizeof(protostfree)*NBBY; rv++) 535 protostfree &= ~l2tobm(rv); 536 } 537 #endif 538 539 /* 540 * Initialize the pmap pools. 541 */ 542 pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl", 543 &pool_allocator_nointr, IPL_NONE); 544 545 /* 546 * Now that this is done, mark the pages shared with the 547 * hardware page table search as non-CCB (actually, as CI). 548 * 549 * XXX Hm. Given that this is in the kernel map, can't we just 550 * use the va's? 551 */ 552 #ifdef M68060 553 #if defined(M68020) || defined(M68030) || defined(M68040) 554 if (cputype == CPU_68060) 555 #endif 556 { 557 struct kpt_page *kptp = kpt_free_list; 558 paddr_t paddr; 559 560 while (kptp) { 561 pmap_changebit(kptp->kpt_pa, PG_CI, ~PG_CCB); 562 kptp = kptp->kpt_next; 563 } 564 565 paddr = (paddr_t)Segtabzeropa; 566 while (paddr < (paddr_t)Segtabzeropa + M68K_STSIZE) { 567 pmap_changebit(paddr, PG_CI, ~PG_CCB); 568 paddr += PAGE_SIZE; 569 } 570 571 DCIS(); 572 } 573 #endif 574 575 /* 576 * Now it is safe to enable pv_table recording. 577 */ 578 pmap_initialized = true; 579 } 580 581 /* 582 * pmap_alloc_pv: 583 * 584 * Allocate a pv_entry. 585 */ 586 struct pv_entry * 587 pmap_alloc_pv(void) 588 { 589 struct pv_page *pvp; 590 struct pv_entry *pv; 591 int i; 592 593 if (pv_nfree == 0) { 594 pvp = (struct pv_page *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 595 UVM_KMF_WIRED | UVM_KMF_ZERO); 596 if (pvp == NULL) 597 panic("pmap_alloc_pv: uvm_km_alloc() failed"); 598 pvp->pvp_pgi.pgi_freelist = pv = &pvp->pvp_pv[1]; 599 for (i = NPVPPG - 2; i; i--, pv++) 600 pv->pv_next = pv + 1; 601 pv->pv_next = NULL; 602 pv_nfree += pvp->pvp_pgi.pgi_nfree = NPVPPG - 1; 603 TAILQ_INSERT_HEAD(&pv_page_freelist, pvp, pvp_pgi.pgi_list); 604 pv = &pvp->pvp_pv[0]; 605 } else { 606 --pv_nfree; 607 pvp = TAILQ_FIRST(&pv_page_freelist); 608 if (--pvp->pvp_pgi.pgi_nfree == 0) { 609 TAILQ_REMOVE(&pv_page_freelist, pvp, pvp_pgi.pgi_list); 610 } 611 pv = pvp->pvp_pgi.pgi_freelist; 612 #ifdef DIAGNOSTIC 613 if (pv == NULL) 614 panic("pmap_alloc_pv: pgi_nfree inconsistent"); 615 #endif 616 pvp->pvp_pgi.pgi_freelist = pv->pv_next; 617 } 618 return pv; 619 } 620 621 /* 622 * pmap_free_pv: 623 * 624 * Free a pv_entry. 625 */ 626 void 627 pmap_free_pv(struct pv_entry *pv) 628 { 629 struct pv_page *pvp; 630 631 pvp = (struct pv_page *)trunc_page((vaddr_t)pv); 632 switch (++pvp->pvp_pgi.pgi_nfree) { 633 case 1: 634 TAILQ_INSERT_TAIL(&pv_page_freelist, pvp, pvp_pgi.pgi_list); 635 default: 636 pv->pv_next = pvp->pvp_pgi.pgi_freelist; 637 pvp->pvp_pgi.pgi_freelist = pv; 638 ++pv_nfree; 639 break; 640 case NPVPPG: 641 pv_nfree -= NPVPPG - 1; 642 TAILQ_REMOVE(&pv_page_freelist, pvp, pvp_pgi.pgi_list); 643 uvm_km_free(kernel_map, (vaddr_t)pvp, PAGE_SIZE, UVM_KMF_WIRED); 644 break; 645 } 646 } 647 648 /* 649 * pmap_collect_pv: 650 * 651 * Perform compaction on the PV list, called via pmap_collect(). 652 */ 653 #ifdef notyet 654 void 655 pmap_collect_pv(void) 656 { 657 struct pv_page_list pv_page_collectlist; 658 struct pv_page *pvp, *npvp; 659 struct pv_entry *ph, *ppv, *pv, *npv; 660 struct pv_header *pvh; 661 int s; 662 663 TAILQ_INIT(&pv_page_collectlist); 664 665 for (pvp = TAILQ_FIRST(&pv_page_freelist); pvp != NULL; pvp = npvp) { 666 if (pv_nfree < NPVPPG) 667 break; 668 npvp = TAILQ_NEXT(&pvp->pvp_pgi, pgi_list); 669 if (pvp->pvp_pgi.pgi_nfree > NPVPPG / 3) { 670 TAILQ_REMOVE(&pv_page_freelist, pvp, pvp_pgi.pgi_list); 671 TAILQ_INSERT_TAIL(&pv_page_collectlist, pvp, 672 pvp_pgi.pgi_list); 673 pv_nfree -= NPVPPG; 674 pvp->pvp_pgi.pgi_nfree = -1; 675 } 676 } 677 678 if (TAILQ_FIRST(&pv_page_collectlist) == NULL) 679 return; 680 681 for (pvh = &pv_table[page_cnt - 1]; pvh >= &pv_table[0]; pvh--) { 682 ph = &pvh->pvh_first; 683 if (ph->pv_pmap == NULL) 684 continue; 685 s = splvm(); 686 for (ppv = ph; (pv = ppv->pv_next) != NULL; ) { 687 pvp = (struct pv_page *) trunc_page((vaddr_t)pv); 688 if (pvp->pvp_pgi.pgi_nfree == -1) { 689 pvp = TAILQ_FIRST(&pv_page_freelist); 690 if (--pvp->pvp_pgi.pgi_nfree == 0) { 691 TAILQ_REMOVE(&pv_page_freelist, pvp, 692 pvp_pgi.pgi_list); 693 } 694 npv = pvp->pvp_pgi.pgi_freelist; 695 #ifdef DIAGNOSTIC 696 if (npv == NULL) 697 panic("pmap_collect_pv: " 698 "pgi_nfree inconsistent"); 699 #endif 700 pvp->pvp_pgi.pgi_freelist = npv->pv_next; 701 *npv = *pv; 702 ppv->pv_next = npv; 703 ppv = npv; 704 } else 705 ppv = pv; 706 } 707 splx(s); 708 } 709 710 for (pvp = TAILQ_FIRST(&pv_page_collectlist); pvp != NULL; pvp = npvp) { 711 npvp = TAILQ_NEXT(&pvp->pvp_pgi, pgi_list); 712 uvm_km_free(kernel_map, (vaddr_t)pvp, PAGE_SIZE, UVM_KMF_WIRED); 713 } 714 } 715 #endif 716 717 /* 718 * pmap_map: 719 * 720 * Used to map a range of physical addresses into kernel 721 * virtual address space. 722 * 723 * For now, VM is already on, we only need to map the 724 * specified memory. 725 * 726 * Note: THIS FUNCTION IS DEPRECATED, AND SHOULD BE REMOVED! 727 */ 728 vaddr_t 729 pmap_map(vaddr_t va, paddr_t spa, paddr_t epa, int prot) 730 { 731 732 PMAP_DPRINTF(PDB_FOLLOW, 733 ("pmap_map(%lx, %lx, %lx, %x)\n", va, spa, epa, prot)); 734 735 while (spa < epa) { 736 pmap_enter(pmap_kernel(), va, spa, prot, 0); 737 va += PAGE_SIZE; 738 spa += PAGE_SIZE; 739 } 740 pmap_update(pmap_kernel()); 741 return va; 742 } 743 744 /* 745 * pmap_create: [ INTERFACE ] 746 * 747 * Create and return a physical map. 748 * 749 * Note: no locking is necessary in this function. 750 */ 751 pmap_t 752 pmap_create(void) 753 { 754 struct pmap *pmap; 755 756 PMAP_DPRINTF(PDB_FOLLOW|PDB_CREATE, 757 ("pmap_create()\n")); 758 759 pmap = pool_get(&pmap_pmap_pool, PR_WAITOK); 760 memset(pmap, 0, sizeof(*pmap)); 761 pmap_pinit(pmap); 762 return pmap; 763 } 764 765 /* 766 * pmap_pinit: 767 * 768 * Initialize a preallocated and zeroed pmap structure. 769 * 770 * Note: THIS FUNCTION SHOULD BE MOVED INTO pmap_create()! 771 */ 772 void 773 pmap_pinit(struct pmap *pmap) 774 { 775 776 PMAP_DPRINTF(PDB_FOLLOW|PDB_CREATE, 777 ("pmap_pinit(%p)\n", pmap)); 778 779 /* 780 * No need to allocate page table space yet but we do need a 781 * valid segment table. Initially, we point everyone at the 782 * "null" segment table. On the first pmap_enter, a real 783 * segment table will be allocated. 784 */ 785 pmap->pm_stab = Segtabzero; 786 pmap->pm_stpa = Segtabzeropa; 787 #if defined(M68040) || defined(M68060) 788 #if defined(M68020) || defined(M68030) 789 if (mmutype == MMU_68040) 790 #endif 791 pmap->pm_stfree = protostfree; 792 #endif 793 pmap->pm_count = 1; 794 simple_lock_init(&pmap->pm_lock); 795 } 796 797 /* 798 * pmap_destroy: [ INTERFACE ] 799 * 800 * Drop the reference count on the specified pmap, releasing 801 * all resources if the reference count drops to zero. 802 */ 803 void 804 pmap_destroy(pmap_t pmap) 805 { 806 int count; 807 808 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_destroy(%p)\n", pmap)); 809 810 simple_lock(&pmap->pm_lock); 811 count = --pmap->pm_count; 812 simple_unlock(&pmap->pm_lock); 813 if (count == 0) { 814 pmap_release(pmap); 815 pool_put(&pmap_pmap_pool, pmap); 816 } 817 } 818 819 /* 820 * pmap_release: 821 * 822 * Relese the resources held by a pmap. 823 * 824 * Note: THIS FUNCTION SHOULD BE MOVED INTO pmap_destroy(). 825 */ 826 void 827 pmap_release(pmap_t pmap) 828 { 829 830 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_release(%p)\n", pmap)); 831 832 #ifdef notdef /* DIAGNOSTIC */ 833 /* count would be 0 from pmap_destroy... */ 834 simple_lock(&pmap->pm_lock); 835 if (pmap->pm_count != 1) 836 panic("pmap_release count"); 837 #endif 838 839 if (pmap->pm_ptab) { 840 pmap_remove(pmap_kernel(), (vaddr_t)pmap->pm_ptab, 841 (vaddr_t)pmap->pm_ptab + M68K_MAX_PTSIZE); 842 uvm_km_pgremove((vaddr_t)pmap->pm_ptab, 843 (vaddr_t)pmap->pm_ptab + M68K_MAX_PTSIZE); 844 uvm_km_free(pt_map, (vaddr_t)pmap->pm_ptab, 845 M68K_MAX_PTSIZE, UVM_KMF_VAONLY); 846 } 847 KASSERT(pmap->pm_stab == Segtabzero); 848 } 849 850 /* 851 * pmap_reference: [ INTERFACE ] 852 * 853 * Add a reference to the specified pmap. 854 */ 855 void 856 pmap_reference(pmap_t pmap) 857 { 858 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_reference(%p)\n", pmap)); 859 860 simple_lock(&pmap->pm_lock); 861 pmap->pm_count++; 862 simple_unlock(&pmap->pm_lock); 863 } 864 865 /* 866 * pmap_activate: [ INTERFACE ] 867 * 868 * Activate the pmap used by the specified process. This includes 869 * reloading the MMU context if the current process, and marking 870 * the pmap in use by the processor. 871 * 872 * Note: we may only use spin locks here, since we are called 873 * by a critical section in cpu_switch()! 874 */ 875 void 876 pmap_activate(struct lwp *l) 877 { 878 pmap_t pmap = l->l_proc->p_vmspace->vm_map.pmap; 879 880 PMAP_DPRINTF(PDB_FOLLOW|PDB_SEGTAB, 881 ("pmap_activate(%p)\n", l)); 882 883 PMAP_ACTIVATE(pmap, (curlwp->l_flag & LW_IDLE) != 0 || 884 l->l_proc == curproc); 885 } 886 887 /* 888 * pmap_deactivate: [ INTERFACE ] 889 * 890 * Mark that the pmap used by the specified process is no longer 891 * in use by the processor. 892 * 893 * The comment above pmap_activate() wrt. locking applies here, 894 * as well. 895 */ 896 void 897 pmap_deactivate(struct lwp *l) 898 { 899 900 /* No action necessary in this pmap implementation. */ 901 } 902 903 /* 904 * pmap_remove: [ INTERFACE ] 905 * 906 * Remove the given range of addresses from the specified map. 907 * 908 * It is assumed that the start and end are properly 909 * rounded to the page size. 910 */ 911 void 912 pmap_remove(pmap_t pmap, vaddr_t sva, vaddr_t eva) 913 { 914 vaddr_t nssva; 915 pt_entry_t *pte; 916 int flags; 917 #ifdef CACHE_HAVE_VAC 918 bool firstpage = true, needcflush = false; 919 #endif 920 921 PMAP_DPRINTF(PDB_FOLLOW|PDB_REMOVE|PDB_PROTECT, 922 ("pmap_remove(%p, %lx, %lx)\n", pmap, sva, eva)); 923 924 flags = active_pmap(pmap) ? PRM_TFLUSH : 0; 925 while (sva < eva) { 926 nssva = m68k_trunc_seg(sva) + NBSEG; 927 if (nssva == 0 || nssva > eva) 928 nssva = eva; 929 930 /* 931 * Invalidate every valid mapping within this segment. 932 */ 933 934 pte = pmap_pte(pmap, sva); 935 while (sva < nssva) { 936 937 /* 938 * If this segment is unallocated, 939 * skip to the next segment boundary. 940 */ 941 942 if (!pmap_ste_v(pmap, sva)) { 943 sva = nssva; 944 break; 945 } 946 947 if (pmap_pte_v(pte)) { 948 #ifdef CACHE_HAVE_VAC 949 if (pmap_aliasmask) { 950 951 /* 952 * Purge kernel side of VAC to ensure 953 * we get the correct state of any 954 * hardware maintained bits. 955 */ 956 957 if (firstpage) { 958 DCIS(); 959 } 960 961 /* 962 * Remember if we may need to 963 * flush the VAC due to a non-CI 964 * mapping. 965 */ 966 967 if (!needcflush && !pmap_pte_ci(pte)) 968 needcflush = true; 969 970 } 971 firstpage = false; 972 #endif 973 pmap_remove_mapping(pmap, sva, pte, flags); 974 } 975 pte++; 976 sva += PAGE_SIZE; 977 } 978 } 979 980 #ifdef CACHE_HAVE_VAC 981 982 /* 983 * Didn't do anything, no need for cache flushes 984 */ 985 986 if (firstpage) 987 return; 988 989 /* 990 * In a couple of cases, we don't need to worry about flushing 991 * the VAC: 992 * 1. if this is a kernel mapping, 993 * we have already done it 994 * 2. if it is a user mapping not for the current process, 995 * it won't be there 996 */ 997 998 if (pmap_aliasmask && !active_user_pmap(pmap)) 999 needcflush = false; 1000 if (needcflush) { 1001 if (pmap == pmap_kernel()) { 1002 DCIS(); 1003 } else { 1004 DCIU(); 1005 } 1006 } 1007 #endif 1008 } 1009 1010 /* 1011 * pmap_page_protect: [ INTERFACE ] 1012 * 1013 * Lower the permission for all mappings to a given page to 1014 * the permissions specified. 1015 */ 1016 void 1017 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 1018 { 1019 paddr_t pa = VM_PAGE_TO_PHYS(pg); 1020 struct pv_header *pvh; 1021 struct pv_entry *pv; 1022 pt_entry_t *pte; 1023 int s; 1024 1025 #ifdef DEBUG 1026 if ((pmapdebug & (PDB_FOLLOW|PDB_PROTECT)) || 1027 (prot == VM_PROT_NONE && (pmapdebug & PDB_REMOVE))) 1028 printf("pmap_page_protect(%p, %x)\n", pg, prot); 1029 #endif 1030 1031 switch (prot) { 1032 case VM_PROT_READ|VM_PROT_WRITE: 1033 case VM_PROT_ALL: 1034 return; 1035 1036 /* copy_on_write */ 1037 case VM_PROT_READ: 1038 case VM_PROT_READ|VM_PROT_EXECUTE: 1039 pmap_changebit(pa, PG_RO, ~0); 1040 return; 1041 1042 /* remove_all */ 1043 default: 1044 break; 1045 } 1046 1047 pvh = pa_to_pvh(pa); 1048 pv = &pvh->pvh_first; 1049 s = splvm(); 1050 while (pv->pv_pmap != NULL) { 1051 1052 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1053 #ifdef DEBUG 1054 if (!pmap_ste_v(pv->pv_pmap, pv->pv_va) || 1055 pmap_pte_pa(pte) != pa) 1056 panic("pmap_page_protect: bad mapping"); 1057 #endif 1058 pmap_remove_mapping(pv->pv_pmap, pv->pv_va, 1059 pte, PRM_TFLUSH|PRM_CFLUSH); 1060 } 1061 splx(s); 1062 } 1063 1064 /* 1065 * pmap_protect: [ INTERFACE ] 1066 * 1067 * Set the physical protection on the specified range of this map 1068 * as requested. 1069 */ 1070 void 1071 pmap_protect(pmap_t pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 1072 { 1073 vaddr_t nssva; 1074 pt_entry_t *pte; 1075 bool firstpage, needtflush; 1076 int isro; 1077 1078 PMAP_DPRINTF(PDB_FOLLOW|PDB_PROTECT, 1079 ("pmap_protect(%p, %lx, %lx, %x)\n", 1080 pmap, sva, eva, prot)); 1081 1082 #ifdef PMAPSTATS 1083 protect_stats.calls++; 1084 #endif 1085 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1086 pmap_remove(pmap, sva, eva); 1087 return; 1088 } 1089 isro = pte_prot(pmap, prot); 1090 needtflush = active_pmap(pmap); 1091 firstpage = true; 1092 while (sva < eva) { 1093 nssva = m68k_trunc_seg(sva) + NBSEG; 1094 if (nssva == 0 || nssva > eva) 1095 nssva = eva; 1096 1097 /* 1098 * If VA belongs to an unallocated segment, 1099 * skip to the next segment boundary. 1100 */ 1101 1102 if (!pmap_ste_v(pmap, sva)) { 1103 sva = nssva; 1104 continue; 1105 } 1106 1107 /* 1108 * Change protection on mapping if it is valid and doesn't 1109 * already have the correct protection. 1110 */ 1111 1112 pte = pmap_pte(pmap, sva); 1113 while (sva < nssva) { 1114 if (pmap_pte_v(pte) && pmap_pte_prot_chg(pte, isro)) { 1115 #ifdef CACHE_HAVE_VAC 1116 1117 /* 1118 * Purge kernel side of VAC to ensure we 1119 * get the correct state of any hardware 1120 * maintained bits. 1121 * 1122 * XXX do we need to clear the VAC in 1123 * general to reflect the new protection? 1124 */ 1125 1126 if (firstpage && pmap_aliasmask) 1127 DCIS(); 1128 #endif 1129 1130 #if defined(M68040) || defined(M68060) 1131 1132 /* 1133 * Clear caches if making RO (see section 1134 * "7.3 Cache Coherency" in the manual). 1135 */ 1136 1137 #if defined(M68020) || defined(M68030) 1138 if (isro && mmutype == MMU_68040) 1139 #else 1140 if (isro) 1141 #endif 1142 { 1143 paddr_t pa = pmap_pte_pa(pte); 1144 1145 DCFP(pa); 1146 ICPP(pa); 1147 } 1148 #endif 1149 pmap_pte_set_prot(pte, isro); 1150 if (needtflush) 1151 TBIS(sva); 1152 firstpage = false; 1153 } 1154 pte++; 1155 sva += PAGE_SIZE; 1156 } 1157 } 1158 } 1159 1160 /* 1161 * pmap_enter: [ INTERFACE ] 1162 * 1163 * Insert the given physical page (pa) at 1164 * the specified virtual address (va) in the 1165 * target physical map with the protection requested. 1166 * 1167 * If specified, the page will be wired down, meaning 1168 * that the related pte cannot be reclaimed. 1169 * 1170 * Note: This is the only routine which MAY NOT lazy-evaluate 1171 * or lose information. Thatis, this routine must actually 1172 * insert this page into the given map NOW. 1173 */ 1174 int 1175 pmap_enter(pmap_t pmap, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 1176 { 1177 pt_entry_t *pte; 1178 int npte; 1179 paddr_t opa; 1180 bool cacheable = true; 1181 bool checkpv = true; 1182 bool wired = (flags & PMAP_WIRED) != 0; 1183 bool can_fail = (flags & PMAP_CANFAIL) != 0; 1184 1185 PMAP_DPRINTF(PDB_FOLLOW|PDB_ENTER, 1186 ("pmap_enter(%p, %lx, %lx, %x, %x)\n", 1187 pmap, va, pa, prot, wired)); 1188 1189 #ifdef DIAGNOSTIC 1190 /* 1191 * pmap_enter() should never be used for CADDR1 and CADDR2. 1192 */ 1193 if (pmap == pmap_kernel() && 1194 (va == (vaddr_t)CADDR1 || va == (vaddr_t)CADDR2)) 1195 panic("pmap_enter: used for CADDR1 or CADDR2"); 1196 #endif 1197 1198 /* 1199 * For user mapping, allocate kernel VM resources if necessary. 1200 */ 1201 if (pmap->pm_ptab == NULL) { 1202 pmap->pm_ptab = (pt_entry_t *) 1203 uvm_km_alloc(pt_map, M68K_MAX_PTSIZE, 0, 1204 UVM_KMF_VAONLY | 1205 (can_fail ? UVM_KMF_NOWAIT : UVM_KMF_WAITVA)); 1206 if (pmap->pm_ptab == NULL) 1207 return ENOMEM; 1208 } 1209 1210 /* 1211 * Segment table entry not valid, we need a new PT page 1212 */ 1213 if (!pmap_ste_v(pmap, va)) { 1214 int err = pmap_enter_ptpage(pmap, va, can_fail); 1215 if (err) 1216 return err; 1217 } 1218 1219 pa = m68k_trunc_page(pa); 1220 pte = pmap_pte(pmap, va); 1221 opa = pmap_pte_pa(pte); 1222 1223 PMAP_DPRINTF(PDB_ENTER, ("enter: pte %p, *pte %x\n", pte, *pte)); 1224 1225 /* 1226 * Mapping has not changed, must be protection or wiring change. 1227 */ 1228 if (opa == pa) { 1229 /* 1230 * Wiring change, just update stats. 1231 * We don't worry about wiring PT pages as they remain 1232 * resident as long as there are valid mappings in them. 1233 * Hence, if a user page is wired, the PT page will be also. 1234 */ 1235 if (pmap_pte_w_chg(pte, wired ? PG_W : 0)) { 1236 PMAP_DPRINTF(PDB_ENTER, 1237 ("enter: wiring change -> %x\n", wired)); 1238 if (wired) 1239 pmap->pm_stats.wired_count++; 1240 else 1241 pmap->pm_stats.wired_count--; 1242 } 1243 /* 1244 * Retain cache inhibition status 1245 */ 1246 checkpv = false; 1247 if (pmap_pte_ci(pte)) 1248 cacheable = false; 1249 goto validate; 1250 } 1251 1252 /* 1253 * Mapping has changed, invalidate old range and fall through to 1254 * handle validating new mapping. 1255 */ 1256 if (opa) { 1257 PMAP_DPRINTF(PDB_ENTER, 1258 ("enter: removing old mapping %lx\n", va)); 1259 pmap_remove_mapping(pmap, va, pte, 1260 PRM_TFLUSH|PRM_CFLUSH|PRM_KEEPPTPAGE); 1261 } 1262 1263 /* 1264 * If this is a new user mapping, increment the wiring count 1265 * on this PT page. PT pages are wired down as long as there 1266 * is a valid mapping in the page. 1267 */ 1268 if (pmap != pmap_kernel()) 1269 pmap_ptpage_addref(trunc_page((vaddr_t)pte)); 1270 1271 /* 1272 * Enter on the PV list if part of our managed memory 1273 * Note that we raise IPL while manipulating pv_table 1274 * since pmap_enter can be called at interrupt time. 1275 */ 1276 if (PAGE_IS_MANAGED(pa)) { 1277 struct pv_header *pvh; 1278 struct pv_entry *pv, *npv; 1279 int s; 1280 1281 pvh = pa_to_pvh(pa); 1282 pv = &pvh->pvh_first; 1283 s = splvm(); 1284 1285 PMAP_DPRINTF(PDB_ENTER, 1286 ("enter: pv at %p: %lx/%p/%p\n", 1287 pv, pv->pv_va, pv->pv_pmap, pv->pv_next)); 1288 /* 1289 * No entries yet, use header as the first entry 1290 */ 1291 if (pv->pv_pmap == NULL) { 1292 pv->pv_va = va; 1293 pv->pv_pmap = pmap; 1294 pv->pv_next = NULL; 1295 pv->pv_ptste = NULL; 1296 pv->pv_ptpmap = NULL; 1297 pvh->pvh_attrs = 0; 1298 } 1299 /* 1300 * There is at least one other VA mapping this page. 1301 * Place this entry after the header. 1302 */ 1303 else { 1304 #ifdef DEBUG 1305 for (npv = pv; npv; npv = npv->pv_next) 1306 if (pmap == npv->pv_pmap && va == npv->pv_va) 1307 panic("pmap_enter: already in pv_tab"); 1308 #endif 1309 npv = pmap_alloc_pv(); 1310 npv->pv_va = va; 1311 npv->pv_pmap = pmap; 1312 npv->pv_next = pv->pv_next; 1313 npv->pv_ptste = NULL; 1314 npv->pv_ptpmap = NULL; 1315 pv->pv_next = npv; 1316 1317 #ifdef CACHE_HAVE_VAC 1318 1319 /* 1320 * Since there is another logical mapping for the 1321 * same page we may need to cache-inhibit the 1322 * descriptors on those CPUs with external VACs. 1323 * We don't need to CI if: 1324 * 1325 * - No two mappings belong to the same user pmaps. 1326 * Since the cache is flushed on context switches 1327 * there is no problem between user processes. 1328 * 1329 * - Mappings within a single pmap are a certain 1330 * magic distance apart. VAs at these appropriate 1331 * boundaries map to the same cache entries or 1332 * otherwise don't conflict. 1333 * 1334 * To keep it simple, we only check for these special 1335 * cases if there are only two mappings, otherwise we 1336 * punt and always CI. 1337 * 1338 * Note that there are no aliasing problems with the 1339 * on-chip data-cache when the WA bit is set. 1340 */ 1341 1342 if (pmap_aliasmask) { 1343 if (pvh->pvh_attrs & PVH_CI) { 1344 PMAP_DPRINTF(PDB_CACHE, 1345 ("enter: pa %lx already CI'ed\n", 1346 pa)); 1347 checkpv = cacheable = false; 1348 } else if (npv->pv_next || 1349 ((pmap == pv->pv_pmap || 1350 pmap == pmap_kernel() || 1351 pv->pv_pmap == pmap_kernel()) && 1352 ((pv->pv_va & pmap_aliasmask) != 1353 (va & pmap_aliasmask)))) { 1354 PMAP_DPRINTF(PDB_CACHE, 1355 ("enter: pa %lx CI'ing all\n", 1356 pa)); 1357 cacheable = false; 1358 pvh->pvh_attrs |= PVH_CI; 1359 } 1360 } 1361 #endif 1362 } 1363 1364 /* 1365 * Speed pmap_is_referenced() or pmap_is_modified() based 1366 * on the hint provided in access_type. 1367 */ 1368 #ifdef DIAGNOSTIC 1369 if ((flags & VM_PROT_ALL) & ~prot) 1370 panic("pmap_enter: access_type exceeds prot"); 1371 #endif 1372 if (flags & VM_PROT_WRITE) 1373 pvh->pvh_attrs |= (PG_U|PG_M); 1374 else if (flags & VM_PROT_ALL) 1375 pvh->pvh_attrs |= PG_U; 1376 1377 splx(s); 1378 } 1379 /* 1380 * Assumption: if it is not part of our managed memory 1381 * then it must be device memory which may be volitile. 1382 */ 1383 else if (pmap_initialized) { 1384 checkpv = cacheable = false; 1385 } 1386 1387 /* 1388 * Increment counters 1389 */ 1390 pmap->pm_stats.resident_count++; 1391 if (wired) 1392 pmap->pm_stats.wired_count++; 1393 1394 validate: 1395 #ifdef CACHE_HAVE_VAC 1396 /* 1397 * Purge kernel side of VAC to ensure we get correct state 1398 * of HW bits so we don't clobber them. 1399 */ 1400 if (pmap_aliasmask) 1401 DCIS(); 1402 #endif 1403 1404 /* 1405 * Build the new PTE. 1406 */ 1407 1408 npte = pa | pte_prot(pmap, prot) | (*pte & (PG_M|PG_U)) | PG_V; 1409 if (wired) 1410 npte |= PG_W; 1411 if (!checkpv && !cacheable) 1412 #if defined(M68040) || defined(M68060) 1413 #if defined(M68020) || defined(M68030) 1414 npte |= (mmutype == MMU_68040 ? PG_CIN : PG_CI); 1415 #else 1416 npte |= PG_CIN; 1417 #endif 1418 #else 1419 npte |= PG_CI; 1420 #endif 1421 #if defined(M68040) || defined(M68060) 1422 #if defined(M68020) || defined(M68030) 1423 else if (mmutype == MMU_68040 && (npte & (PG_PROT|PG_CI)) == PG_RW) 1424 #else 1425 else if ((npte & (PG_PROT|PG_CI)) == PG_RW) 1426 #endif 1427 npte |= PG_CCB; 1428 #endif 1429 1430 PMAP_DPRINTF(PDB_ENTER, ("enter: new pte value %x\n", npte)); 1431 1432 /* 1433 * Remember if this was a wiring-only change. 1434 * If so, we need not flush the TLB and caches. 1435 */ 1436 1437 wired = ((*pte ^ npte) == PG_W); 1438 #if defined(M68040) || defined(M68060) 1439 #if defined(M68020) || defined(M68030) 1440 if (mmutype == MMU_68040 && !wired) 1441 #else 1442 if (!wired) 1443 #endif 1444 { 1445 DCFP(pa); 1446 ICPP(pa); 1447 } 1448 #endif 1449 *pte = npte; 1450 if (!wired && active_pmap(pmap)) 1451 TBIS(va); 1452 #ifdef CACHE_HAVE_VAC 1453 /* 1454 * The following is executed if we are entering a second 1455 * (or greater) mapping for a physical page and the mappings 1456 * may create an aliasing problem. In this case we must 1457 * cache inhibit the descriptors involved and flush any 1458 * external VAC. 1459 */ 1460 if (checkpv && !cacheable) { 1461 pmap_changebit(pa, PG_CI, ~0); 1462 DCIA(); 1463 #ifdef DEBUG 1464 if ((pmapdebug & (PDB_CACHE|PDB_PVDUMP)) == 1465 (PDB_CACHE|PDB_PVDUMP)) 1466 pmap_pvdump(pa); 1467 #endif 1468 } 1469 #endif 1470 #ifdef DEBUG 1471 if ((pmapdebug & PDB_WIRING) && pmap != pmap_kernel()) 1472 pmap_check_wiring("enter", trunc_page((vaddr_t)pte)); 1473 #endif 1474 1475 return 0; 1476 } 1477 1478 void 1479 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 1480 { 1481 pmap_t pmap = pmap_kernel(); 1482 pt_entry_t *pte; 1483 int s, npte; 1484 1485 PMAP_DPRINTF(PDB_FOLLOW|PDB_ENTER, 1486 ("pmap_kenter_pa(%lx, %lx, %x)\n", va, pa, prot)); 1487 1488 /* 1489 * Segment table entry not valid, we need a new PT page 1490 */ 1491 1492 if (!pmap_ste_v(pmap, va)) { 1493 s = splvm(); 1494 pmap_enter_ptpage(pmap, va, false); 1495 splx(s); 1496 } 1497 1498 pa = m68k_trunc_page(pa); 1499 pte = pmap_pte(pmap, va); 1500 1501 PMAP_DPRINTF(PDB_ENTER, ("enter: pte %p, *pte %x\n", pte, *pte)); 1502 KASSERT(!pmap_pte_v(pte)); 1503 1504 /* 1505 * Increment counters 1506 */ 1507 1508 pmap->pm_stats.resident_count++; 1509 pmap->pm_stats.wired_count++; 1510 1511 /* 1512 * Build the new PTE. 1513 */ 1514 1515 npte = pa | pte_prot(pmap, prot) | PG_V | PG_W; 1516 #if defined(M68040) || defined(M68060) 1517 #if defined(M68020) || defined(M68030) 1518 if (mmutype == MMU_68040 && (npte & PG_PROT) == PG_RW) 1519 #else 1520 if ((npte & PG_PROT) == PG_RW) 1521 #endif 1522 npte |= PG_CCB; 1523 1524 if (mmutype == MMU_68040) { 1525 DCFP(pa); 1526 ICPP(pa); 1527 } 1528 #endif 1529 1530 *pte = npte; 1531 TBIS(va); 1532 } 1533 1534 void 1535 pmap_kremove(vaddr_t va, vsize_t size) 1536 { 1537 pmap_t pmap = pmap_kernel(); 1538 pt_entry_t *pte; 1539 vaddr_t nssva; 1540 vaddr_t eva = va + size; 1541 #ifdef CACHE_HAVE_VAC 1542 bool firstpage, needcflush; 1543 #endif 1544 1545 PMAP_DPRINTF(PDB_FOLLOW|PDB_REMOVE|PDB_PROTECT, 1546 ("pmap_kremove(%lx, %lx)\n", va, size)); 1547 1548 #ifdef CACHE_HAVE_VAC 1549 firstpage = true; 1550 needcflush = false; 1551 #endif 1552 while (va < eva) { 1553 nssva = m68k_trunc_seg(va) + NBSEG; 1554 if (nssva == 0 || nssva > eva) 1555 nssva = eva; 1556 1557 /* 1558 * If VA belongs to an unallocated segment, 1559 * skip to the next segment boundary. 1560 */ 1561 1562 if (!pmap_ste_v(pmap, va)) { 1563 va = nssva; 1564 continue; 1565 } 1566 1567 /* 1568 * Invalidate every valid mapping within this segment. 1569 */ 1570 1571 pte = pmap_pte(pmap, va); 1572 while (va < nssva) { 1573 if (!pmap_pte_v(pte)) { 1574 pte++; 1575 va += PAGE_SIZE; 1576 continue; 1577 } 1578 #ifdef CACHE_HAVE_VAC 1579 if (pmap_aliasmask) { 1580 1581 /* 1582 * Purge kernel side of VAC to ensure 1583 * we get the correct state of any 1584 * hardware maintained bits. 1585 */ 1586 1587 if (firstpage) { 1588 DCIS(); 1589 firstpage = false; 1590 } 1591 1592 /* 1593 * Remember if we may need to 1594 * flush the VAC. 1595 */ 1596 1597 needcflush = true; 1598 } 1599 #endif 1600 pmap->pm_stats.wired_count--; 1601 pmap->pm_stats.resident_count--; 1602 *pte = PG_NV; 1603 TBIS(va); 1604 pte++; 1605 va += PAGE_SIZE; 1606 } 1607 } 1608 1609 #ifdef CACHE_HAVE_VAC 1610 1611 /* 1612 * In a couple of cases, we don't need to worry about flushing 1613 * the VAC: 1614 * 1. if this is a kernel mapping, 1615 * we have already done it 1616 * 2. if it is a user mapping not for the current process, 1617 * it won't be there 1618 */ 1619 1620 if (pmap_aliasmask && !active_user_pmap(pmap)) 1621 needcflush = false; 1622 if (needcflush) { 1623 if (pmap == pmap_kernel()) { 1624 DCIS(); 1625 } else { 1626 DCIU(); 1627 } 1628 } 1629 #endif 1630 } 1631 1632 /* 1633 * pmap_unwire: [ INTERFACE ] 1634 * 1635 * Clear the wired attribute for a map/virtual-address pair. 1636 * 1637 * The mapping must already exist in the pmap. 1638 */ 1639 void 1640 pmap_unwire(pmap_t pmap, vaddr_t va) 1641 { 1642 pt_entry_t *pte; 1643 1644 PMAP_DPRINTF(PDB_FOLLOW, 1645 ("pmap_unwire(%p, %lx)\n", pmap, va)); 1646 1647 pte = pmap_pte(pmap, va); 1648 1649 /* 1650 * If wiring actually changed (always?) clear the wire bit and 1651 * update the wire count. Note that wiring is not a hardware 1652 * characteristic so there is no need to invalidate the TLB. 1653 */ 1654 1655 if (pmap_pte_w_chg(pte, 0)) { 1656 pmap_pte_set_w(pte, false); 1657 pmap->pm_stats.wired_count--; 1658 } 1659 } 1660 1661 /* 1662 * pmap_extract: [ INTERFACE ] 1663 * 1664 * Extract the physical address associated with the given 1665 * pmap/virtual address pair. 1666 */ 1667 bool 1668 pmap_extract(pmap_t pmap, vaddr_t va, paddr_t *pap) 1669 { 1670 paddr_t pa; 1671 u_int pte; 1672 1673 PMAP_DPRINTF(PDB_FOLLOW, 1674 ("pmap_extract(%p, %lx) -> ", pmap, va)); 1675 1676 if (pmap_ste_v(pmap, va)) { 1677 pte = *(u_int *)pmap_pte(pmap, va); 1678 if (pte) { 1679 pa = (pte & PG_FRAME) | (va & ~PG_FRAME); 1680 if (pap != NULL) 1681 *pap = pa; 1682 #ifdef DEBUG 1683 if (pmapdebug & PDB_FOLLOW) 1684 printf("%lx\n", pa); 1685 #endif 1686 return true; 1687 } 1688 } 1689 #ifdef DEBUG 1690 if (pmapdebug & PDB_FOLLOW) 1691 printf("failed\n"); 1692 #endif 1693 return false; 1694 } 1695 1696 /* 1697 * pmap_copy: [ INTERFACE ] 1698 * 1699 * Copy the mapping range specified by src_addr/len 1700 * from the source map to the range dst_addr/len 1701 * in the destination map. 1702 * 1703 * This routine is only advisory and need not do anything. 1704 */ 1705 void 1706 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vaddr_t dst_addr, vsize_t len, 1707 vaddr_t src_addr) 1708 { 1709 1710 PMAP_DPRINTF(PDB_FOLLOW, 1711 ("pmap_copy(%p, %p, %lx, %lx, %lx)\n", 1712 dst_pmap, src_pmap, dst_addr, len, src_addr)); 1713 } 1714 1715 /* 1716 * pmap_collect1(): 1717 * 1718 * Garbage-collect KPT pages. Helper for the above (bogus) 1719 * pmap_collect(). 1720 * 1721 * Note: THIS SHOULD GO AWAY, AND BE REPLACED WITH A BETTER 1722 * WAY OF HANDLING PT PAGES! 1723 */ 1724 static inline void 1725 pmap_collect1(pmap_t pmap, paddr_t startpa, paddr_t endpa) 1726 { 1727 paddr_t pa; 1728 struct pv_header *pvh; 1729 struct pv_entry *pv; 1730 pt_entry_t *pte; 1731 paddr_t kpa; 1732 #ifdef DEBUG 1733 st_entry_t *ste; 1734 int opmapdebug = 0; 1735 #endif 1736 1737 for (pa = startpa; pa < endpa; pa += PAGE_SIZE) { 1738 struct kpt_page *kpt, **pkpt; 1739 1740 /* 1741 * Locate physical pages which are being used as kernel 1742 * page table pages. 1743 */ 1744 1745 pvh = pa_to_pvh(pa); 1746 pv = &pvh->pvh_first; 1747 if (pv->pv_pmap != pmap_kernel() || 1748 !(pvh->pvh_attrs & PVH_PTPAGE)) 1749 continue; 1750 do { 1751 if (pv->pv_ptste && pv->pv_ptpmap == pmap_kernel()) 1752 break; 1753 } while ((pv = pv->pv_next)); 1754 if (pv == NULL) 1755 continue; 1756 #ifdef DEBUG 1757 if (pv->pv_va < (vaddr_t)Sysmap || 1758 pv->pv_va >= (vaddr_t)Sysmap + M68K_MAX_PTSIZE) { 1759 printf("collect: kernel PT VA out of range\n"); 1760 pmap_pvdump(pa); 1761 continue; 1762 } 1763 #endif 1764 pte = (pt_entry_t *)(pv->pv_va + PAGE_SIZE); 1765 while (--pte >= (pt_entry_t *)pv->pv_va && *pte == PG_NV) 1766 ; 1767 if (pte >= (pt_entry_t *)pv->pv_va) 1768 continue; 1769 1770 #ifdef DEBUG 1771 if (pmapdebug & (PDB_PTPAGE|PDB_COLLECT)) { 1772 printf("collect: freeing KPT page at %lx (ste %x@%p)\n", 1773 pv->pv_va, *pv->pv_ptste, pv->pv_ptste); 1774 opmapdebug = pmapdebug; 1775 pmapdebug |= PDB_PTPAGE; 1776 } 1777 1778 ste = pv->pv_ptste; 1779 #endif 1780 /* 1781 * If all entries were invalid we can remove the page. 1782 * We call pmap_remove_entry to take care of invalidating 1783 * ST and Sysptmap entries. 1784 */ 1785 1786 (void) pmap_extract(pmap, pv->pv_va, &kpa); 1787 pmap_remove_mapping(pmap, pv->pv_va, NULL, 1788 PRM_TFLUSH|PRM_CFLUSH); 1789 1790 /* 1791 * Use the physical address to locate the original 1792 * (kmem_alloc assigned) address for the page and put 1793 * that page back on the free list. 1794 */ 1795 1796 for (pkpt = &kpt_used_list, kpt = *pkpt; 1797 kpt != NULL; 1798 pkpt = &kpt->kpt_next, kpt = *pkpt) 1799 if (kpt->kpt_pa == kpa) 1800 break; 1801 #ifdef DEBUG 1802 if (kpt == NULL) 1803 panic("pmap_collect: lost a KPT page"); 1804 if (pmapdebug & (PDB_PTPAGE|PDB_COLLECT)) 1805 printf("collect: %lx (%lx) to free list\n", 1806 kpt->kpt_va, kpa); 1807 #endif 1808 *pkpt = kpt->kpt_next; 1809 kpt->kpt_next = kpt_free_list; 1810 kpt_free_list = kpt; 1811 #ifdef DEBUG 1812 if (pmapdebug & (PDB_PTPAGE|PDB_COLLECT)) 1813 pmapdebug = opmapdebug; 1814 1815 if (*ste != SG_NV) 1816 printf("collect: kernel STE at %p still valid (%x)\n", 1817 ste, *ste); 1818 ste = &Sysptmap[ste - pmap_ste(pmap_kernel(), 0)]; 1819 if (*ste != SG_NV) 1820 printf("collect: kernel PTmap at %p still valid (%x)\n", 1821 ste, *ste); 1822 #endif 1823 } 1824 } 1825 1826 /* 1827 * pmap_collect: 1828 * 1829 * Helper for pmap_enter_ptpage(). 1830 * 1831 * Garbage collects the physical map system for pages which are no 1832 * longer used. Success need not be guaranteed -- that is, there 1833 * may well be pages which are not referenced, but others may be 1834 * collected. 1835 */ 1836 static void 1837 pmap_collect(void) 1838 { 1839 int bank, s; 1840 1841 /* 1842 * XXX This is very bogus. We should handle kernel PT 1843 * XXX pages much differently. 1844 */ 1845 1846 s = splvm(); 1847 for (bank = 0; bank < vm_nphysseg; bank++) { 1848 pmap_collect1(pmap_kernel(), ptoa(VM_PHYSMEM_PTR(bank)->start), 1849 ptoa(VM_PHYSMEM_PTR(bank)->end)); 1850 } 1851 splx(s); 1852 1853 #ifdef notyet 1854 /* Go compact and garbage-collect the pv_table. */ 1855 pmap_collect_pv(); 1856 #endif 1857 } 1858 1859 /* 1860 * pmap_zero_page: [ INTERFACE ] 1861 * 1862 * Zero the specified (machine independent) page by mapping the page 1863 * into virtual memory and using memset to clear its contents, one 1864 * machine dependent page at a time. 1865 * 1866 * Note: WE DO NOT CURRENTLY LOCK THE TEMPORARY ADDRESSES! 1867 * (Actually, we go to splvm(), and since we don't 1868 * support multiple processors, this is sufficient.) 1869 */ 1870 void 1871 pmap_zero_page(paddr_t phys) 1872 { 1873 int npte; 1874 1875 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_zero_page(%lx)\n", phys)); 1876 1877 npte = phys | PG_V; 1878 #ifdef CACHE_HAVE_VAC 1879 if (pmap_aliasmask) { 1880 1881 /* 1882 * Cache-inhibit the mapping on VAC machines, as we would 1883 * be wasting the cache load. 1884 */ 1885 1886 npte |= PG_CI; 1887 } 1888 #endif 1889 1890 #if defined(M68040) || defined(M68060) 1891 #if defined(M68020) || defined(M68030) 1892 if (mmutype == MMU_68040) 1893 #endif 1894 { 1895 /* 1896 * Set copyback caching on the page; this is required 1897 * for cache consistency (since regular mappings are 1898 * copyback as well). 1899 */ 1900 1901 npte |= PG_CCB; 1902 } 1903 #endif 1904 1905 *caddr1_pte = npte; 1906 TBIS((vaddr_t)CADDR1); 1907 1908 zeropage(CADDR1); 1909 1910 #ifdef DEBUG 1911 *caddr1_pte = PG_NV; 1912 TBIS((vaddr_t)CADDR1); 1913 #endif 1914 } 1915 1916 /* 1917 * pmap_copy_page: [ INTERFACE ] 1918 * 1919 * Copy the specified (machine independent) page by mapping the page 1920 * into virtual memory and using memcpy to copy the page, one machine 1921 * dependent page at a time. 1922 * 1923 * Note: WE DO NOT CURRENTLY LOCK THE TEMPORARY ADDRESSES! 1924 * (Actually, we go to splvm(), and since we don't 1925 * support multiple processors, this is sufficient.) 1926 */ 1927 void 1928 pmap_copy_page(paddr_t src, paddr_t dst) 1929 { 1930 int npte1, npte2; 1931 1932 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_copy_page(%lx, %lx)\n", src, dst)); 1933 1934 npte1 = src | PG_RO | PG_V; 1935 npte2 = dst | PG_V; 1936 #ifdef CACHE_HAVE_VAC 1937 if (pmap_aliasmask) { 1938 1939 /* 1940 * Cache-inhibit the mapping on VAC machines, as we would 1941 * be wasting the cache load. 1942 */ 1943 1944 npte1 |= PG_CI; 1945 npte2 |= PG_CI; 1946 } 1947 #endif 1948 1949 #if defined(M68040) || defined(M68060) 1950 #if defined(M68020) || defined(M68030) 1951 if (mmutype == MMU_68040) 1952 #endif 1953 { 1954 /* 1955 * Set copyback caching on the pages; this is required 1956 * for cache consistency (since regular mappings are 1957 * copyback as well). 1958 */ 1959 1960 npte1 |= PG_CCB; 1961 npte2 |= PG_CCB; 1962 } 1963 #endif 1964 1965 *caddr1_pte = npte1; 1966 TBIS((vaddr_t)CADDR1); 1967 1968 *caddr2_pte = npte2; 1969 TBIS((vaddr_t)CADDR2); 1970 1971 copypage(CADDR1, CADDR2); 1972 1973 #ifdef DEBUG 1974 *caddr1_pte = PG_NV; 1975 TBIS((vaddr_t)CADDR1); 1976 1977 *caddr2_pte = PG_NV; 1978 TBIS((vaddr_t)CADDR2); 1979 #endif 1980 } 1981 1982 /* 1983 * pmap_clear_modify: [ INTERFACE ] 1984 * 1985 * Clear the modify bits on the specified physical page. 1986 */ 1987 bool 1988 pmap_clear_modify(struct vm_page *pg) 1989 { 1990 paddr_t pa = VM_PAGE_TO_PHYS(pg); 1991 1992 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_clear_modify(%p)\n", pg)); 1993 1994 return pmap_changebit(pa, 0, ~PG_M); 1995 } 1996 1997 /* 1998 * pmap_clear_reference: [ INTERFACE ] 1999 * 2000 * Clear the reference bit on the specified physical page. 2001 */ 2002 bool 2003 pmap_clear_reference(struct vm_page *pg) 2004 { 2005 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2006 2007 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_clear_reference(%p)\n", pg)); 2008 2009 return pmap_changebit(pa, 0, ~PG_U); 2010 } 2011 2012 /* 2013 * pmap_is_referenced: [ INTERFACE ] 2014 * 2015 * Return whether or not the specified physical page is referenced 2016 * by any physical maps. 2017 */ 2018 bool 2019 pmap_is_referenced(struct vm_page *pg) 2020 { 2021 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2022 2023 return pmap_testbit(pa, PG_U); 2024 } 2025 2026 /* 2027 * pmap_is_modified: [ INTERFACE ] 2028 * 2029 * Return whether or not the specified physical page is modified 2030 * by any physical maps. 2031 */ 2032 bool 2033 pmap_is_modified(struct vm_page *pg) 2034 { 2035 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2036 2037 return pmap_testbit(pa, PG_M); 2038 } 2039 2040 /* 2041 * pmap_phys_address: [ INTERFACE ] 2042 * 2043 * Return the physical address corresponding to the specified 2044 * cookie. Used by the device pager to decode a device driver's 2045 * mmap entry point return value. 2046 * 2047 * Note: no locking is necessary in this function. 2048 */ 2049 paddr_t 2050 pmap_phys_address(paddr_t ppn) 2051 { 2052 return m68k_ptob(ppn); 2053 } 2054 2055 #ifdef CACHE_HAVE_VAC 2056 /* 2057 * pmap_prefer: [ INTERFACE ] 2058 * 2059 * Find the first virtual address >= *vap that does not 2060 * cause a virtually-addressed cache alias problem. 2061 */ 2062 void 2063 pmap_prefer(vaddr_t foff, vaddr_t *vap) 2064 { 2065 vaddr_t va; 2066 vsize_t d; 2067 2068 #ifdef M68K_MMU_MOTOROLA 2069 if (pmap_aliasmask) 2070 #endif 2071 { 2072 va = *vap; 2073 d = foff - va; 2074 d &= pmap_aliasmask; 2075 *vap = va + d; 2076 } 2077 } 2078 #endif /* CACHE_HAVE_VAC */ 2079 2080 /* 2081 * Miscellaneous support routines follow 2082 */ 2083 2084 /* 2085 * pmap_remove_mapping: 2086 * 2087 * Invalidate a single page denoted by pmap/va. 2088 * 2089 * If (pte != NULL), it is the already computed PTE for the page. 2090 * 2091 * If (flags & PRM_TFLUSH), we must invalidate any TLB information. 2092 * 2093 * If (flags & PRM_CFLUSH), we must flush/invalidate any cache 2094 * information. 2095 * 2096 * If (flags & PRM_KEEPPTPAGE), we don't free the page table page 2097 * if the reference drops to zero. 2098 */ 2099 /* static */ 2100 void 2101 pmap_remove_mapping(pmap_t pmap, vaddr_t va, pt_entry_t *pte, int flags) 2102 { 2103 paddr_t pa; 2104 struct pv_header *pvh; 2105 struct pv_entry *pv, *npv; 2106 struct pmap *ptpmap; 2107 st_entry_t *ste; 2108 int s, bits; 2109 #ifdef DEBUG 2110 pt_entry_t opte; 2111 #endif 2112 2113 PMAP_DPRINTF(PDB_FOLLOW|PDB_REMOVE|PDB_PROTECT, 2114 ("pmap_remove_mapping(%p, %lx, %p, %x)\n", 2115 pmap, va, pte, flags)); 2116 2117 /* 2118 * PTE not provided, compute it from pmap and va. 2119 */ 2120 2121 if (pte == NULL) { 2122 pte = pmap_pte(pmap, va); 2123 if (*pte == PG_NV) 2124 return; 2125 } 2126 2127 #ifdef CACHE_HAVE_VAC 2128 if (pmap_aliasmask && (flags & PRM_CFLUSH)) { 2129 2130 /* 2131 * Purge kernel side of VAC to ensure we get the correct 2132 * state of any hardware maintained bits. 2133 */ 2134 2135 DCIS(); 2136 2137 /* 2138 * If this is a non-CI user mapping for the current process, 2139 * flush the VAC. Note that the kernel side was flushed 2140 * above so we don't worry about non-CI kernel mappings. 2141 */ 2142 2143 if (active_user_pmap(pmap) && !pmap_pte_ci(pte)) { 2144 DCIU(); 2145 } 2146 } 2147 #endif 2148 2149 pa = pmap_pte_pa(pte); 2150 #ifdef DEBUG 2151 opte = *pte; 2152 #endif 2153 2154 /* 2155 * Update statistics 2156 */ 2157 2158 if (pmap_pte_w(pte)) 2159 pmap->pm_stats.wired_count--; 2160 pmap->pm_stats.resident_count--; 2161 2162 #if defined(M68040) || defined(M68060) 2163 #if defined(M68020) || defined(M68030) 2164 if (mmutype == MMU_68040) 2165 #endif 2166 if ((flags & PRM_CFLUSH)) { 2167 DCFP(pa); 2168 ICPP(pa); 2169 } 2170 #endif 2171 2172 /* 2173 * Invalidate the PTE after saving the reference modify info. 2174 */ 2175 2176 PMAP_DPRINTF(PDB_REMOVE, ("remove: invalidating pte at %p\n", pte)); 2177 bits = *pte & (PG_U|PG_M); 2178 *pte = PG_NV; 2179 if ((flags & PRM_TFLUSH) && active_pmap(pmap)) 2180 TBIS(va); 2181 2182 /* 2183 * For user mappings decrement the wiring count on 2184 * the PT page. 2185 */ 2186 2187 if (pmap != pmap_kernel()) { 2188 vaddr_t ptpva = trunc_page((vaddr_t)pte); 2189 int refs = pmap_ptpage_delref(ptpva); 2190 #ifdef DEBUG 2191 if (pmapdebug & PDB_WIRING) 2192 pmap_check_wiring("remove", ptpva); 2193 #endif 2194 2195 /* 2196 * If reference count drops to 0, and we're not instructed 2197 * to keep it around, free the PT page. 2198 */ 2199 2200 if (refs == 0 && (flags & PRM_KEEPPTPAGE) == 0) { 2201 #ifdef DIAGNOSTIC 2202 struct pv_header *ptppvh; 2203 struct pv_entry *ptppv; 2204 #endif 2205 paddr_t ptppa; 2206 2207 ptppa = pmap_pte_pa(pmap_pte(pmap_kernel(), ptpva)); 2208 #ifdef DIAGNOSTIC 2209 if (PAGE_IS_MANAGED(ptppa) == 0) 2210 panic("pmap_remove_mapping: unmanaged PT page"); 2211 ptppvh = pa_to_pvh(ptppa); 2212 ptppv = &ptppvh->pvh_first; 2213 if (ptppv->pv_ptste == NULL) 2214 panic("pmap_remove_mapping: ptste == NULL"); 2215 if (ptppv->pv_pmap != pmap_kernel() || 2216 ptppv->pv_va != ptpva || 2217 ptppv->pv_next != NULL) 2218 panic("pmap_remove_mapping: " 2219 "bad PT page pmap %p, va 0x%lx, next %p", 2220 ptppv->pv_pmap, ptppv->pv_va, 2221 ptppv->pv_next); 2222 #endif 2223 pmap_remove_mapping(pmap_kernel(), ptpva, 2224 NULL, PRM_TFLUSH|PRM_CFLUSH); 2225 mutex_enter(&uvm_kernel_object->vmobjlock); 2226 uvm_pagefree(PHYS_TO_VM_PAGE(ptppa)); 2227 mutex_exit(&uvm_kernel_object->vmobjlock); 2228 PMAP_DPRINTF(PDB_REMOVE|PDB_PTPAGE, 2229 ("remove: PT page 0x%lx (0x%lx) freed\n", 2230 ptpva, ptppa)); 2231 } 2232 } 2233 2234 /* 2235 * If this isn't a managed page, we are all done. 2236 */ 2237 2238 if (PAGE_IS_MANAGED(pa) == 0) 2239 return; 2240 2241 /* 2242 * Otherwise remove it from the PV table 2243 * (raise IPL since we may be called at interrupt time). 2244 */ 2245 2246 pvh = pa_to_pvh(pa); 2247 pv = &pvh->pvh_first; 2248 ste = NULL; 2249 s = splvm(); 2250 2251 /* 2252 * If it is the first entry on the list, it is actually 2253 * in the header and we must copy the following entry up 2254 * to the header. Otherwise we must search the list for 2255 * the entry. In either case we free the now unused entry. 2256 */ 2257 2258 if (pmap == pv->pv_pmap && va == pv->pv_va) { 2259 ste = pv->pv_ptste; 2260 ptpmap = pv->pv_ptpmap; 2261 npv = pv->pv_next; 2262 if (npv) { 2263 *pv = *npv; 2264 pmap_free_pv(npv); 2265 } else 2266 pv->pv_pmap = NULL; 2267 } else { 2268 for (npv = pv->pv_next; npv; npv = npv->pv_next) { 2269 if (pmap == npv->pv_pmap && va == npv->pv_va) 2270 break; 2271 pv = npv; 2272 } 2273 #ifdef DEBUG 2274 if (npv == NULL) 2275 panic("pmap_remove: PA not in pv_tab"); 2276 #endif 2277 ste = npv->pv_ptste; 2278 ptpmap = npv->pv_ptpmap; 2279 pv->pv_next = npv->pv_next; 2280 pmap_free_pv(npv); 2281 pvh = pa_to_pvh(pa); 2282 pv = &pvh->pvh_first; 2283 } 2284 2285 #ifdef CACHE_HAVE_VAC 2286 2287 /* 2288 * If only one mapping left we no longer need to cache inhibit 2289 */ 2290 2291 if (pmap_aliasmask && 2292 pv->pv_pmap && pv->pv_next == NULL && (pvh->pvh_attrs & PVH_CI)) { 2293 PMAP_DPRINTF(PDB_CACHE, 2294 ("remove: clearing CI for pa %lx\n", pa)); 2295 pvh->pvh_attrs &= ~PVH_CI; 2296 pmap_changebit(pa, 0, ~PG_CI); 2297 #ifdef DEBUG 2298 if ((pmapdebug & (PDB_CACHE|PDB_PVDUMP)) == 2299 (PDB_CACHE|PDB_PVDUMP)) 2300 pmap_pvdump(pa); 2301 #endif 2302 } 2303 #endif 2304 2305 /* 2306 * If this was a PT page we must also remove the 2307 * mapping from the associated segment table. 2308 */ 2309 2310 if (ste) { 2311 PMAP_DPRINTF(PDB_REMOVE|PDB_PTPAGE, 2312 ("remove: ste was %x@%p pte was %x@%p\n", 2313 *ste, ste, opte, pmap_pte(pmap, va))); 2314 #if defined(M68040) || defined(M68060) 2315 #if defined(M68020) || defined(M68030) 2316 if (mmutype == MMU_68040) 2317 #endif 2318 { 2319 st_entry_t *este = &ste[NPTEPG/SG4_LEV3SIZE]; 2320 2321 while (ste < este) 2322 *ste++ = SG_NV; 2323 #ifdef DEBUG 2324 ste -= NPTEPG/SG4_LEV3SIZE; 2325 #endif 2326 } 2327 #if defined(M68020) || defined(M68030) 2328 else 2329 #endif 2330 #endif 2331 #if defined(M68020) || defined(M68030) 2332 *ste = SG_NV; 2333 #endif 2334 2335 /* 2336 * If it was a user PT page, we decrement the 2337 * reference count on the segment table as well, 2338 * freeing it if it is now empty. 2339 */ 2340 2341 if (ptpmap != pmap_kernel()) { 2342 PMAP_DPRINTF(PDB_REMOVE|PDB_SEGTAB, 2343 ("remove: stab %p, refcnt %d\n", 2344 ptpmap->pm_stab, ptpmap->pm_sref - 1)); 2345 #ifdef DEBUG 2346 if ((pmapdebug & PDB_PARANOIA) && 2347 ptpmap->pm_stab != 2348 (st_entry_t *)trunc_page((vaddr_t)ste)) 2349 panic("remove: bogus ste"); 2350 #endif 2351 if (--(ptpmap->pm_sref) == 0) { 2352 PMAP_DPRINTF(PDB_REMOVE|PDB_SEGTAB, 2353 ("remove: free stab %p\n", 2354 ptpmap->pm_stab)); 2355 uvm_km_free(st_map, (vaddr_t)ptpmap->pm_stab, 2356 M68K_STSIZE, UVM_KMF_WIRED); 2357 ptpmap->pm_stab = Segtabzero; 2358 ptpmap->pm_stpa = Segtabzeropa; 2359 #if defined(M68040) || defined(M68060) 2360 #if defined(M68020) || defined(M68030) 2361 if (mmutype == MMU_68040) 2362 #endif 2363 ptpmap->pm_stfree = protostfree; 2364 #endif 2365 2366 /* 2367 * XXX may have changed segment table 2368 * pointer for current process so 2369 * update now to reload hardware. 2370 */ 2371 2372 if (active_user_pmap(ptpmap)) 2373 PMAP_ACTIVATE(ptpmap, 1); 2374 } 2375 } 2376 pvh->pvh_attrs &= ~PVH_PTPAGE; 2377 ptpmap->pm_ptpages--; 2378 } 2379 2380 /* 2381 * Update saved attributes for managed page 2382 */ 2383 2384 pvh->pvh_attrs |= bits; 2385 splx(s); 2386 } 2387 2388 /* 2389 * pmap_testbit: 2390 * 2391 * Test the modified/referenced bits of a physical page. 2392 */ 2393 /* static */ 2394 bool 2395 pmap_testbit(paddr_t pa, int bit) 2396 { 2397 struct pv_header *pvh; 2398 struct pv_entry *pv; 2399 pt_entry_t *pte; 2400 int s; 2401 2402 pvh = pa_to_pvh(pa); 2403 pv = &pvh->pvh_first; 2404 s = splvm(); 2405 2406 /* 2407 * Check saved info first 2408 */ 2409 2410 if (pvh->pvh_attrs & bit) { 2411 splx(s); 2412 return true; 2413 } 2414 2415 #ifdef CACHE_HAVE_VAC 2416 2417 /* 2418 * Flush VAC to get correct state of any hardware maintained bits. 2419 */ 2420 2421 if (pmap_aliasmask && (bit & (PG_U|PG_M))) 2422 DCIS(); 2423 #endif 2424 2425 /* 2426 * Not found. Check current mappings, returning immediately if 2427 * found. Cache a hit to speed future lookups. 2428 */ 2429 2430 if (pv->pv_pmap != NULL) { 2431 for (; pv; pv = pv->pv_next) { 2432 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2433 if (*pte & bit) { 2434 pvh->pvh_attrs |= bit; 2435 splx(s); 2436 return true; 2437 } 2438 } 2439 } 2440 splx(s); 2441 return false; 2442 } 2443 2444 /* 2445 * pmap_changebit: 2446 * 2447 * Change the modified/referenced bits, or other PTE bits, 2448 * for a physical page. 2449 */ 2450 /* static */ 2451 bool 2452 pmap_changebit(paddr_t pa, int set, int mask) 2453 { 2454 struct pv_header *pvh; 2455 struct pv_entry *pv; 2456 pt_entry_t *pte, npte; 2457 vaddr_t va; 2458 int s; 2459 #if defined(CACHE_HAVE_VAC) || defined(M68040) || defined(M68060) 2460 bool firstpage = true; 2461 #endif 2462 bool r; 2463 2464 PMAP_DPRINTF(PDB_BITS, 2465 ("pmap_changebit(%lx, %x, %x)\n", pa, set, mask)); 2466 2467 pvh = pa_to_pvh(pa); 2468 pv = &pvh->pvh_first; 2469 s = splvm(); 2470 2471 /* 2472 * Clear saved attributes (modify, reference) 2473 */ 2474 2475 r = (pvh->pvh_attrs & ~mask) != 0; 2476 pvh->pvh_attrs &= mask; 2477 2478 /* 2479 * Loop over all current mappings setting/clearing as appropos 2480 * If setting RO do we need to clear the VAC? 2481 */ 2482 2483 if (pv->pv_pmap != NULL) { 2484 #ifdef DEBUG 2485 int toflush = 0; 2486 #endif 2487 for (; pv; pv = pv->pv_next) { 2488 #ifdef DEBUG 2489 toflush |= (pv->pv_pmap == pmap_kernel()) ? 2 : 1; 2490 #endif 2491 va = pv->pv_va; 2492 pte = pmap_pte(pv->pv_pmap, va); 2493 #ifdef CACHE_HAVE_VAC 2494 2495 /* 2496 * Flush VAC to ensure we get correct state of HW bits 2497 * so we don't clobber them. 2498 */ 2499 2500 if (firstpage && pmap_aliasmask) { 2501 firstpage = false; 2502 DCIS(); 2503 } 2504 #endif 2505 npte = (*pte | set) & mask; 2506 if (*pte != npte) { 2507 r = true; 2508 #if defined(M68040) || defined(M68060) 2509 /* 2510 * If we are changing caching status or 2511 * protection make sure the caches are 2512 * flushed (but only once). 2513 */ 2514 if (firstpage && 2515 #if defined(M68020) || defined(M68030) 2516 (mmutype == MMU_68040) && 2517 #endif 2518 ((set == PG_RO) || 2519 (set & PG_CMASK) || 2520 (mask & PG_CMASK) == 0)) { 2521 firstpage = false; 2522 DCFP(pa); 2523 ICPP(pa); 2524 } 2525 #endif 2526 *pte = npte; 2527 if (active_pmap(pv->pv_pmap)) 2528 TBIS(va); 2529 } 2530 } 2531 } 2532 splx(s); 2533 return r; 2534 } 2535 2536 /* 2537 * pmap_enter_ptpage: 2538 * 2539 * Allocate and map a PT page for the specified pmap/va pair. 2540 */ 2541 /* static */ 2542 int 2543 pmap_enter_ptpage(pmap_t pmap, vaddr_t va, bool can_fail) 2544 { 2545 paddr_t ptpa; 2546 struct vm_page *pg; 2547 struct pv_header *pvh; 2548 struct pv_entry *pv; 2549 st_entry_t *ste; 2550 int s; 2551 2552 PMAP_DPRINTF(PDB_FOLLOW|PDB_ENTER|PDB_PTPAGE, 2553 ("pmap_enter_ptpage: pmap %p, va %lx\n", pmap, va)); 2554 2555 /* 2556 * Allocate a segment table if necessary. Note that it is allocated 2557 * from a private map and not pt_map. This keeps user page tables 2558 * aligned on segment boundaries in the kernel address space. 2559 * The segment table is wired down. It will be freed whenever the 2560 * reference count drops to zero. 2561 */ 2562 if (pmap->pm_stab == Segtabzero) { 2563 pmap->pm_stab = (st_entry_t *) 2564 uvm_km_alloc(st_map, M68K_STSIZE, 0, 2565 UVM_KMF_WIRED | UVM_KMF_ZERO | 2566 (can_fail ? UVM_KMF_NOWAIT : 0)); 2567 if (pmap->pm_stab == NULL) { 2568 pmap->pm_stab = Segtabzero; 2569 return ENOMEM; 2570 } 2571 (void) pmap_extract(pmap_kernel(), (vaddr_t)pmap->pm_stab, 2572 (paddr_t *)&pmap->pm_stpa); 2573 #if defined(M68040) || defined(M68060) 2574 #if defined(M68020) || defined(M68030) 2575 if (mmutype == MMU_68040) 2576 #endif 2577 { 2578 pt_entry_t *pte; 2579 2580 pte = pmap_pte(pmap_kernel(), pmap->pm_stab); 2581 *pte = (*pte & ~PG_CMASK) | PG_CI; 2582 pmap->pm_stfree = protostfree; 2583 } 2584 #endif 2585 /* 2586 * XXX may have changed segment table pointer for current 2587 * process so update now to reload hardware. 2588 */ 2589 if (active_user_pmap(pmap)) 2590 PMAP_ACTIVATE(pmap, 1); 2591 2592 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2593 ("enter: pmap %p stab %p(%p)\n", 2594 pmap, pmap->pm_stab, pmap->pm_stpa)); 2595 } 2596 2597 ste = pmap_ste(pmap, va); 2598 #if defined(M68040) || defined(M68060) 2599 /* 2600 * Allocate level 2 descriptor block if necessary 2601 */ 2602 #if defined(M68020) || defined(M68030) 2603 if (mmutype == MMU_68040) 2604 #endif 2605 { 2606 if (*ste == SG_NV) { 2607 int ix; 2608 void *addr; 2609 2610 ix = bmtol2(pmap->pm_stfree); 2611 if (ix == -1) 2612 panic("enter: out of address space"); /* XXX */ 2613 pmap->pm_stfree &= ~l2tobm(ix); 2614 addr = (void *)&pmap->pm_stab[ix*SG4_LEV2SIZE]; 2615 memset(addr, 0, SG4_LEV2SIZE*sizeof(st_entry_t)); 2616 addr = (void *)&pmap->pm_stpa[ix*SG4_LEV2SIZE]; 2617 *ste = (u_int)addr | SG_RW | SG_U | SG_V; 2618 2619 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2620 ("enter: alloc ste2 %d(%p)\n", ix, addr)); 2621 } 2622 ste = pmap_ste2(pmap, va); 2623 /* 2624 * Since a level 2 descriptor maps a block of SG4_LEV3SIZE 2625 * level 3 descriptors, we need a chunk of NPTEPG/SG4_LEV3SIZE 2626 * (16) such descriptors (PAGE_SIZE/SG4_LEV3SIZE bytes) to map a 2627 * PT page--the unit of allocation. We set `ste' to point 2628 * to the first entry of that chunk which is validated in its 2629 * entirety below. 2630 */ 2631 ste = (st_entry_t *)((int)ste & ~(PAGE_SIZE/SG4_LEV3SIZE-1)); 2632 2633 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2634 ("enter: ste2 %p (%p)\n", pmap_ste2(pmap, va), ste)); 2635 } 2636 #endif 2637 va = trunc_page((vaddr_t)pmap_pte(pmap, va)); 2638 2639 /* 2640 * In the kernel we allocate a page from the kernel PT page 2641 * free list and map it into the kernel page table map (via 2642 * pmap_enter). 2643 */ 2644 if (pmap == pmap_kernel()) { 2645 struct kpt_page *kpt; 2646 2647 s = splvm(); 2648 if ((kpt = kpt_free_list) == NULL) { 2649 /* 2650 * No PT pages available. 2651 * Try once to free up unused ones. 2652 */ 2653 PMAP_DPRINTF(PDB_COLLECT, 2654 ("enter: no KPT pages, collecting...\n")); 2655 pmap_collect(); 2656 if ((kpt = kpt_free_list) == NULL) 2657 panic("pmap_enter_ptpage: can't get KPT page"); 2658 } 2659 kpt_free_list = kpt->kpt_next; 2660 kpt->kpt_next = kpt_used_list; 2661 kpt_used_list = kpt; 2662 ptpa = kpt->kpt_pa; 2663 memset((void *)kpt->kpt_va, 0, PAGE_SIZE); 2664 pmap_enter(pmap, va, ptpa, VM_PROT_READ | VM_PROT_WRITE, 2665 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 2666 pmap_update(pmap); 2667 #ifdef DEBUG 2668 if (pmapdebug & (PDB_ENTER|PDB_PTPAGE)) { 2669 int ix = pmap_ste(pmap, va) - pmap_ste(pmap, 0); 2670 2671 printf("enter: add &Sysptmap[%d]: %x (KPT page %lx)\n", 2672 ix, Sysptmap[ix], kpt->kpt_va); 2673 } 2674 #endif 2675 splx(s); 2676 } else { 2677 2678 /* 2679 * For user processes we just allocate a page from the 2680 * VM system. Note that we set the page "wired" count to 1, 2681 * which is what we use to check if the page can be freed. 2682 * See pmap_remove_mapping(). 2683 * 2684 * Count the segment table reference first so that we won't 2685 * lose the segment table when low on memory. 2686 */ 2687 2688 pmap->pm_sref++; 2689 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE, 2690 ("enter: about to alloc UPT pg at %lx\n", va)); 2691 mutex_enter(&uvm_kernel_object->vmobjlock); 2692 while ((pg = uvm_pagealloc(uvm_kernel_object, 2693 va - vm_map_min(kernel_map), 2694 NULL, UVM_PGA_ZERO)) == NULL) { 2695 mutex_exit(&uvm_kernel_object->vmobjlock); 2696 uvm_wait("ptpage"); 2697 mutex_enter(&uvm_kernel_object->vmobjlock); 2698 } 2699 mutex_exit(&uvm_kernel_object->vmobjlock); 2700 pg->flags &= ~(PG_BUSY|PG_FAKE); 2701 UVM_PAGE_OWN(pg, NULL); 2702 ptpa = VM_PAGE_TO_PHYS(pg); 2703 pmap_enter(pmap_kernel(), va, ptpa, 2704 VM_PROT_READ | VM_PROT_WRITE, 2705 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 2706 pmap_update(pmap_kernel()); 2707 } 2708 #if defined(M68040) || defined(M68060) 2709 /* 2710 * Turn off copyback caching of page table pages, 2711 * could get ugly otherwise. 2712 */ 2713 #if defined(M68020) || defined(M68030) 2714 if (mmutype == MMU_68040) 2715 #endif 2716 { 2717 #ifdef DEBUG 2718 pt_entry_t *pte = pmap_pte(pmap_kernel(), va); 2719 if ((pmapdebug & PDB_PARANOIA) && (*pte & PG_CCB) == 0) 2720 printf("%s PT no CCB: kva=%lx ptpa=%lx pte@%p=%x\n", 2721 pmap == pmap_kernel() ? "Kernel" : "User", 2722 va, ptpa, pte, *pte); 2723 #endif 2724 if (pmap_changebit(ptpa, PG_CI, ~PG_CCB)) 2725 DCIS(); 2726 } 2727 #endif 2728 /* 2729 * Locate the PV entry in the kernel for this PT page and 2730 * record the STE address. This is so that we can invalidate 2731 * the STE when we remove the mapping for the page. 2732 */ 2733 pvh = pa_to_pvh(ptpa); 2734 s = splvm(); 2735 if (pvh) { 2736 pv = &pvh->pvh_first; 2737 pvh->pvh_attrs |= PVH_PTPAGE; 2738 do { 2739 if (pv->pv_pmap == pmap_kernel() && pv->pv_va == va) 2740 break; 2741 } while ((pv = pv->pv_next)); 2742 } else { 2743 pv = NULL; 2744 } 2745 #ifdef DEBUG 2746 if (pv == NULL) 2747 panic("pmap_enter_ptpage: PT page not entered"); 2748 #endif 2749 pv->pv_ptste = ste; 2750 pv->pv_ptpmap = pmap; 2751 2752 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE, 2753 ("enter: new PT page at PA %lx, ste at %p\n", ptpa, ste)); 2754 2755 /* 2756 * Map the new PT page into the segment table. 2757 * Also increment the reference count on the segment table if this 2758 * was a user page table page. Note that we don't use vm_map_pageable 2759 * to keep the count like we do for PT pages, this is mostly because 2760 * it would be difficult to identify ST pages in pmap_pageable to 2761 * release them. We also avoid the overhead of vm_map_pageable. 2762 */ 2763 #if defined(M68040) || defined(M68060) 2764 #if defined(M68020) || defined(M68030) 2765 if (mmutype == MMU_68040) 2766 #endif 2767 { 2768 st_entry_t *este; 2769 2770 for (este = &ste[NPTEPG/SG4_LEV3SIZE]; ste < este; ste++) { 2771 *ste = ptpa | SG_U | SG_RW | SG_V; 2772 ptpa += SG4_LEV3SIZE * sizeof(st_entry_t); 2773 } 2774 } 2775 #if defined(M68020) || defined(M68030) 2776 else 2777 *ste = (ptpa & SG_FRAME) | SG_RW | SG_V; 2778 #endif 2779 #else 2780 *ste = (ptpa & SG_FRAME) | SG_RW | SG_V; 2781 #endif 2782 if (pmap != pmap_kernel()) { 2783 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2784 ("enter: stab %p refcnt %d\n", 2785 pmap->pm_stab, pmap->pm_sref)); 2786 } 2787 /* 2788 * Flush stale TLB info. 2789 */ 2790 if (pmap == pmap_kernel()) 2791 TBIAS(); 2792 else 2793 TBIAU(); 2794 pmap->pm_ptpages++; 2795 splx(s); 2796 2797 return 0; 2798 } 2799 2800 /* 2801 * pmap_ptpage_addref: 2802 * 2803 * Add a reference to the specified PT page. 2804 */ 2805 void 2806 pmap_ptpage_addref(vaddr_t ptpva) 2807 { 2808 struct vm_page *pg; 2809 2810 mutex_enter(&uvm_kernel_object->vmobjlock); 2811 pg = uvm_pagelookup(uvm_kernel_object, ptpva - vm_map_min(kernel_map)); 2812 pg->wire_count++; 2813 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2814 ("ptpage addref: pg %p now %d\n", 2815 pg, pg->wire_count)); 2816 mutex_exit(&uvm_kernel_object->vmobjlock); 2817 } 2818 2819 /* 2820 * pmap_ptpage_delref: 2821 * 2822 * Delete a reference to the specified PT page. 2823 */ 2824 int 2825 pmap_ptpage_delref(vaddr_t ptpva) 2826 { 2827 struct vm_page *pg; 2828 int rv; 2829 2830 mutex_enter(&uvm_kernel_object->vmobjlock); 2831 pg = uvm_pagelookup(uvm_kernel_object, ptpva - vm_map_min(kernel_map)); 2832 rv = --pg->wire_count; 2833 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2834 ("ptpage delref: pg %p now %d\n", 2835 pg, pg->wire_count)); 2836 mutex_exit(&uvm_kernel_object->vmobjlock); 2837 return rv; 2838 } 2839 2840 /* 2841 * Routine: pmap_procwr 2842 * 2843 * Function: 2844 * Synchronize caches corresponding to [addr, addr + len) in p. 2845 */ 2846 void 2847 pmap_procwr(struct proc *p, vaddr_t va, size_t len) 2848 { 2849 2850 (void)cachectl1(0x80000004, va, len, p); 2851 } 2852 2853 void 2854 _pmap_set_page_cacheable(pmap_t pmap, vaddr_t va) 2855 { 2856 2857 if (!pmap_ste_v(pmap, va)) 2858 return; 2859 2860 #if defined(M68040) || defined(M68060) 2861 #if defined(M68020) || defined(M68030) 2862 if (mmutype == MMU_68040) { 2863 #endif 2864 if (pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), PG_CCB, ~PG_CI)) 2865 DCIS(); 2866 2867 #if defined(M68020) || defined(M68030) 2868 } else 2869 pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), 0, ~PG_CI); 2870 #endif 2871 #else 2872 pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), 0, ~PG_CI); 2873 #endif 2874 } 2875 2876 void 2877 _pmap_set_page_cacheinhibit(pmap_t pmap, vaddr_t va) 2878 { 2879 2880 if (!pmap_ste_v(pmap, va)) 2881 return; 2882 2883 #if defined(M68040) || defined(M68060) 2884 #if defined(M68020) || defined(M68030) 2885 if (mmutype == MMU_68040) { 2886 #endif 2887 if (pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), PG_CI, ~PG_CCB)) 2888 DCIS(); 2889 #if defined(M68020) || defined(M68030) 2890 } else 2891 pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), PG_CI, ~0); 2892 #endif 2893 #else 2894 pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), PG_CI, ~0); 2895 #endif 2896 } 2897 2898 int 2899 _pmap_page_is_cacheable(pmap_t pmap, vaddr_t va) 2900 { 2901 2902 if (!pmap_ste_v(pmap, va)) 2903 return 0; 2904 2905 return (pmap_pte_ci(pmap_pte(pmap, va)) == 0) ? 1 : 0; 2906 } 2907 2908 #ifdef DEBUG 2909 /* 2910 * pmap_pvdump: 2911 * 2912 * Dump the contents of the PV list for the specified physical page. 2913 */ 2914 void 2915 pmap_pvdump(paddr_t pa) 2916 { 2917 struct pv_header *pvh; 2918 struct pv_entry *pv; 2919 2920 printf("pa %lx", pa); 2921 pvh = pa_to_pvh(pa); 2922 for (pv = &pvh->pvh_first; pv; pv = pv->pv_next) 2923 printf(" -> pmap %p, va %lx, ptste %p, ptpmap %p", 2924 pv->pv_pmap, pv->pv_va, pv->pv_ptste, pv->pv_ptpmap); 2925 printf("\n"); 2926 } 2927 2928 /* 2929 * pmap_check_wiring: 2930 * 2931 * Count the number of valid mappings in the specified PT page, 2932 * and ensure that it is consistent with the number of wirings 2933 * to that page that the VM system has. 2934 */ 2935 void 2936 pmap_check_wiring(const char *str, vaddr_t va) 2937 { 2938 pt_entry_t *pte; 2939 paddr_t pa; 2940 struct vm_page *pg; 2941 int count; 2942 2943 if (!pmap_ste_v(pmap_kernel(), va) || 2944 !pmap_pte_v(pmap_pte(pmap_kernel(), va))) 2945 return; 2946 2947 pa = pmap_pte_pa(pmap_pte(pmap_kernel(), va)); 2948 pg = PHYS_TO_VM_PAGE(pa); 2949 if (pg->wire_count > PAGE_SIZE / sizeof(pt_entry_t)) { 2950 panic("*%s*: 0x%lx: wire count %d", str, va, pg->wire_count); 2951 } 2952 2953 count = 0; 2954 for (pte = (pt_entry_t *)va; pte < (pt_entry_t *)(va + PAGE_SIZE); 2955 pte++) 2956 if (*pte) 2957 count++; 2958 if (pg->wire_count != count) 2959 panic("*%s*: 0x%lx: w%d/a%d", 2960 str, va, pg->wire_count, count); 2961 } 2962 #endif /* DEBUG */ 2963