1 /* $NetBSD: sbc.c,v 1.41 2000/03/18 16:13:23 mycroft Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Scott Reynolds. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains only the machine-dependent parts of the mac68k 31 * NCR 5380 SCSI driver. (Autoconfig stuff and PDMA functions.) 32 * The machine-independent parts are in ncr5380sbc.c 33 * 34 * Supported hardware includes: 35 * Macintosh II family 5380-based controller 36 * 37 * Credits, history: 38 * 39 * Scott Reynolds wrote this module, based on work by Allen Briggs 40 * (mac68k), Gordon W. Ross and David Jones (sun3), and Leo Weppelman 41 * (atari). Thanks to Allen for supplying crucial interpretation of the 42 * NetBSD/mac68k 1.1 'ncrscsi' driver. Also, Allen, Gordon, and Jason 43 * Thorpe all helped to refine this code, and were considerable sources 44 * of moral support. 45 */ 46 #include "opt_ddb.h" 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsipi_debug.h> 61 #include <dev/scsipi/scsiconf.h> 62 63 #include <dev/ic/ncr5380reg.h> 64 #include <dev/ic/ncr5380var.h> 65 66 #include <machine/cpu.h> 67 #include <machine/viareg.h> 68 69 #include <mac68k/dev/sbcreg.h> 70 #include <mac68k/dev/sbcvar.h> 71 72 /* SBC_DEBUG -- relies on DDB */ 73 #ifdef SBC_DEBUG 74 # define SBC_DB_INTR 0x01 75 # define SBC_DB_DMA 0x02 76 # define SBC_DB_REG 0x04 77 # define SBC_DB_BREAK 0x08 78 # ifndef DDB 79 # define Debugger() printf("Debug: sbc.c:%d\n", __LINE__) 80 # endif 81 # define SBC_BREAK \ 82 do { if (sbc_debug & SBC_DB_BREAK) Debugger(); } while (0) 83 #else 84 # define SBC_BREAK 85 #endif 86 87 88 int sbc_debug = 0 /* | SBC_DB_INTR | SBC_DB_DMA */; 89 int sbc_link_flags = 0 /* | SDEV_DB2 */; 90 int sbc_options = 0 /* | SBC_PDMA */; 91 92 extern label_t *nofault; 93 extern caddr_t m68k_fault_addr; 94 95 static int sbc_wait_busy __P((struct ncr5380_softc *)); 96 static int sbc_ready __P((struct ncr5380_softc *)); 97 static int sbc_wait_dreq __P((struct ncr5380_softc *)); 98 99 100 /*** 101 * General support for Mac-specific SCSI logic. 102 ***/ 103 104 /* These are used in the following inline functions. */ 105 int sbc_wait_busy_timo = 1000 * 5000; /* X2 = 10 S. */ 106 int sbc_ready_timo = 1000 * 5000; /* X2 = 10 S. */ 107 int sbc_wait_dreq_timo = 1000 * 5000; /* X2 = 10 S. */ 108 109 /* Return zero on success. */ 110 static __inline__ int 111 sbc_wait_busy(sc) 112 struct ncr5380_softc *sc; 113 { 114 int timo = sbc_wait_busy_timo; 115 for (;;) { 116 if (SCI_BUSY(sc)) { 117 timo = 0; /* return 0 */ 118 break; 119 } 120 if (--timo < 0) 121 break; /* return -1 */ 122 delay(2); 123 } 124 return (timo); 125 } 126 127 static __inline__ int 128 sbc_ready(sc) 129 struct ncr5380_softc *sc; 130 { 131 int timo = sbc_ready_timo; 132 133 for (;;) { 134 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 135 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 136 timo = 0; 137 break; 138 } 139 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) 140 || (SCI_BUSY(sc) == 0)) { 141 timo = -1; 142 break; 143 } 144 if (--timo < 0) 145 break; /* return -1 */ 146 delay(2); 147 } 148 return (timo); 149 } 150 151 static __inline__ int 152 sbc_wait_dreq(sc) 153 struct ncr5380_softc *sc; 154 { 155 int timo = sbc_wait_dreq_timo; 156 157 for (;;) { 158 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 159 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 160 timo = 0; 161 break; 162 } 163 if (--timo < 0) 164 break; /* return -1 */ 165 delay(2); 166 } 167 return (timo); 168 } 169 170 void 171 sbc_irq_intr(p) 172 void *p; 173 { 174 struct ncr5380_softc *ncr_sc = p; 175 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 176 int claimed = 0; 177 178 /* How we ever arrive here without IRQ set is a mystery... */ 179 if (*ncr_sc->sci_csr & SCI_CSR_INT) { 180 #ifdef SBC_DEBUG 181 if (sbc_debug & SBC_DB_INTR) 182 decode_5380_intr(ncr_sc); 183 #endif 184 if (!cold) 185 claimed = ncr5380_intr(ncr_sc); 186 if (!claimed) { 187 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) 188 && ((*ncr_sc->sci_bus_csr & ~SCI_BUS_RST) == 0)) { 189 SCI_CLR_INTR(ncr_sc); /* RST interrupt */ 190 if (sc->sc_clrintr) 191 (*sc->sc_clrintr)(ncr_sc); 192 } 193 #ifdef SBC_DEBUG 194 else { 195 printf("%s: spurious intr\n", 196 ncr_sc->sc_dev.dv_xname); 197 SBC_BREAK; 198 } 199 #endif 200 } 201 } 202 } 203 204 #ifdef SBC_DEBUG 205 void 206 decode_5380_intr(ncr_sc) 207 struct ncr5380_softc *ncr_sc; 208 { 209 u_int8_t csr = *ncr_sc->sci_csr; 210 u_int8_t bus_csr = *ncr_sc->sci_bus_csr; 211 212 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && 213 ((bus_csr & ~(SCI_BUS_MSG | SCI_BUS_CD | SCI_BUS_IO | SCI_BUS_DBP)) == SCI_BUS_SEL)) { 214 if (csr & SCI_BUS_IO) 215 printf("%s: reselect\n", ncr_sc->sc_dev.dv_xname); 216 else 217 printf("%s: select\n", ncr_sc->sc_dev.dv_xname); 218 } else if (((csr & ~SCI_CSR_ACK) == (SCI_CSR_DONE | SCI_CSR_INT)) && 219 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 220 printf("%s: dma eop\n", ncr_sc->sc_dev.dv_xname); 221 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && 222 ((bus_csr & ~SCI_BUS_RST) == 0)) 223 printf("%s: bus reset\n", ncr_sc->sc_dev.dv_xname); 224 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && 225 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_SEL)) == SCI_BUS_BSY)) 226 printf("%s: parity error\n", ncr_sc->sc_dev.dv_xname); 227 else if (((csr & ~SCI_CSR_ATN) == SCI_CSR_INT) && 228 ((bus_csr & (SCI_BUS_RST | SCI_BUS_BSY | SCI_BUS_REQ | SCI_BUS_SEL)) == (SCI_BUS_BSY | SCI_BUS_REQ))) 229 printf("%s: phase mismatch\n", ncr_sc->sc_dev.dv_xname); 230 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) && 231 (bus_csr == 0)) 232 printf("%s: disconnect\n", ncr_sc->sc_dev.dv_xname); 233 else 234 printf("%s: unknown intr: csr=%x, bus_csr=%x\n", 235 ncr_sc->sc_dev.dv_xname, csr, bus_csr); 236 } 237 #endif 238 239 240 /*** 241 * The following code implements polled PDMA. 242 ***/ 243 244 int 245 sbc_pdma_in(ncr_sc, phase, datalen, data) 246 struct ncr5380_softc *ncr_sc; 247 int phase; 248 int datalen; 249 u_char *data; 250 { 251 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 252 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 253 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 254 int resid, s; 255 256 if (datalen < ncr_sc->sc_min_dma_len || 257 (sc->sc_options & SBC_PDMA) == 0) 258 return ncr5380_pio_in(ncr_sc, phase, datalen, data); 259 260 s = splbio(); 261 if (sbc_wait_busy(ncr_sc)) { 262 splx(s); 263 return 0; 264 } 265 266 *ncr_sc->sci_mode |= SCI_MODE_DMA; 267 *ncr_sc->sci_irecv = 0; 268 269 #define R4 *((u_int32_t *)data)++ = *long_data 270 #define R1 *((u_int8_t *)data)++ = *byte_data 271 for (resid = datalen; resid >= 128; resid -= 128) { 272 if (sbc_ready(ncr_sc)) 273 goto interrupt; 274 R4; R4; R4; R4; R4; R4; R4; R4; 275 R4; R4; R4; R4; R4; R4; R4; R4; 276 R4; R4; R4; R4; R4; R4; R4; R4; 277 R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */ 278 } 279 while (resid) { 280 if (sbc_ready(ncr_sc)) 281 goto interrupt; 282 R1; 283 resid--; 284 } 285 #undef R4 286 #undef R1 287 288 interrupt: 289 SCI_CLR_INTR(ncr_sc); 290 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 291 *ncr_sc->sci_icmd = 0; 292 splx(s); 293 return (datalen - resid); 294 } 295 296 int 297 sbc_pdma_out(ncr_sc, phase, datalen, data) 298 struct ncr5380_softc *ncr_sc; 299 int phase; 300 int datalen; 301 u_char *data; 302 { 303 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 304 volatile u_int32_t *long_data = (u_int32_t *)sc->sc_drq_addr; 305 volatile u_int8_t *byte_data = (u_int8_t *)sc->sc_nodrq_addr; 306 label_t faultbuf; 307 int resid, s; 308 u_int8_t icmd; 309 310 #if 1 311 /* Work around lame gcc initialization bug */ 312 (void)&data; 313 #endif 314 315 if (datalen < ncr_sc->sc_min_dma_len || 316 (sc->sc_options & SBC_PDMA) == 0) 317 return ncr5380_pio_out(ncr_sc, phase, datalen, data); 318 319 s = splbio(); 320 if (sbc_wait_busy(ncr_sc)) { 321 splx(s); 322 return 0; 323 } 324 325 icmd = *(ncr_sc->sci_icmd) & SCI_ICMD_RMASK; 326 *ncr_sc->sci_icmd = icmd | SCI_ICMD_DATA; 327 *ncr_sc->sci_mode |= SCI_MODE_DMA; 328 *ncr_sc->sci_dma_send = 0; 329 330 /* 331 * Setup for a possible bus error caused by SCSI controller 332 * switching out of DATA OUT before we're done with the 333 * current transfer. (See comment before sbc_drq_intr().) 334 */ 335 nofault = &faultbuf; 336 337 if (setjmp(nofault)) { 338 printf("buf = 0x%lx, fault = 0x%lx\n", 339 (u_long)sc->sc_drq_addr, (u_long)m68k_fault_addr); 340 panic("Unexpected bus error in sbc_pdma_out()"); 341 } 342 343 #define W1 *byte_data = *((u_int8_t *)data)++ 344 #define W4 *long_data = *((u_int32_t *)data)++ 345 for (resid = datalen; resid >= 64; resid -= 64) { 346 if (sbc_ready(ncr_sc)) 347 goto interrupt; 348 W1; 349 if (sbc_ready(ncr_sc)) 350 goto interrupt; 351 W1; 352 if (sbc_ready(ncr_sc)) 353 goto interrupt; 354 W1; 355 if (sbc_ready(ncr_sc)) 356 goto interrupt; 357 W1; 358 if (sbc_ready(ncr_sc)) 359 goto interrupt; 360 W4; W4; W4; W4; 361 W4; W4; W4; W4; 362 W4; W4; W4; W4; 363 W4; W4; W4; 364 } 365 while (resid) { 366 if (sbc_ready(ncr_sc)) 367 goto interrupt; 368 W1; 369 resid--; 370 } 371 #undef W1 372 #undef W4 373 if (sbc_wait_dreq(ncr_sc)) 374 printf("%s: timeout waiting for DREQ.\n", 375 ncr_sc->sc_dev.dv_xname); 376 377 *byte_data = 0; 378 goto done; 379 380 interrupt: 381 if ((*ncr_sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) { 382 *ncr_sc->sci_icmd = icmd & ~SCI_ICMD_DATA; 383 --resid; 384 } 385 386 done: 387 SCI_CLR_INTR(ncr_sc); 388 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 389 *ncr_sc->sci_icmd = icmd; 390 splx(s); 391 return (datalen - resid); 392 } 393 394 395 /*** 396 * The following code implements interrupt-driven PDMA. 397 ***/ 398 399 /* 400 * This is the meat of the PDMA transfer. 401 * When we get here, we shove data as fast as the mac can take it. 402 * We depend on several things: 403 * * All macs after the Mac Plus that have a 5380 chip should have a general 404 * logic IC that handshakes data for blind transfers. 405 * * If the SCSI controller finishes sending/receiving data before we do, 406 * the same general logic IC will generate a /BERR for us in short order. 407 * * The fault address for said /BERR minus the base address for the 408 * transfer will be the amount of data that was actually written. 409 * 410 * We use the nofault flag and the setjmp/longjmp in locore.s so we can 411 * detect and handle the bus error for early termination of a command. 412 * This is usually caused by a disconnecting target. 413 */ 414 void 415 sbc_drq_intr(p) 416 void *p; 417 { 418 struct sbc_softc *sc = (struct sbc_softc *)p; 419 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)p; 420 struct sci_req *sr = ncr_sc->sc_current; 421 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 422 label_t faultbuf; 423 volatile u_int32_t *long_drq; 424 u_int32_t *long_data; 425 volatile u_int8_t *drq; 426 u_int8_t *data; 427 int count, dcount, resid; 428 u_int8_t tmp; 429 430 /* Work around lame gcc initialization bug */ 431 (void)&drq; 432 433 /* 434 * If we're not ready to xfer data, or have no more, just return. 435 */ 436 if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0) 437 return; 438 439 #ifdef SBC_DEBUG 440 if (sbc_debug & SBC_DB_INTR) 441 printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n", 442 ncr_sc->sc_dev.dv_xname, dh->dh_len, dh->dh_flags); 443 #endif 444 445 /* 446 * Setup for a possible bus error caused by SCSI controller 447 * switching out of DATA-IN/OUT before we're done with the 448 * current transfer. 449 */ 450 nofault = &faultbuf; 451 452 if (setjmp(nofault)) { 453 nofault = (label_t *)0; 454 if ((dh->dh_flags & SBC_DH_DONE) == 0) { 455 count = (( (u_long)m68k_fault_addr 456 - (u_long)sc->sc_drq_addr)); 457 458 if ((count < 0) || (count > dh->dh_len)) { 459 printf("%s: complete=0x%x (pending 0x%x)\n", 460 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 461 panic("something is wrong"); 462 } 463 464 dh->dh_addr += count; 465 dh->dh_len -= count; 466 } else 467 count = 0; 468 469 #ifdef SBC_DEBUG 470 if (sbc_debug & SBC_DB_INTR) 471 printf("%s: drq /berr, complete=0x%x (pending 0x%x)\n", 472 ncr_sc->sc_dev.dv_xname, count, dh->dh_len); 473 #endif 474 m68k_fault_addr = 0; 475 476 return; 477 } 478 479 if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */ 480 dcount = 0; 481 482 /* 483 * Get the source address aligned. 484 */ 485 resid = 486 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 487 if (count && count < 4) { 488 drq = (volatile u_int8_t *)sc->sc_drq_addr; 489 data = (u_int8_t *)dh->dh_addr; 490 491 #define W1 *drq++ = *data++ 492 while (count) { 493 W1; count--; 494 } 495 #undef W1 496 dh->dh_addr += resid; 497 dh->dh_len -= resid; 498 } 499 500 /* 501 * Start the transfer. 502 */ 503 while (dh->dh_len) { 504 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 505 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 506 long_data = (u_int32_t *)dh->dh_addr; 507 508 #define W4 *long_drq++ = *long_data++ 509 while (count >= 64) { 510 W4; W4; W4; W4; W4; W4; W4; W4; 511 W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */ 512 count -= 64; 513 } 514 while (count >= 4) { 515 W4; count -= 4; 516 } 517 #undef W4 518 data = (u_int8_t *)long_data; 519 drq = (u_int8_t *)long_drq; 520 521 #define W1 *drq++ = *data++ 522 while (count) { 523 W1; count--; 524 } 525 #undef W1 526 dh->dh_len -= dcount; 527 dh->dh_addr += dcount; 528 } 529 dh->dh_flags |= SBC_DH_DONE; 530 531 /* 532 * XXX -- Read a byte from the SBC to trigger a /BERR. 533 * This seems to be necessary for us to notice that 534 * the target has disconnected. Ick. 06 jun 1996 (sr) 535 */ 536 if (dcount >= MAX_DMA_LEN) 537 drq = (volatile u_int8_t *)sc->sc_drq_addr; 538 tmp = *drq; 539 } else { /* Data In */ 540 /* 541 * Get the dest address aligned. 542 */ 543 resid = 544 count = min(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3)); 545 if (count && count < 4) { 546 data = (u_int8_t *)dh->dh_addr; 547 drq = (volatile u_int8_t *)sc->sc_drq_addr; 548 549 #define R1 *data++ = *drq++ 550 while (count) { 551 R1; count--; 552 } 553 #undef R1 554 dh->dh_addr += resid; 555 dh->dh_len -= resid; 556 } 557 558 /* 559 * Start the transfer. 560 */ 561 while (dh->dh_len) { 562 dcount = count = min(dh->dh_len, MAX_DMA_LEN); 563 long_data = (u_int32_t *)dh->dh_addr; 564 long_drq = (volatile u_int32_t *)sc->sc_drq_addr; 565 566 #define R4 *long_data++ = *long_drq++ 567 while (count >= 64) { 568 R4; R4; R4; R4; R4; R4; R4; R4; 569 R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */ 570 count -= 64; 571 } 572 while (count >= 4) { 573 R4; count -= 4; 574 } 575 #undef R4 576 data = (u_int8_t *)long_data; 577 drq = (volatile u_int8_t *)long_drq; 578 579 #define R1 *data++ = *drq++ 580 while (count) { 581 R1; count--; 582 } 583 #undef R1 584 dh->dh_len -= dcount; 585 dh->dh_addr += dcount; 586 } 587 dh->dh_flags |= SBC_DH_DONE; 588 } 589 590 /* 591 * OK. No bus error occurred above. Clear the nofault flag 592 * so we no longer short-circuit bus errors. 593 */ 594 nofault = (label_t *)0; 595 596 #ifdef SBC_DEBUG 597 if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR)) 598 printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n", 599 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 600 *ncr_sc->sci_bus_csr); 601 #endif 602 } 603 604 void 605 sbc_dma_alloc(ncr_sc) 606 struct ncr5380_softc *ncr_sc; 607 { 608 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 609 struct sci_req *sr = ncr_sc->sc_current; 610 struct scsipi_xfer *xs = sr->sr_xs; 611 struct sbc_pdma_handle *dh; 612 int i, xlen; 613 614 #ifdef DIAGNOSTIC 615 if (sr->sr_dma_hand != NULL) 616 panic("sbc_dma_alloc: already have PDMA handle"); 617 #endif 618 619 /* Polled transfers shouldn't allocate a PDMA handle. */ 620 if (sr->sr_flags & SR_IMMED) 621 return; 622 623 xlen = ncr_sc->sc_datalen; 624 625 /* Make sure our caller checked sc_min_dma_len. */ 626 if (xlen < MIN_DMA_LEN) 627 panic("sbc_dma_alloc: len=0x%x\n", xlen); 628 629 /* 630 * Find free PDMA handle. Guaranteed to find one since we 631 * have as many PDMA handles as the driver has processes. 632 * (instances?) 633 */ 634 for (i = 0; i < SCI_OPENINGS; i++) { 635 if ((sc->sc_pdma[i].dh_flags & SBC_DH_BUSY) == 0) 636 goto found; 637 } 638 panic("sbc: no free PDMA handles"); 639 found: 640 dh = &sc->sc_pdma[i]; 641 dh->dh_flags = SBC_DH_BUSY; 642 dh->dh_addr = ncr_sc->sc_dataptr; 643 dh->dh_len = xlen; 644 645 /* Copy the 'write' flag for convenience. */ 646 if (xs->xs_control & XS_CTL_DATA_OUT) 647 dh->dh_flags |= SBC_DH_OUT; 648 649 sr->sr_dma_hand = dh; 650 } 651 652 void 653 sbc_dma_free(ncr_sc) 654 struct ncr5380_softc *ncr_sc; 655 { 656 struct sci_req *sr = ncr_sc->sc_current; 657 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 658 659 #ifdef DIAGNOSTIC 660 if (sr->sr_dma_hand == NULL) 661 panic("sbc_dma_free: no DMA handle"); 662 #endif 663 664 if (ncr_sc->sc_state & NCR_DOINGDMA) 665 panic("sbc_dma_free: free while in progress"); 666 667 if (dh->dh_flags & SBC_DH_BUSY) { 668 dh->dh_flags = 0; 669 dh->dh_addr = NULL; 670 dh->dh_len = 0; 671 } 672 sr->sr_dma_hand = NULL; 673 } 674 675 void 676 sbc_dma_poll(ncr_sc) 677 struct ncr5380_softc *ncr_sc; 678 { 679 struct sci_req *sr = ncr_sc->sc_current; 680 681 /* 682 * We shouldn't arrive here; if SR_IMMED is set, then 683 * dma_alloc() should have refused to allocate a handle 684 * for the transfer. This forces the polled PDMA code 685 * to handle the request... 686 */ 687 #ifdef SBC_DEBUG 688 if (sbc_debug & SBC_DB_DMA) 689 printf("%s: lost DRQ interrupt?\n", ncr_sc->sc_dev.dv_xname); 690 #endif 691 sr->sr_flags |= SR_OVERDUE; 692 } 693 694 void 695 sbc_dma_setup(ncr_sc) 696 struct ncr5380_softc *ncr_sc; 697 { 698 /* Not needed; we don't have real DMA */ 699 } 700 701 void 702 sbc_dma_start(ncr_sc) 703 struct ncr5380_softc *ncr_sc; 704 { 705 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 706 struct sci_req *sr = ncr_sc->sc_current; 707 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 708 709 /* 710 * Match bus phase, clear pending interrupts, set DMA mode, and 711 * assert data bus (for writing only), then start the transfer. 712 */ 713 if (dh->dh_flags & SBC_DH_OUT) { 714 *ncr_sc->sci_tcmd = PHASE_DATA_OUT; 715 SCI_CLR_INTR(ncr_sc); 716 if (sc->sc_clrintr) 717 (*sc->sc_clrintr)(ncr_sc); 718 *ncr_sc->sci_mode |= SCI_MODE_DMA; 719 *ncr_sc->sci_icmd = SCI_ICMD_DATA; 720 *ncr_sc->sci_dma_send = 0; 721 } else { 722 *ncr_sc->sci_tcmd = PHASE_DATA_IN; 723 SCI_CLR_INTR(ncr_sc); 724 if (sc->sc_clrintr) 725 (*sc->sc_clrintr)(ncr_sc); 726 *ncr_sc->sci_mode |= SCI_MODE_DMA; 727 *ncr_sc->sci_icmd = 0; 728 *ncr_sc->sci_irecv = 0; 729 } 730 ncr_sc->sc_state |= NCR_DOINGDMA; 731 732 #ifdef SBC_DEBUG 733 if (sbc_debug & SBC_DB_DMA) 734 printf("%s: PDMA started, va=%p, len=0x%x\n", 735 ncr_sc->sc_dev.dv_xname, dh->dh_addr, dh->dh_len); 736 #endif 737 } 738 739 void 740 sbc_dma_eop(ncr_sc) 741 struct ncr5380_softc *ncr_sc; 742 { 743 /* Not used; the EOP pin is wired high (GMFH, pp. 389-390) */ 744 } 745 746 void 747 sbc_dma_stop(ncr_sc) 748 struct ncr5380_softc *ncr_sc; 749 { 750 struct sbc_softc *sc = (struct sbc_softc *)ncr_sc; 751 struct sci_req *sr = ncr_sc->sc_current; 752 struct sbc_pdma_handle *dh = sr->sr_dma_hand; 753 int ntrans; 754 755 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 756 #ifdef SBC_DEBUG 757 if (sbc_debug & SBC_DB_DMA) 758 printf("%s: dma_stop: DMA not running\n", 759 ncr_sc->sc_dev.dv_xname); 760 #endif 761 return; 762 } 763 ncr_sc->sc_state &= ~NCR_DOINGDMA; 764 765 if ((ncr_sc->sc_state & NCR_ABORTING) == 0) { 766 ntrans = ncr_sc->sc_datalen - dh->dh_len; 767 768 #ifdef SBC_DEBUG 769 if (sbc_debug & SBC_DB_DMA) 770 printf("%s: dma_stop: ntrans=0x%x\n", 771 ncr_sc->sc_dev.dv_xname, ntrans); 772 #endif 773 774 if (ntrans > ncr_sc->sc_datalen) 775 panic("sbc_dma_stop: excess transfer\n"); 776 777 /* Adjust data pointer */ 778 ncr_sc->sc_dataptr += ntrans; 779 ncr_sc->sc_datalen -= ntrans; 780 781 /* Clear any pending interrupts. */ 782 SCI_CLR_INTR(ncr_sc); 783 if (sc->sc_clrintr) 784 (*sc->sc_clrintr)(ncr_sc); 785 } 786 787 /* Put SBIC back into PIO mode. */ 788 *ncr_sc->sci_mode &= ~SCI_MODE_DMA; 789 *ncr_sc->sci_icmd = 0; 790 791 #ifdef SBC_DEBUG 792 if (sbc_debug & SBC_DB_REG) 793 printf("%s: dma_stop: csr=0x%x, bus_csr=0x%x\n", 794 ncr_sc->sc_dev.dv_xname, *ncr_sc->sci_csr, 795 *ncr_sc->sci_bus_csr); 796 #endif 797 } 798