1 /* $NetBSD: zs.c,v 1.35 2002/03/17 19:40:43 atatat Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1998 Bill Studenmund 5 * Copyright (c) 1995 Gordon W. Ross 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 4. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Gordon Ross 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Zilog Z8530 Dual UART driver (machine-dependent part) 36 * 37 * Runs two serial lines per chip using slave drivers. 38 * Plain tty/async lines use the zs_async slave. 39 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 40 * Other ports use their own mice & keyboard slaves. 41 * 42 * Credits & history: 43 * 44 * With NetBSD 1.1, port-mac68k started using a port of the port-sparc 45 * (port-sun3?) zs.c driver (which was in turn based on code in the 46 * Berkeley 4.4 Lite release). Bill Studenmund did the port, with 47 * help from Allen Briggs and Gordon Ross <gwr@netbsd.org>. Noud de 48 * Brouwer field-tested the driver at a local ISP. 49 * 50 * Bill Studenmund and Gordon Ross then ported the machine-independant 51 * z8530 driver to work with port-mac68k. NetBSD 1.2 contained an 52 * intermediate version (mac68k using a local, patched version of 53 * the m.i. drivers), with NetBSD 1.3 containing a full version. 54 */ 55 56 #include "opt_ddb.h" 57 #include "opt_mac68k.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/proc.h> 62 #include <sys/device.h> 63 #include <sys/conf.h> 64 #include <sys/file.h> 65 #include <sys/ioctl.h> 66 #include <sys/tty.h> 67 #include <sys/time.h> 68 #include <sys/kernel.h> 69 #include <sys/syslog.h> 70 71 #include <machine/autoconf.h> 72 #include <machine/cpu.h> 73 #include <machine/psc.h> 74 #include <machine/viareg.h> 75 76 #include <dev/cons.h> 77 #include <dev/ic/z8530reg.h> 78 #include <machine/z8530var.h> 79 #include <mac68k/dev/zs_cons.h> 80 81 /* Are these in a header file anywhere? */ 82 /* Booter flags interface */ 83 #define ZSMAC_RAW 0x01 84 #define ZSMAC_LOCALTALK 0x02 85 86 #define PCLK (9600 * 384) 87 88 #include "zsc.h" /* get the # of zs chips defined */ 89 90 /* 91 * Some warts needed by z8530tty.c - 92 */ 93 int zs_def_cflag = (CREAD | CS8 | HUPCL); 94 int zs_major = 12; 95 96 /* 97 * abort detection on console will now timeout after iterating on a loop 98 * the following # of times. Cheep hack. Also, abort detection is turned 99 * off after a timeout (i.e. maybe there's not a terminal hooked up). 100 */ 101 #define ZSABORT_DELAY 3000000 102 103 /* 104 * Define interrupt levels. 105 */ 106 #define ZSHARD_PRI 4 /* Wired on the CPU board... */ 107 /* 108 * Serial port cards with zs chips on them are actually at the 109 * NuBus interrupt level, which is lower than 4. But blocking 110 * level 4 interrupts will block those interrupts too, so level 111 * 4 is fine. 112 */ 113 114 /* The layout of this is hardware-dependent (padding, order). */ 115 struct zschan { 116 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 117 u_char zc_xxx0; 118 u_char zc_xxx1; /* part of the other channel lives here! */ 119 u_char zc_xxx2; /* Yea Apple! */ 120 volatile u_char zc_data; /* data */ 121 u_char zc_xxx3; 122 u_char zc_xxx4; 123 u_char zc_xxx5; 124 }; 125 126 /* Saved PROM mappings */ 127 static char *zsaddr[NZSC]; /* See zs_init() */ 128 /* Flags from cninit() */ 129 static int zs_hwflags[NZSC][2]; 130 /* Default speed for each channel */ 131 static int zs_defspeed[NZSC][2] = { 132 { 9600, /* tty00 */ 133 9600 }, /* tty01 */ 134 }; 135 /* console stuff */ 136 void *zs_conschan = 0; 137 int zs_consunit; 138 #ifdef ZS_CONSOLE_ABORT 139 int zs_cons_canabort = 1; 140 #else 141 int zs_cons_canabort = 0; 142 #endif /* ZS_CONSOLE_ABORT*/ 143 /* device to which the console is attached--if serial. */ 144 dev_t mac68k_zsdev; 145 /* Mac stuff */ 146 volatile unsigned char *sccA = 0; 147 148 int zs_cn_check_speed __P((int bps)); 149 150 /* 151 * Even though zsparam will set up the clock multiples, etc., we 152 * still set them here as: 1) mice & keyboards don't use zsparam, 153 * and 2) the console stuff uses these defaults before device 154 * attach. 155 */ 156 157 static u_char zs_init_reg[16] = { 158 0, /* 0: CMD (reset, etc.) */ 159 0, /* 1: No interrupts yet. */ 160 0x18 + ZSHARD_PRI, /* IVECT */ 161 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 162 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 163 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 164 0, /* 6: TXSYNC/SYNCLO */ 165 0, /* 7: RXSYNC/SYNCHI */ 166 0, /* 8: alias for data port */ 167 ZSWR9_MASTER_IE, 168 0, /*10: Misc. TX/RX control bits */ 169 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 170 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 171 0, /*13: BAUDHI (default=9600) */ 172 ZSWR14_BAUD_ENA, 173 ZSWR15_BREAK_IE, 174 }; 175 176 struct zschan * 177 zs_get_chan_addr(zsc_unit, channel) 178 int zsc_unit, channel; 179 { 180 char *addr; 181 struct zschan *zc; 182 183 if (zsc_unit >= NZSC) 184 return NULL; 185 addr = zsaddr[zsc_unit]; 186 if (addr == NULL) 187 return NULL; 188 if (channel == 0) { 189 zc = (struct zschan *)(addr + 2); 190 /* handle the fact the ports are intertwined. */ 191 } else { 192 zc = (struct zschan *)(addr); 193 } 194 return (zc); 195 } 196 197 198 /* Find PROM mappings (for console support). */ 199 int zsinited = 0; /* 0 = not, 1 = inited, not attached, 2= attached */ 200 201 void 202 zs_init() 203 { 204 if ((zsinited == 2)&&(zsaddr[0] != (char *) sccA)) 205 panic("Moved zs0 address after attached!"); 206 zsaddr[0] = (char *) sccA; 207 zsinited = 1; 208 if (zs_conschan != 0){ /* we might have moved io under the console */ 209 zs_conschan = zs_get_chan_addr(0, zs_consunit); 210 /* so recalc the console port */ 211 } 212 } 213 214 215 /**************************************************************** 216 * Autoconfig 217 ****************************************************************/ 218 219 /* Definition of the driver for autoconfig. */ 220 static int zsc_match __P((struct device *, struct cfdata *, void *)); 221 static void zsc_attach __P((struct device *, struct device *, void *)); 222 static int zsc_print __P((void *, const char *name)); 223 224 struct cfattach zsc_ca = { 225 sizeof(struct zsc_softc), zsc_match, zsc_attach 226 }; 227 228 extern struct cfdriver zsc_cd; 229 230 int zshard __P((void *)); 231 int zssoft __P((void *)); 232 233 234 /* 235 * Is the zs chip present? 236 */ 237 static int 238 zsc_match(parent, cf, aux) 239 struct device *parent; 240 struct cfdata *cf; 241 void *aux; 242 { 243 return 1; 244 } 245 246 /* 247 * Attach a found zs. 248 * 249 * Match slave number to zs unit number, so that misconfiguration will 250 * not set up the keyboard as ttya, etc. 251 */ 252 static void 253 zsc_attach(parent, self, aux) 254 struct device *parent; 255 struct device *self; 256 void *aux; 257 { 258 struct zsc_softc *zsc = (void *) self; 259 struct zsc_attach_args zsc_args; 260 volatile struct zschan *zc; 261 struct xzs_chanstate *xcs; 262 struct zs_chanstate *cs; 263 int zsc_unit, channel; 264 int s, chip, theflags; 265 266 if (!zsinited) 267 zs_init(); 268 zsinited = 2; 269 270 zsc_unit = zsc->zsc_dev.dv_unit; 271 272 /* Make sure everything's inited ok. */ 273 if (zsaddr[zsc_unit] == NULL) 274 panic("zs_attach: zs%d not mapped\n", zsc_unit); 275 276 chip = 0; /* We'll deal with chip types post 1.2 */ 277 printf(" chip type %d \n",chip); 278 279 /* 280 * Initialize software state for each channel. 281 */ 282 for (channel = 0; channel < 2; channel++) { 283 zsc_args.channel = channel; 284 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 285 xcs = &zsc->xzsc_xcs_store[channel]; 286 cs = &xcs->xzs_cs; 287 zsc->zsc_cs[channel] = cs; 288 289 cs->cs_channel = channel; 290 cs->cs_private = NULL; 291 cs->cs_ops = &zsops_null; 292 293 zc = zs_get_chan_addr(zsc_unit, channel); 294 cs->cs_reg_csr = &zc->zc_csr; 295 cs->cs_reg_data = &zc->zc_data; 296 297 bcopy(zs_init_reg, cs->cs_creg, 16); 298 bcopy(zs_init_reg, cs->cs_preg, 16); 299 300 /* Current BAUD rate generator clock. */ 301 cs->cs_brg_clk = PCLK / 16; /* RTxC is 230400*16, so use 230400 */ 302 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 303 cs->cs_defcflag = zs_def_cflag; 304 305 /* Make these correspond to cs_defcflag (-crtscts) */ 306 cs->cs_rr0_dcd = ZSRR0_DCD; 307 cs->cs_rr0_cts = 0; 308 cs->cs_wr5_dtr = ZSWR5_DTR; 309 cs->cs_wr5_rts = 0; 310 311 #ifdef __notyet__ 312 cs->cs_slave_type = ZS_SLAVE_NONE; 313 #endif 314 315 /* Define BAUD rate stuff. */ 316 xcs->cs_clocks[0].clk = PCLK; 317 xcs->cs_clocks[0].flags = ZSC_RTXBRG | ZSC_RTXDIV; 318 xcs->cs_clocks[1].flags = 319 ZSC_RTXBRG | ZSC_RTXDIV | ZSC_VARIABLE | ZSC_EXTERN; 320 xcs->cs_clocks[2].flags = ZSC_TRXDIV | ZSC_VARIABLE; 321 xcs->cs_clock_count = 3; 322 if (channel == 0) { 323 theflags = mac68k_machine.modem_flags; 324 xcs->cs_clocks[1].clk = mac68k_machine.modem_dcd_clk; 325 xcs->cs_clocks[2].clk = mac68k_machine.modem_cts_clk; 326 } else { 327 theflags = mac68k_machine.print_flags; 328 xcs->cs_clocks[1].flags = ZSC_VARIABLE; 329 /* 330 * Yes, we aren't defining ANY clock source enables for the 331 * printer's DCD clock in. The hardware won't let us 332 * use it. But a clock will freak out the chip, so we 333 * let you set it, telling us to bar interrupts on the line. 334 */ 335 xcs->cs_clocks[1].clk = mac68k_machine.print_dcd_clk; 336 xcs->cs_clocks[2].clk = mac68k_machine.print_cts_clk; 337 } 338 if (xcs->cs_clocks[1].clk) 339 zsc_args.hwflags |= ZS_HWFLAG_NO_DCD; 340 if (xcs->cs_clocks[2].clk) 341 zsc_args.hwflags |= ZS_HWFLAG_NO_CTS; 342 343 printf("zsc%d channel %d: d_speed %6d DCD clk %ld CTS clk %ld", 344 zsc_unit, channel, cs->cs_defspeed, 345 xcs->cs_clocks[1].clk, xcs->cs_clocks[2].clk); 346 347 /* Set defaults in our "extended" chanstate. */ 348 xcs->cs_csource = 0; 349 xcs->cs_psource = 0; 350 xcs->cs_cclk_flag = 0; /* Nothing fancy by default */ 351 xcs->cs_pclk_flag = 0; 352 353 if (theflags & ZSMAC_RAW) { 354 zsc_args.hwflags |= ZS_HWFLAG_RAW; 355 printf(" (raw defaults)"); 356 } 357 358 /* 359 * XXX - This might be better done with a "stub" driver 360 * (to replace zstty) that ignores LocalTalk for now. 361 */ 362 if (theflags & ZSMAC_LOCALTALK) { 363 printf(" shielding from LocalTalk"); 364 cs->cs_defspeed = 1; 365 cs->cs_creg[ZSRR_BAUDLO] = cs->cs_preg[ZSRR_BAUDLO] = 0xff; 366 cs->cs_creg[ZSRR_BAUDHI] = cs->cs_preg[ZSRR_BAUDHI] = 0xff; 367 zs_write_reg(cs, ZSRR_BAUDLO, 0xff); 368 zs_write_reg(cs, ZSRR_BAUDHI, 0xff); 369 /* 370 * If we might have LocalTalk, then make sure we have the 371 * Baud rate low-enough to not do any damage. 372 */ 373 } 374 375 /* 376 * We used to disable chip interrupts here, but we now 377 * do that in zscnprobe, just in case MacOS left the chip on. 378 */ 379 380 xcs->cs_chip = chip; 381 382 /* Stash away a copy of the final H/W flags. */ 383 xcs->cs_hwflags = zsc_args.hwflags; 384 385 printf("\n"); 386 387 /* 388 * Look for a child driver for this channel. 389 * The child attach will setup the hardware. 390 */ 391 if (!config_found(self, (void *)&zsc_args, zsc_print)) { 392 /* No sub-driver. Just reset it. */ 393 u_char reset = (channel == 0) ? 394 ZSWR9_A_RESET : ZSWR9_B_RESET; 395 s = splzs(); 396 zs_write_reg(cs, 9, reset); 397 splx(s); 398 } 399 } 400 401 if (current_mac_model->class == MACH_CLASSAV) { 402 add_psc_lev4_intr(PSCINTR_SCCA, zshard, zsc); 403 add_psc_lev4_intr(PSCINTR_SCCB, zshard, zsc); 404 } else { 405 intr_establish(zshard, zsc, ZSHARD_PRI); 406 } 407 408 /* Now safe to enable interrupts. */ 409 410 /* 411 * Set the master interrupt enable and interrupt vector. 412 * (common to both channels, do it on A) 413 */ 414 cs = zsc->zsc_cs[0]; 415 s = splzs(); 416 /* interrupt vector */ 417 zs_write_reg(cs, 2, zs_init_reg[2]); 418 /* master interrupt control (enable) */ 419 zs_write_reg(cs, 9, zs_init_reg[9]); 420 splx(s); 421 } 422 423 static int 424 zsc_print(aux, name) 425 void *aux; 426 const char *name; 427 { 428 struct zsc_attach_args *args = aux; 429 430 if (name != NULL) 431 printf("%s: ", name); 432 433 if (args->channel != -1) 434 printf(" channel %d", args->channel); 435 436 return UNCONF; 437 } 438 439 int 440 zsmdioctl(cs, cmd, data) 441 struct zs_chanstate *cs; 442 u_long cmd; 443 caddr_t data; 444 { 445 switch (cmd) { 446 default: 447 return (EPASSTHROUGH); 448 } 449 return (0); 450 } 451 452 void 453 zsmd_setclock(cs) 454 struct zs_chanstate *cs; 455 { 456 struct xzs_chanstate *xcs = (void *)cs; 457 458 if (cs->cs_channel != 0) 459 return; 460 461 /* 462 * If the new clock has the external bit set, then select the 463 * external source. 464 */ 465 via_set_modem((xcs->cs_pclk_flag & ZSC_EXTERN) ? 1 : 0); 466 } 467 468 static int zssoftpending; 469 470 /* 471 * Do the minimum work to pull data off of the chip and queue it up 472 * for later processing. 473 */ 474 int 475 zshard(arg) 476 void *arg; 477 { 478 struct zsc_softc *zsc = (struct zsc_softc *)arg; 479 int rval; 480 481 if (zsc == NULL) 482 return 0; 483 484 rval = zsc_intr_hard(zsc); 485 if ((zsc->zsc_cs[0]->cs_softreq) || (zsc->zsc_cs[1]->cs_softreq)) { 486 /* zsc_req_softint(zsc); */ 487 /* We are at splzs here, so no need to lock. */ 488 if (zssoftpending == 0) { 489 zssoftpending = 1; 490 setsoftserial(); 491 } 492 } 493 return (rval); 494 } 495 496 /* 497 * Look at all of the zsc softint queues. 498 */ 499 int 500 zssoft(arg) 501 void *arg; 502 { 503 struct zsc_softc *zsc; 504 int unit; 505 506 /* This is not the only ISR on this IPL. */ 507 if (zssoftpending == 0) 508 return (0); 509 510 /* 511 * The soft intr. bit will be set by zshard only if 512 * the variable zssoftpending is zero. 513 */ 514 zssoftpending = 0; 515 516 for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) { 517 zsc = zsc_cd.cd_devs[unit]; 518 if (zsc == NULL) 519 continue; 520 (void) zsc_intr_soft(zsc); 521 } 522 return (1); 523 } 524 525 526 #ifndef ZS_TOLERANCE 527 #define ZS_TOLERANCE 51 528 /* 5% in tenths of a %, plus 1 so that exactly 5% will be ok. */ 529 #endif 530 531 /* 532 * check out a rate for acceptability from the internal clock 533 * source. Used in console config to validate a requested 534 * default speed. Placed here so that all the speed checking code is 535 * in one place. 536 * 537 * != 0 means ok. 538 */ 539 int 540 zs_cn_check_speed(bps) 541 int bps; /* target rate */ 542 { 543 int tc, rate; 544 545 tc = BPS_TO_TCONST(PCLK / 16, bps); 546 if (tc < 0) 547 return 0; 548 rate = TCONST_TO_BPS(PCLK / 16, tc); 549 if (ZS_TOLERANCE > abs(((rate - bps)*1000)/bps)) 550 return 1; 551 else 552 return 0; 553 } 554 555 /* 556 * Search through the signal sources in the channel, and 557 * pick the best one for the baud rate requested. Return 558 * a -1 if not achievable in tolerance. Otherwise return 0 559 * and fill in the values. 560 * 561 * This routine draws inspiration from the Atari port's zs.c 562 * driver in NetBSD 1.1 which did the same type of source switching. 563 * Tolerance code inspired by comspeed routine in isa/com.c. 564 * 565 * By Bill Studenmund, 1996-05-12 566 */ 567 int 568 zs_set_speed(cs, bps) 569 struct zs_chanstate *cs; 570 int bps; /* bits per second */ 571 { 572 struct xzs_chanstate *xcs = (void *) cs; 573 int i, tc, tc0 = 0, tc1, s, sf = 0; 574 int src, rate0, rate1, err, tol; 575 576 if (bps == 0) 577 return (0); 578 579 src = -1; /* no valid source yet */ 580 tol = ZS_TOLERANCE; 581 582 /* 583 * Step through all the sources and see which one matches 584 * the best. A source has to match BETTER than tol to be chosen. 585 * Thus if two sources give the same error, the first one will be 586 * chosen. Also, allow for the possability that one source might run 587 * both the BRG and the direct divider (i.e. RTxC). 588 */ 589 for (i=0; i < xcs->cs_clock_count; i++) { 590 if (xcs->cs_clocks[i].clk <= 0) 591 continue; /* skip non-existent or bad clocks */ 592 if (xcs->cs_clocks[i].flags & ZSC_BRG) { 593 /* check out BRG at /16 */ 594 tc1 = BPS_TO_TCONST(xcs->cs_clocks[i].clk >> 4, bps); 595 if (tc1 >= 0) { 596 rate1 = TCONST_TO_BPS(xcs->cs_clocks[i].clk >> 4, tc1); 597 err = abs(((rate1 - bps)*1000)/bps); 598 if (err < tol) { 599 tol = err; 600 src = i; 601 sf = xcs->cs_clocks[i].flags & ~ZSC_DIV; 602 tc0 = tc1; 603 rate0 = rate1; 604 } 605 } 606 } 607 if (xcs->cs_clocks[i].flags & ZSC_DIV) { 608 /* 609 * Check out either /1, /16, /32, or /64 610 * Note: for /1, you'd better be using a synchronized 611 * clock! 612 */ 613 int b0 = xcs->cs_clocks[i].clk, e0 = abs(b0-bps); 614 int b1 = b0 >> 4, e1 = abs(b1-bps); 615 int b2 = b1 >> 1, e2 = abs(b2-bps); 616 int b3 = b2 >> 1, e3 = abs(b3-bps); 617 618 if (e0 < e1 && e0 < e2 && e0 < e3) { 619 err = e0; 620 rate1 = b0; 621 tc1 = ZSWR4_CLK_X1; 622 } else if (e0 > e1 && e1 < e2 && e1 < e3) { 623 err = e1; 624 rate1 = b1; 625 tc1 = ZSWR4_CLK_X16; 626 } else if (e0 > e2 && e1 > e2 && e2 < e3) { 627 err = e2; 628 rate1 = b2; 629 tc1 = ZSWR4_CLK_X32; 630 } else { 631 err = e3; 632 rate1 = b3; 633 tc1 = ZSWR4_CLK_X64; 634 } 635 636 err = (err * 1000)/bps; 637 if (err < tol) { 638 tol = err; 639 src = i; 640 sf = xcs->cs_clocks[i].flags & ~ZSC_BRG; 641 tc0 = tc1; 642 rate0 = rate1; 643 } 644 } 645 } 646 #ifdef ZSMACDEBUG 647 zsprintf("Checking for rate %d. Found source #%d.\n",bps, src); 648 #endif 649 if (src == -1) 650 return (EINVAL); /* no can do */ 651 652 /* 653 * The M.I. layer likes to keep cs_brg_clk current, even though 654 * we are the only ones who should be touching the BRG's rate. 655 * 656 * Note: we are assuming that any ZSC_EXTERN signal source comes in 657 * on the RTxC pin. Correct for the mac68k obio zsc. 658 */ 659 if (sf & ZSC_EXTERN) 660 cs->cs_brg_clk = xcs->cs_clocks[i].clk >> 4; 661 else 662 cs->cs_brg_clk = PCLK / 16; 663 664 /* 665 * Now we have a source, so set it up. 666 */ 667 s = splzs(); 668 xcs->cs_psource = src; 669 xcs->cs_pclk_flag = sf; 670 bps = rate0; 671 if (sf & ZSC_BRG) { 672 cs->cs_preg[4] = ZSWR4_CLK_X16; 673 cs->cs_preg[11]= ZSWR11_RXCLK_BAUD | ZSWR11_TXCLK_BAUD; 674 if (sf & ZSC_PCLK) { 675 cs->cs_preg[14] = ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK; 676 } else { 677 cs->cs_preg[14] = ZSWR14_BAUD_ENA; 678 } 679 tc = tc0; 680 } else { 681 cs->cs_preg[4] = tc0; 682 if (sf & ZSC_RTXDIV) { 683 cs->cs_preg[11] = ZSWR11_RXCLK_RTXC | ZSWR11_TXCLK_RTXC; 684 } else { 685 cs->cs_preg[11] = ZSWR11_RXCLK_TRXC | ZSWR11_TXCLK_TRXC; 686 } 687 cs->cs_preg[14]= 0; 688 tc = 0xffff; 689 } 690 /* Set the BAUD rate divisor. */ 691 cs->cs_preg[12] = tc; 692 cs->cs_preg[13] = tc >> 8; 693 splx(s); 694 695 #ifdef ZSMACDEBUG 696 zsprintf("Rate is %7d, tc is %7d, source no. %2d, flags %4x\n", \ 697 bps, tc, src, sf); 698 zsprintf("Registers are: 4 %x, 11 %x, 14 %x\n\n", 699 cs->cs_preg[4], cs->cs_preg[11], cs->cs_preg[14]); 700 #endif 701 702 cs->cs_preg[5] |= ZSWR5_RTS; /* Make sure the drivers are on! */ 703 704 /* Caller will stuff the pending registers. */ 705 return (0); 706 } 707 708 int 709 zs_set_modes(cs, cflag) 710 struct zs_chanstate *cs; 711 int cflag; /* bits per second */ 712 { 713 struct xzs_chanstate *xcs = (void*)cs; 714 int s; 715 716 /* 717 * Make sure we don't enable hfc on a signal line we're ignoring. 718 * As we enable CTS interrupts only if we have CRTSCTS or CDTRCTS, 719 * this code also effectivly turns off ZSWR15_CTS_IE. 720 * 721 * Also, disable DCD interrupts if we've been told to ignore 722 * the DCD pin. Happens on mac68k because the input line for 723 * DCD can also be used as a clock input. (Just set CLOCAL.) 724 * 725 * If someone tries to turn an invalid flow mode on, Just Say No 726 * (Suggested by gwr) 727 */ 728 if ((cflag & CDTRCTS) && (cflag & (CRTSCTS | MDMBUF))) 729 return (EINVAL); 730 cs->cs_rr0_pps = 0; 731 if (xcs->cs_hwflags & ZS_HWFLAG_NO_DCD) { 732 if (cflag & MDMBUF) 733 return (EINVAL); 734 cflag |= CLOCAL; 735 } else { 736 /* 737 * cs->cs_rr0_pps indicates which bit MAY be used for pps. 738 * Enable only if nothing else will want the interrupt and 739 * it's ok to enable interrupts on this line. 740 */ 741 if ((cflag & (CLOCAL | MDMBUF)) == CLOCAL) 742 cs->cs_rr0_pps = ZSRR0_DCD; 743 } 744 if ((xcs->cs_hwflags & ZS_HWFLAG_NO_CTS) && (cflag & (CRTSCTS | CDTRCTS))) 745 return (EINVAL); 746 747 /* 748 * Output hardware flow control on the chip is horrendous: 749 * if carrier detect drops, the receiver is disabled, and if 750 * CTS drops, the transmitter is stoped IN MID CHARACTER! 751 * Therefore, NEVER set the HFC bit, and instead use the 752 * status interrupt to detect CTS changes. 753 */ 754 s = splzs(); 755 if ((cflag & (CLOCAL | MDMBUF)) != 0) 756 cs->cs_rr0_dcd = 0; 757 else 758 cs->cs_rr0_dcd = ZSRR0_DCD; 759 /* 760 * The mac hardware only has one output, DTR (HSKo in Mac 761 * parlance). In HFC mode, we use it for the functions 762 * typically served by RTS and DTR on other ports, so we 763 * have to fake the upper layer out some. 764 * 765 * CRTSCTS we use CTS as an input which tells us when to shut up. 766 * We make no effort to shut up the other side of the connection. 767 * DTR is used to hang up the modem. 768 * 769 * In CDTRCTS, we use CTS to tell us to stop, but we use DTR to 770 * shut up the other side. 771 */ 772 if ((cflag & CRTSCTS) != 0) { 773 cs->cs_wr5_dtr = ZSWR5_DTR; 774 cs->cs_wr5_rts = 0; 775 cs->cs_rr0_cts = ZSRR0_CTS; 776 } else if ((cflag & CDTRCTS) != 0) { 777 cs->cs_wr5_dtr = 0; 778 cs->cs_wr5_rts = ZSWR5_DTR; 779 cs->cs_rr0_cts = ZSRR0_CTS; 780 } else if ((cflag & MDMBUF) != 0) { 781 cs->cs_wr5_dtr = 0; 782 cs->cs_wr5_rts = ZSWR5_DTR; 783 cs->cs_rr0_cts = ZSRR0_DCD; 784 } else { 785 cs->cs_wr5_dtr = ZSWR5_DTR; 786 cs->cs_wr5_rts = 0; 787 cs->cs_rr0_cts = 0; 788 } 789 splx(s); 790 791 /* Caller will stuff the pending registers. */ 792 return (0); 793 } 794 795 796 /* 797 * Read or write the chip with suitable delays. 798 * MacII hardware has the delay built in. 799 * No need for extra delay. :-) However, some clock-chirped 800 * macs, or zsc's on serial add-on boards might need it. 801 */ 802 #define ZS_DELAY() 803 804 u_char 805 zs_read_reg(cs, reg) 806 struct zs_chanstate *cs; 807 u_char reg; 808 { 809 u_char val; 810 811 *cs->cs_reg_csr = reg; 812 ZS_DELAY(); 813 val = *cs->cs_reg_csr; 814 ZS_DELAY(); 815 return val; 816 } 817 818 void 819 zs_write_reg(cs, reg, val) 820 struct zs_chanstate *cs; 821 u_char reg, val; 822 { 823 *cs->cs_reg_csr = reg; 824 ZS_DELAY(); 825 *cs->cs_reg_csr = val; 826 ZS_DELAY(); 827 } 828 829 u_char zs_read_csr(cs) 830 struct zs_chanstate *cs; 831 { 832 u_char val; 833 834 val = *cs->cs_reg_csr; 835 ZS_DELAY(); 836 /* make up for the fact CTS is wired backwards */ 837 val ^= ZSRR0_CTS; 838 return val; 839 } 840 841 void zs_write_csr(cs, val) 842 struct zs_chanstate *cs; 843 u_char val; 844 { 845 /* Note, the csr does not write CTS... */ 846 *cs->cs_reg_csr = val; 847 ZS_DELAY(); 848 } 849 850 u_char zs_read_data(cs) 851 struct zs_chanstate *cs; 852 { 853 u_char val; 854 855 val = *cs->cs_reg_data; 856 ZS_DELAY(); 857 return val; 858 } 859 860 void zs_write_data(cs, val) 861 struct zs_chanstate *cs; 862 u_char val; 863 { 864 *cs->cs_reg_data = val; 865 ZS_DELAY(); 866 } 867 868 /**************************************************************** 869 * Console support functions (mac68k specific!) 870 * Note: this code is allowed to know about the layout of 871 * the chip registers, and uses that to keep things simple. 872 * XXX - I think I like the mvme167 code better. -gwr 873 * XXX - Well :-P :-) -wrs 874 ****************************************************************/ 875 876 #define zscnpollc nullcnpollc 877 cons_decl(zs); 878 879 static void zscnsetup __P((void)); 880 extern int zsopen __P(( dev_t dev, int flags, int mode, struct proc *p)); 881 882 /* 883 * Console functions. 884 */ 885 886 /* 887 * This code modled after the zs_setparam routine in zskgdb 888 * It sets the console unit to a known state so we can output 889 * correctly. 890 */ 891 static void 892 zscnsetup() 893 { 894 struct xzs_chanstate xcs; 895 struct zs_chanstate *cs; 896 struct zschan *zc; 897 int tconst, s; 898 899 /* Setup temporary chanstate. */ 900 bzero((caddr_t)&xcs, sizeof(xcs)); 901 cs = &xcs.xzs_cs; 902 zc = zs_conschan; 903 cs->cs_reg_csr = &zc->zc_csr; 904 cs->cs_reg_data = &zc->zc_data; 905 cs->cs_channel = zs_consunit; 906 cs->cs_brg_clk = PCLK / 16; 907 908 bcopy(zs_init_reg, cs->cs_preg, 16); 909 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 910 cs->cs_preg[15] = ZSWR15_BREAK_IE; 911 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 912 zs_defspeed[0][zs_consunit]); 913 cs->cs_preg[12] = tconst; 914 cs->cs_preg[13] = tconst >> 8; 915 /* can't use zs_set_speed as we haven't set up the 916 * signal sources, and it's not worth it for now 917 */ 918 919 /* 920 * As zs_loadchannelregs doesn't touch reg 9 (interupt control), 921 * we won't accidentally turn on interupts below 922 */ 923 s = splhigh(); 924 zs_loadchannelregs(cs); 925 splx(s); 926 } 927 928 /* 929 * zscnprobe is the routine which gets called as the kernel is trying to 930 * figure out where the console should be. Each io driver which might 931 * be the console (as defined in mac68k/conf.c) gets probed. The probe 932 * fills in the consdev structure. Important parts are the device #, 933 * and the console priority. Values are CN_DEAD (don't touch me), 934 * CN_NORMAL (I'm here, but elsewhere might be better), CN_INTERNAL 935 * (the video, better than CN_NORMAL), and CN_REMOTE (pick me!) 936 * 937 * As the mac's a bit different, we do extra work here. We mainly check 938 * to see if we have serial echo going on. Also chould check for default 939 * speeds. 940 */ 941 void 942 zscnprobe(struct consdev * cp) 943 { 944 extern u_long IOBase; 945 int maj, unit, i; 946 947 for (maj = 0; maj < nchrdev; maj++) { 948 if (cdevsw[maj].d_open == zsopen) { 949 break; 950 } 951 } 952 if (maj != nchrdev) { 953 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 954 if (mac68k_machine.serial_console != 0) { 955 cp->cn_pri = CN_REMOTE; /* Higher than CN_INTERNAL */ 956 mac68k_machine.serial_boot_echo =0; 957 } 958 959 unit = (mac68k_machine.serial_console == 1) ? 0 : 1; 960 zs_consunit = unit; 961 zs_conschan = (struct zschan *) -1; /* dummy flag for zs_init() */ 962 963 mac68k_zsdev = cp->cn_dev = makedev(maj, unit); 964 } 965 if (mac68k_machine.serial_boot_echo) { 966 /* 967 * at this point, we know that we don't have a serial 968 * console, but are doing echo 969 */ 970 zs_conschan = (struct zschan *) -1; /* dummy flag for zs_init() */ 971 zs_consunit = 1; 972 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 973 } 974 975 if ((i = mac68k_machine.modem_d_speed) > 0) { 976 if (zs_cn_check_speed(i)) 977 zs_defspeed[0][0] = i; 978 } 979 if ((i = mac68k_machine.print_d_speed) > 0) { 980 if (zs_cn_check_speed(i)) 981 zs_defspeed[0][1] = i; 982 } 983 mac68k_set_io_offsets(IOBase); 984 zs_init(); 985 /* 986 * zsinit will set up the addresses of the scc. It will also, if 987 * zs_conschan != 0, calculate the new address of the conschan for 988 * unit zs_consunit. So if we are (or think we are) going to use the 989 * chip for console I/O, we just set up the internal addresses for it. 990 * 991 * Now turn off interrupts for the chip. Note: using sccA to get at 992 * the chip is the only vestage of the NetBSD 1.0 ser driver. :-) 993 */ 994 unit = sccA[2]; /* reset reg. access */ 995 unit = sccA[0]; 996 sccA[2] = 9; sccA[2] = 0; /* write 0 to reg. 9, clearing MIE */ 997 sccA[2] = ZSWR0_CLR_INTR; unit = sccA[2]; /* reset any pending ints. */ 998 sccA[0] = ZSWR0_CLR_INTR; unit = sccA[0]; 999 1000 if (mac68k_machine.serial_boot_echo) 1001 zscnsetup(); 1002 return; 1003 } 1004 1005 void 1006 zscninit(struct consdev * cp) 1007 { 1008 1009 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 1010 /* 1011 * zsinit will set up the addresses of the scc. It will also, if 1012 * zs_conschan != 0, calculate the new address of the conschan for 1013 * unit zs_consunit. So zs_init implicitly sets zs_conschan to the right 1014 * number. :-) 1015 */ 1016 zscnsetup(); 1017 printf("\nNetBSD/mac68k console\n"); 1018 } 1019 1020 1021 /* 1022 * Polled input char. 1023 */ 1024 int 1025 zs_getc(arg) 1026 void *arg; 1027 { 1028 volatile struct zschan *zc = arg; 1029 int s, c, rr0; 1030 1031 s = splhigh(); 1032 /* Wait for a character to arrive. */ 1033 do { 1034 rr0 = zc->zc_csr; 1035 ZS_DELAY(); 1036 } while ((rr0 & ZSRR0_RX_READY) == 0); 1037 1038 c = zc->zc_data; 1039 ZS_DELAY(); 1040 splx(s); 1041 1042 /* 1043 * This is used by the kd driver to read scan codes, 1044 * so don't translate '\r' ==> '\n' here... 1045 */ 1046 return (c); 1047 } 1048 1049 /* 1050 * Polled output char. 1051 */ 1052 void 1053 zs_putc(arg, c) 1054 void *arg; 1055 int c; 1056 { 1057 volatile struct zschan *zc = arg; 1058 int s, rr0; 1059 long wait = 0; 1060 1061 s = splhigh(); 1062 /* Wait for transmitter to become ready. */ 1063 do { 1064 rr0 = zc->zc_csr; 1065 ZS_DELAY(); 1066 } while (((rr0 & ZSRR0_TX_READY) == 0) && (wait++ < 1000000)); 1067 1068 if ((rr0 & ZSRR0_TX_READY) != 0) { 1069 zc->zc_data = c; 1070 ZS_DELAY(); 1071 } 1072 splx(s); 1073 } 1074 1075 1076 /* 1077 * Polled console input putchar. 1078 */ 1079 int 1080 zscngetc(dev) 1081 dev_t dev; 1082 { 1083 struct zschan *zc = zs_conschan; 1084 int c; 1085 1086 c = zs_getc(zc); 1087 return (c); 1088 } 1089 1090 /* 1091 * Polled console output putchar. 1092 */ 1093 void 1094 zscnputc(dev, c) 1095 dev_t dev; 1096 int c; 1097 { 1098 struct zschan *zc = zs_conschan; 1099 1100 zs_putc(zc, c); 1101 } 1102 1103 1104 1105 /* 1106 * Handle user request to enter kernel debugger. 1107 */ 1108 void 1109 zs_abort(cs) 1110 struct zs_chanstate *cs; 1111 { 1112 volatile struct zschan *zc = zs_conschan; 1113 int rr0; 1114 long wait = 0; 1115 1116 if (zs_cons_canabort == 0) 1117 return; 1118 1119 /* Wait for end of break to avoid PROM abort. */ 1120 do { 1121 rr0 = zc->zc_csr; 1122 ZS_DELAY(); 1123 } while ((rr0 & ZSRR0_BREAK) && (wait++ < ZSABORT_DELAY)); 1124 1125 if (wait > ZSABORT_DELAY) { 1126 zs_cons_canabort = 0; 1127 /* If we time out, turn off the abort ability! */ 1128 } 1129 1130 #ifdef DDB 1131 Debugger(); 1132 #endif 1133 } 1134 1135