1 /* $NetBSD: zs.c,v 1.39 2002/10/02 05:36:37 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1998 Bill Studenmund 5 * Copyright (c) 1995 Gordon W. Ross 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 4. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Gordon Ross 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Zilog Z8530 Dual UART driver (machine-dependent part) 36 * 37 * Runs two serial lines per chip using slave drivers. 38 * Plain tty/async lines use the zs_async slave. 39 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 40 * Other ports use their own mice & keyboard slaves. 41 * 42 * Credits & history: 43 * 44 * With NetBSD 1.1, port-mac68k started using a port of the port-sparc 45 * (port-sun3?) zs.c driver (which was in turn based on code in the 46 * Berkeley 4.4 Lite release). Bill Studenmund did the port, with 47 * help from Allen Briggs and Gordon Ross <gwr@netbsd.org>. Noud de 48 * Brouwer field-tested the driver at a local ISP. 49 * 50 * Bill Studenmund and Gordon Ross then ported the machine-independant 51 * z8530 driver to work with port-mac68k. NetBSD 1.2 contained an 52 * intermediate version (mac68k using a local, patched version of 53 * the m.i. drivers), with NetBSD 1.3 containing a full version. 54 */ 55 56 #include "opt_ddb.h" 57 #include "opt_mac68k.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/proc.h> 62 #include <sys/device.h> 63 #include <sys/conf.h> 64 #include <sys/file.h> 65 #include <sys/ioctl.h> 66 #include <sys/tty.h> 67 #include <sys/time.h> 68 #include <sys/kernel.h> 69 #include <sys/syslog.h> 70 71 #include <machine/autoconf.h> 72 #include <machine/cpu.h> 73 #include <machine/psc.h> 74 #include <machine/viareg.h> 75 76 #include <dev/cons.h> 77 #include <dev/ic/z8530reg.h> 78 #include <machine/z8530var.h> 79 #include <mac68k/dev/zs_cons.h> 80 81 /* Are these in a header file anywhere? */ 82 /* Booter flags interface */ 83 #define ZSMAC_RAW 0x01 84 #define ZSMAC_LOCALTALK 0x02 85 86 #define PCLK (9600 * 384) 87 88 #include "zsc.h" /* get the # of zs chips defined */ 89 90 /* 91 * Some warts needed by z8530tty.c - 92 */ 93 int zs_def_cflag = (CREAD | CS8 | HUPCL); 94 95 /* 96 * abort detection on console will now timeout after iterating on a loop 97 * the following # of times. Cheep hack. Also, abort detection is turned 98 * off after a timeout (i.e. maybe there's not a terminal hooked up). 99 */ 100 #define ZSABORT_DELAY 3000000 101 102 /* 103 * Define interrupt levels. 104 */ 105 #define ZSHARD_PRI 4 /* Wired on the CPU board... */ 106 /* 107 * Serial port cards with zs chips on them are actually at the 108 * NuBus interrupt level, which is lower than 4. But blocking 109 * level 4 interrupts will block those interrupts too, so level 110 * 4 is fine. 111 */ 112 113 /* The layout of this is hardware-dependent (padding, order). */ 114 struct zschan { 115 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 116 u_char zc_xxx0; 117 u_char zc_xxx1; /* part of the other channel lives here! */ 118 u_char zc_xxx2; /* Yea Apple! */ 119 volatile u_char zc_data; /* data */ 120 u_char zc_xxx3; 121 u_char zc_xxx4; 122 u_char zc_xxx5; 123 }; 124 125 /* Saved PROM mappings */ 126 static char *zsaddr[NZSC]; /* See zs_init() */ 127 /* Flags from cninit() */ 128 static int zs_hwflags[NZSC][2]; 129 /* Default speed for each channel */ 130 static int zs_defspeed[NZSC][2] = { 131 { 9600, /* tty00 */ 132 9600 }, /* tty01 */ 133 }; 134 /* console stuff */ 135 void *zs_conschan = 0; 136 int zs_consunit; 137 #ifdef ZS_CONSOLE_ABORT 138 int zs_cons_canabort = 1; 139 #else 140 int zs_cons_canabort = 0; 141 #endif /* ZS_CONSOLE_ABORT*/ 142 /* device to which the console is attached--if serial. */ 143 dev_t mac68k_zsdev; 144 /* Mac stuff */ 145 volatile unsigned char *sccA = 0; 146 147 int zs_cn_check_speed __P((int bps)); 148 149 /* 150 * Even though zsparam will set up the clock multiples, etc., we 151 * still set them here as: 1) mice & keyboards don't use zsparam, 152 * and 2) the console stuff uses these defaults before device 153 * attach. 154 */ 155 156 static u_char zs_init_reg[16] = { 157 0, /* 0: CMD (reset, etc.) */ 158 0, /* 1: No interrupts yet. */ 159 0x18 + ZSHARD_PRI, /* IVECT */ 160 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 161 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 162 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 163 0, /* 6: TXSYNC/SYNCLO */ 164 0, /* 7: RXSYNC/SYNCHI */ 165 0, /* 8: alias for data port */ 166 ZSWR9_MASTER_IE, 167 0, /*10: Misc. TX/RX control bits */ 168 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 169 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 170 0, /*13: BAUDHI (default=9600) */ 171 ZSWR14_BAUD_ENA, 172 ZSWR15_BREAK_IE, 173 }; 174 175 struct zschan * 176 zs_get_chan_addr(zsc_unit, channel) 177 int zsc_unit, channel; 178 { 179 char *addr; 180 struct zschan *zc; 181 182 if (zsc_unit >= NZSC) 183 return NULL; 184 addr = zsaddr[zsc_unit]; 185 if (addr == NULL) 186 return NULL; 187 if (channel == 0) { 188 zc = (struct zschan *)(addr + 2); 189 /* handle the fact the ports are intertwined. */ 190 } else { 191 zc = (struct zschan *)(addr); 192 } 193 return (zc); 194 } 195 196 197 /* Find PROM mappings (for console support). */ 198 int zsinited = 0; /* 0 = not, 1 = inited, not attached, 2= attached */ 199 200 void 201 zs_init() 202 { 203 if ((zsinited == 2)&&(zsaddr[0] != (char *) sccA)) 204 panic("Moved zs0 address after attached!"); 205 zsaddr[0] = (char *) sccA; 206 zsinited = 1; 207 if (zs_conschan != 0){ /* we might have moved io under the console */ 208 zs_conschan = zs_get_chan_addr(0, zs_consunit); 209 /* so recalc the console port */ 210 } 211 } 212 213 214 /**************************************************************** 215 * Autoconfig 216 ****************************************************************/ 217 218 /* Definition of the driver for autoconfig. */ 219 static int zsc_match __P((struct device *, struct cfdata *, void *)); 220 static void zsc_attach __P((struct device *, struct device *, void *)); 221 static int zsc_print __P((void *, const char *name)); 222 223 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 224 zsc_match, zsc_attach, NULL, NULL); 225 226 extern struct cfdriver zsc_cd; 227 228 int zshard __P((void *)); 229 int zssoft __P((void *)); 230 231 232 /* 233 * Is the zs chip present? 234 */ 235 static int 236 zsc_match(parent, cf, aux) 237 struct device *parent; 238 struct cfdata *cf; 239 void *aux; 240 { 241 return 1; 242 } 243 244 /* 245 * Attach a found zs. 246 * 247 * Match slave number to zs unit number, so that misconfiguration will 248 * not set up the keyboard as ttya, etc. 249 */ 250 static void 251 zsc_attach(parent, self, aux) 252 struct device *parent; 253 struct device *self; 254 void *aux; 255 { 256 struct zsc_softc *zsc = (void *) self; 257 struct zsc_attach_args zsc_args; 258 volatile struct zschan *zc; 259 struct xzs_chanstate *xcs; 260 struct zs_chanstate *cs; 261 int zsc_unit, channel; 262 int s, chip, theflags; 263 264 if (!zsinited) 265 zs_init(); 266 zsinited = 2; 267 268 zsc_unit = zsc->zsc_dev.dv_unit; 269 270 /* Make sure everything's inited ok. */ 271 if (zsaddr[zsc_unit] == NULL) 272 panic("zs_attach: zs%d not mapped", zsc_unit); 273 274 chip = 0; /* We'll deal with chip types post 1.2 */ 275 printf(" chip type %d \n",chip); 276 277 /* 278 * Initialize software state for each channel. 279 */ 280 for (channel = 0; channel < 2; channel++) { 281 zsc_args.channel = channel; 282 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 283 xcs = &zsc->xzsc_xcs_store[channel]; 284 cs = &xcs->xzs_cs; 285 zsc->zsc_cs[channel] = cs; 286 287 cs->cs_channel = channel; 288 cs->cs_private = NULL; 289 cs->cs_ops = &zsops_null; 290 291 zc = zs_get_chan_addr(zsc_unit, channel); 292 cs->cs_reg_csr = &zc->zc_csr; 293 cs->cs_reg_data = &zc->zc_data; 294 295 bcopy(zs_init_reg, cs->cs_creg, 16); 296 bcopy(zs_init_reg, cs->cs_preg, 16); 297 298 /* Current BAUD rate generator clock. */ 299 cs->cs_brg_clk = PCLK / 16; /* RTxC is 230400*16, so use 230400 */ 300 cs->cs_defspeed = zs_defspeed[zsc_unit][channel]; 301 cs->cs_defcflag = zs_def_cflag; 302 303 /* Make these correspond to cs_defcflag (-crtscts) */ 304 cs->cs_rr0_dcd = ZSRR0_DCD; 305 cs->cs_rr0_cts = 0; 306 cs->cs_wr5_dtr = ZSWR5_DTR; 307 cs->cs_wr5_rts = 0; 308 309 #ifdef __notyet__ 310 cs->cs_slave_type = ZS_SLAVE_NONE; 311 #endif 312 313 /* Define BAUD rate stuff. */ 314 xcs->cs_clocks[0].clk = PCLK; 315 xcs->cs_clocks[0].flags = ZSC_RTXBRG | ZSC_RTXDIV; 316 xcs->cs_clocks[1].flags = 317 ZSC_RTXBRG | ZSC_RTXDIV | ZSC_VARIABLE | ZSC_EXTERN; 318 xcs->cs_clocks[2].flags = ZSC_TRXDIV | ZSC_VARIABLE; 319 xcs->cs_clock_count = 3; 320 if (channel == 0) { 321 theflags = mac68k_machine.modem_flags; 322 xcs->cs_clocks[1].clk = mac68k_machine.modem_dcd_clk; 323 xcs->cs_clocks[2].clk = mac68k_machine.modem_cts_clk; 324 } else { 325 theflags = mac68k_machine.print_flags; 326 xcs->cs_clocks[1].flags = ZSC_VARIABLE; 327 /* 328 * Yes, we aren't defining ANY clock source enables for the 329 * printer's DCD clock in. The hardware won't let us 330 * use it. But a clock will freak out the chip, so we 331 * let you set it, telling us to bar interrupts on the line. 332 */ 333 xcs->cs_clocks[1].clk = mac68k_machine.print_dcd_clk; 334 xcs->cs_clocks[2].clk = mac68k_machine.print_cts_clk; 335 } 336 if (xcs->cs_clocks[1].clk) 337 zsc_args.hwflags |= ZS_HWFLAG_NO_DCD; 338 if (xcs->cs_clocks[2].clk) 339 zsc_args.hwflags |= ZS_HWFLAG_NO_CTS; 340 341 printf("zsc%d channel %d: d_speed %6d DCD clk %ld CTS clk %ld", 342 zsc_unit, channel, cs->cs_defspeed, 343 xcs->cs_clocks[1].clk, xcs->cs_clocks[2].clk); 344 345 /* Set defaults in our "extended" chanstate. */ 346 xcs->cs_csource = 0; 347 xcs->cs_psource = 0; 348 xcs->cs_cclk_flag = 0; /* Nothing fancy by default */ 349 xcs->cs_pclk_flag = 0; 350 351 if (theflags & ZSMAC_RAW) { 352 zsc_args.hwflags |= ZS_HWFLAG_RAW; 353 printf(" (raw defaults)"); 354 } 355 356 /* 357 * XXX - This might be better done with a "stub" driver 358 * (to replace zstty) that ignores LocalTalk for now. 359 */ 360 if (theflags & ZSMAC_LOCALTALK) { 361 printf(" shielding from LocalTalk"); 362 cs->cs_defspeed = 1; 363 cs->cs_creg[ZSRR_BAUDLO] = cs->cs_preg[ZSRR_BAUDLO] = 0xff; 364 cs->cs_creg[ZSRR_BAUDHI] = cs->cs_preg[ZSRR_BAUDHI] = 0xff; 365 zs_write_reg(cs, ZSRR_BAUDLO, 0xff); 366 zs_write_reg(cs, ZSRR_BAUDHI, 0xff); 367 /* 368 * If we might have LocalTalk, then make sure we have the 369 * Baud rate low-enough to not do any damage. 370 */ 371 } 372 373 /* 374 * We used to disable chip interrupts here, but we now 375 * do that in zscnprobe, just in case MacOS left the chip on. 376 */ 377 378 xcs->cs_chip = chip; 379 380 /* Stash away a copy of the final H/W flags. */ 381 xcs->cs_hwflags = zsc_args.hwflags; 382 383 printf("\n"); 384 385 /* 386 * Look for a child driver for this channel. 387 * The child attach will setup the hardware. 388 */ 389 if (!config_found(self, (void *)&zsc_args, zsc_print)) { 390 /* No sub-driver. Just reset it. */ 391 u_char reset = (channel == 0) ? 392 ZSWR9_A_RESET : ZSWR9_B_RESET; 393 s = splzs(); 394 zs_write_reg(cs, 9, reset); 395 splx(s); 396 } 397 } 398 399 if (current_mac_model->class == MACH_CLASSAV) { 400 add_psc_lev4_intr(PSCINTR_SCCA, zshard, zsc); 401 add_psc_lev4_intr(PSCINTR_SCCB, zshard, zsc); 402 } else { 403 intr_establish(zshard, zsc, ZSHARD_PRI); 404 } 405 406 /* Now safe to enable interrupts. */ 407 408 /* 409 * Set the master interrupt enable and interrupt vector. 410 * (common to both channels, do it on A) 411 */ 412 cs = zsc->zsc_cs[0]; 413 s = splzs(); 414 /* interrupt vector */ 415 zs_write_reg(cs, 2, zs_init_reg[2]); 416 /* master interrupt control (enable) */ 417 zs_write_reg(cs, 9, zs_init_reg[9]); 418 splx(s); 419 } 420 421 static int 422 zsc_print(aux, name) 423 void *aux; 424 const char *name; 425 { 426 struct zsc_attach_args *args = aux; 427 428 if (name != NULL) 429 printf("%s: ", name); 430 431 if (args->channel != -1) 432 printf(" channel %d", args->channel); 433 434 return UNCONF; 435 } 436 437 int 438 zsmdioctl(cs, cmd, data) 439 struct zs_chanstate *cs; 440 u_long cmd; 441 caddr_t data; 442 { 443 switch (cmd) { 444 default: 445 return (EPASSTHROUGH); 446 } 447 return (0); 448 } 449 450 void 451 zsmd_setclock(cs) 452 struct zs_chanstate *cs; 453 { 454 struct xzs_chanstate *xcs = (void *)cs; 455 456 if (cs->cs_channel != 0) 457 return; 458 459 /* 460 * If the new clock has the external bit set, then select the 461 * external source. 462 */ 463 via_set_modem((xcs->cs_pclk_flag & ZSC_EXTERN) ? 1 : 0); 464 } 465 466 static int zssoftpending; 467 468 /* 469 * Do the minimum work to pull data off of the chip and queue it up 470 * for later processing. 471 */ 472 int 473 zshard(arg) 474 void *arg; 475 { 476 struct zsc_softc *zsc = (struct zsc_softc *)arg; 477 int rval; 478 479 if (zsc == NULL) 480 return 0; 481 482 rval = zsc_intr_hard(zsc); 483 if ((zsc->zsc_cs[0]->cs_softreq) || (zsc->zsc_cs[1]->cs_softreq)) { 484 /* zsc_req_softint(zsc); */ 485 /* We are at splzs here, so no need to lock. */ 486 if (zssoftpending == 0) { 487 zssoftpending = 1; 488 setsoftserial(); 489 } 490 } 491 return (rval); 492 } 493 494 /* 495 * Look at all of the zsc softint queues. 496 */ 497 int 498 zssoft(arg) 499 void *arg; 500 { 501 struct zsc_softc *zsc; 502 int unit; 503 504 /* This is not the only ISR on this IPL. */ 505 if (zssoftpending == 0) 506 return (0); 507 508 /* 509 * The soft intr. bit will be set by zshard only if 510 * the variable zssoftpending is zero. 511 */ 512 zssoftpending = 0; 513 514 for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) { 515 zsc = zsc_cd.cd_devs[unit]; 516 if (zsc == NULL) 517 continue; 518 (void) zsc_intr_soft(zsc); 519 } 520 return (1); 521 } 522 523 524 #ifndef ZS_TOLERANCE 525 #define ZS_TOLERANCE 51 526 /* 5% in tenths of a %, plus 1 so that exactly 5% will be ok. */ 527 #endif 528 529 /* 530 * check out a rate for acceptability from the internal clock 531 * source. Used in console config to validate a requested 532 * default speed. Placed here so that all the speed checking code is 533 * in one place. 534 * 535 * != 0 means ok. 536 */ 537 int 538 zs_cn_check_speed(bps) 539 int bps; /* target rate */ 540 { 541 int tc, rate; 542 543 tc = BPS_TO_TCONST(PCLK / 16, bps); 544 if (tc < 0) 545 return 0; 546 rate = TCONST_TO_BPS(PCLK / 16, tc); 547 if (ZS_TOLERANCE > abs(((rate - bps)*1000)/bps)) 548 return 1; 549 else 550 return 0; 551 } 552 553 /* 554 * Search through the signal sources in the channel, and 555 * pick the best one for the baud rate requested. Return 556 * a -1 if not achievable in tolerance. Otherwise return 0 557 * and fill in the values. 558 * 559 * This routine draws inspiration from the Atari port's zs.c 560 * driver in NetBSD 1.1 which did the same type of source switching. 561 * Tolerance code inspired by comspeed routine in isa/com.c. 562 * 563 * By Bill Studenmund, 1996-05-12 564 */ 565 int 566 zs_set_speed(cs, bps) 567 struct zs_chanstate *cs; 568 int bps; /* bits per second */ 569 { 570 struct xzs_chanstate *xcs = (void *) cs; 571 int i, tc, tc0 = 0, tc1, s, sf = 0; 572 int src, rate0, rate1, err, tol; 573 574 if (bps == 0) 575 return (0); 576 577 src = -1; /* no valid source yet */ 578 tol = ZS_TOLERANCE; 579 580 /* 581 * Step through all the sources and see which one matches 582 * the best. A source has to match BETTER than tol to be chosen. 583 * Thus if two sources give the same error, the first one will be 584 * chosen. Also, allow for the possability that one source might run 585 * both the BRG and the direct divider (i.e. RTxC). 586 */ 587 for (i=0; i < xcs->cs_clock_count; i++) { 588 if (xcs->cs_clocks[i].clk <= 0) 589 continue; /* skip non-existent or bad clocks */ 590 if (xcs->cs_clocks[i].flags & ZSC_BRG) { 591 /* check out BRG at /16 */ 592 tc1 = BPS_TO_TCONST(xcs->cs_clocks[i].clk >> 4, bps); 593 if (tc1 >= 0) { 594 rate1 = TCONST_TO_BPS(xcs->cs_clocks[i].clk >> 4, tc1); 595 err = abs(((rate1 - bps)*1000)/bps); 596 if (err < tol) { 597 tol = err; 598 src = i; 599 sf = xcs->cs_clocks[i].flags & ~ZSC_DIV; 600 tc0 = tc1; 601 rate0 = rate1; 602 } 603 } 604 } 605 if (xcs->cs_clocks[i].flags & ZSC_DIV) { 606 /* 607 * Check out either /1, /16, /32, or /64 608 * Note: for /1, you'd better be using a synchronized 609 * clock! 610 */ 611 int b0 = xcs->cs_clocks[i].clk, e0 = abs(b0-bps); 612 int b1 = b0 >> 4, e1 = abs(b1-bps); 613 int b2 = b1 >> 1, e2 = abs(b2-bps); 614 int b3 = b2 >> 1, e3 = abs(b3-bps); 615 616 if (e0 < e1 && e0 < e2 && e0 < e3) { 617 err = e0; 618 rate1 = b0; 619 tc1 = ZSWR4_CLK_X1; 620 } else if (e0 > e1 && e1 < e2 && e1 < e3) { 621 err = e1; 622 rate1 = b1; 623 tc1 = ZSWR4_CLK_X16; 624 } else if (e0 > e2 && e1 > e2 && e2 < e3) { 625 err = e2; 626 rate1 = b2; 627 tc1 = ZSWR4_CLK_X32; 628 } else { 629 err = e3; 630 rate1 = b3; 631 tc1 = ZSWR4_CLK_X64; 632 } 633 634 err = (err * 1000)/bps; 635 if (err < tol) { 636 tol = err; 637 src = i; 638 sf = xcs->cs_clocks[i].flags & ~ZSC_BRG; 639 tc0 = tc1; 640 rate0 = rate1; 641 } 642 } 643 } 644 #ifdef ZSMACDEBUG 645 zsprintf("Checking for rate %d. Found source #%d.\n",bps, src); 646 #endif 647 if (src == -1) 648 return (EINVAL); /* no can do */ 649 650 /* 651 * The M.I. layer likes to keep cs_brg_clk current, even though 652 * we are the only ones who should be touching the BRG's rate. 653 * 654 * Note: we are assuming that any ZSC_EXTERN signal source comes in 655 * on the RTxC pin. Correct for the mac68k obio zsc. 656 */ 657 if (sf & ZSC_EXTERN) 658 cs->cs_brg_clk = xcs->cs_clocks[i].clk >> 4; 659 else 660 cs->cs_brg_clk = PCLK / 16; 661 662 /* 663 * Now we have a source, so set it up. 664 */ 665 s = splzs(); 666 xcs->cs_psource = src; 667 xcs->cs_pclk_flag = sf; 668 bps = rate0; 669 if (sf & ZSC_BRG) { 670 cs->cs_preg[4] = ZSWR4_CLK_X16; 671 cs->cs_preg[11]= ZSWR11_RXCLK_BAUD | ZSWR11_TXCLK_BAUD; 672 if (sf & ZSC_PCLK) { 673 cs->cs_preg[14] = ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK; 674 } else { 675 cs->cs_preg[14] = ZSWR14_BAUD_ENA; 676 } 677 tc = tc0; 678 } else { 679 cs->cs_preg[4] = tc0; 680 if (sf & ZSC_RTXDIV) { 681 cs->cs_preg[11] = ZSWR11_RXCLK_RTXC | ZSWR11_TXCLK_RTXC; 682 } else { 683 cs->cs_preg[11] = ZSWR11_RXCLK_TRXC | ZSWR11_TXCLK_TRXC; 684 } 685 cs->cs_preg[14]= 0; 686 tc = 0xffff; 687 } 688 /* Set the BAUD rate divisor. */ 689 cs->cs_preg[12] = tc; 690 cs->cs_preg[13] = tc >> 8; 691 splx(s); 692 693 #ifdef ZSMACDEBUG 694 zsprintf("Rate is %7d, tc is %7d, source no. %2d, flags %4x\n", \ 695 bps, tc, src, sf); 696 zsprintf("Registers are: 4 %x, 11 %x, 14 %x\n\n", 697 cs->cs_preg[4], cs->cs_preg[11], cs->cs_preg[14]); 698 #endif 699 700 cs->cs_preg[5] |= ZSWR5_RTS; /* Make sure the drivers are on! */ 701 702 /* Caller will stuff the pending registers. */ 703 return (0); 704 } 705 706 int 707 zs_set_modes(cs, cflag) 708 struct zs_chanstate *cs; 709 int cflag; /* bits per second */ 710 { 711 struct xzs_chanstate *xcs = (void*)cs; 712 int s; 713 714 /* 715 * Make sure we don't enable hfc on a signal line we're ignoring. 716 * As we enable CTS interrupts only if we have CRTSCTS or CDTRCTS, 717 * this code also effectivly turns off ZSWR15_CTS_IE. 718 * 719 * Also, disable DCD interrupts if we've been told to ignore 720 * the DCD pin. Happens on mac68k because the input line for 721 * DCD can also be used as a clock input. (Just set CLOCAL.) 722 * 723 * If someone tries to turn an invalid flow mode on, Just Say No 724 * (Suggested by gwr) 725 */ 726 if ((cflag & CDTRCTS) && (cflag & (CRTSCTS | MDMBUF))) 727 return (EINVAL); 728 cs->cs_rr0_pps = 0; 729 if (xcs->cs_hwflags & ZS_HWFLAG_NO_DCD) { 730 if (cflag & MDMBUF) 731 return (EINVAL); 732 cflag |= CLOCAL; 733 } else { 734 /* 735 * cs->cs_rr0_pps indicates which bit MAY be used for pps. 736 * Enable only if nothing else will want the interrupt and 737 * it's ok to enable interrupts on this line. 738 */ 739 if ((cflag & (CLOCAL | MDMBUF)) == CLOCAL) 740 cs->cs_rr0_pps = ZSRR0_DCD; 741 } 742 if ((xcs->cs_hwflags & ZS_HWFLAG_NO_CTS) && (cflag & (CRTSCTS | CDTRCTS))) 743 return (EINVAL); 744 745 /* 746 * Output hardware flow control on the chip is horrendous: 747 * if carrier detect drops, the receiver is disabled, and if 748 * CTS drops, the transmitter is stoped IN MID CHARACTER! 749 * Therefore, NEVER set the HFC bit, and instead use the 750 * status interrupt to detect CTS changes. 751 */ 752 s = splzs(); 753 if ((cflag & (CLOCAL | MDMBUF)) != 0) 754 cs->cs_rr0_dcd = 0; 755 else 756 cs->cs_rr0_dcd = ZSRR0_DCD; 757 /* 758 * The mac hardware only has one output, DTR (HSKo in Mac 759 * parlance). In HFC mode, we use it for the functions 760 * typically served by RTS and DTR on other ports, so we 761 * have to fake the upper layer out some. 762 * 763 * CRTSCTS we use CTS as an input which tells us when to shut up. 764 * We make no effort to shut up the other side of the connection. 765 * DTR is used to hang up the modem. 766 * 767 * In CDTRCTS, we use CTS to tell us to stop, but we use DTR to 768 * shut up the other side. 769 */ 770 if ((cflag & CRTSCTS) != 0) { 771 cs->cs_wr5_dtr = ZSWR5_DTR; 772 cs->cs_wr5_rts = 0; 773 cs->cs_rr0_cts = ZSRR0_CTS; 774 } else if ((cflag & CDTRCTS) != 0) { 775 cs->cs_wr5_dtr = 0; 776 cs->cs_wr5_rts = ZSWR5_DTR; 777 cs->cs_rr0_cts = ZSRR0_CTS; 778 } else if ((cflag & MDMBUF) != 0) { 779 cs->cs_wr5_dtr = 0; 780 cs->cs_wr5_rts = ZSWR5_DTR; 781 cs->cs_rr0_cts = ZSRR0_DCD; 782 } else { 783 cs->cs_wr5_dtr = ZSWR5_DTR; 784 cs->cs_wr5_rts = 0; 785 cs->cs_rr0_cts = 0; 786 } 787 splx(s); 788 789 /* Caller will stuff the pending registers. */ 790 return (0); 791 } 792 793 794 /* 795 * Read or write the chip with suitable delays. 796 * MacII hardware has the delay built in. 797 * No need for extra delay. :-) However, some clock-chirped 798 * macs, or zsc's on serial add-on boards might need it. 799 */ 800 #define ZS_DELAY() 801 802 u_char 803 zs_read_reg(cs, reg) 804 struct zs_chanstate *cs; 805 u_char reg; 806 { 807 u_char val; 808 809 *cs->cs_reg_csr = reg; 810 ZS_DELAY(); 811 val = *cs->cs_reg_csr; 812 ZS_DELAY(); 813 return val; 814 } 815 816 void 817 zs_write_reg(cs, reg, val) 818 struct zs_chanstate *cs; 819 u_char reg, val; 820 { 821 *cs->cs_reg_csr = reg; 822 ZS_DELAY(); 823 *cs->cs_reg_csr = val; 824 ZS_DELAY(); 825 } 826 827 u_char zs_read_csr(cs) 828 struct zs_chanstate *cs; 829 { 830 u_char val; 831 832 val = *cs->cs_reg_csr; 833 ZS_DELAY(); 834 /* make up for the fact CTS is wired backwards */ 835 val ^= ZSRR0_CTS; 836 return val; 837 } 838 839 void zs_write_csr(cs, val) 840 struct zs_chanstate *cs; 841 u_char val; 842 { 843 /* Note, the csr does not write CTS... */ 844 *cs->cs_reg_csr = val; 845 ZS_DELAY(); 846 } 847 848 u_char zs_read_data(cs) 849 struct zs_chanstate *cs; 850 { 851 u_char val; 852 853 val = *cs->cs_reg_data; 854 ZS_DELAY(); 855 return val; 856 } 857 858 void zs_write_data(cs, val) 859 struct zs_chanstate *cs; 860 u_char val; 861 { 862 *cs->cs_reg_data = val; 863 ZS_DELAY(); 864 } 865 866 /**************************************************************** 867 * Console support functions (mac68k specific!) 868 * Note: this code is allowed to know about the layout of 869 * the chip registers, and uses that to keep things simple. 870 * XXX - I think I like the mvme167 code better. -gwr 871 * XXX - Well :-P :-) -wrs 872 ****************************************************************/ 873 874 #define zscnpollc nullcnpollc 875 cons_decl(zs); 876 877 static void zscnsetup __P((void)); 878 879 /* 880 * Console functions. 881 */ 882 883 /* 884 * This code modled after the zs_setparam routine in zskgdb 885 * It sets the console unit to a known state so we can output 886 * correctly. 887 */ 888 static void 889 zscnsetup() 890 { 891 struct xzs_chanstate xcs; 892 struct zs_chanstate *cs; 893 struct zschan *zc; 894 int tconst, s; 895 896 /* Setup temporary chanstate. */ 897 bzero((caddr_t)&xcs, sizeof(xcs)); 898 cs = &xcs.xzs_cs; 899 zc = zs_conschan; 900 cs->cs_reg_csr = &zc->zc_csr; 901 cs->cs_reg_data = &zc->zc_data; 902 cs->cs_channel = zs_consunit; 903 cs->cs_brg_clk = PCLK / 16; 904 905 bcopy(zs_init_reg, cs->cs_preg, 16); 906 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 907 cs->cs_preg[15] = ZSWR15_BREAK_IE; 908 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 909 zs_defspeed[0][zs_consunit]); 910 cs->cs_preg[12] = tconst; 911 cs->cs_preg[13] = tconst >> 8; 912 /* can't use zs_set_speed as we haven't set up the 913 * signal sources, and it's not worth it for now 914 */ 915 916 /* 917 * As zs_loadchannelregs doesn't touch reg 9 (interupt control), 918 * we won't accidentally turn on interupts below 919 */ 920 s = splhigh(); 921 zs_loadchannelregs(cs); 922 splx(s); 923 } 924 925 /* 926 * zscnprobe is the routine which gets called as the kernel is trying to 927 * figure out where the console should be. Each io driver which might 928 * be the console (as defined in mac68k/conf.c) gets probed. The probe 929 * fills in the consdev structure. Important parts are the device #, 930 * and the console priority. Values are CN_DEAD (don't touch me), 931 * CN_NORMAL (I'm here, but elsewhere might be better), CN_INTERNAL 932 * (the video, better than CN_NORMAL), and CN_REMOTE (pick me!) 933 * 934 * As the mac's a bit different, we do extra work here. We mainly check 935 * to see if we have serial echo going on. Also chould check for default 936 * speeds. 937 */ 938 void 939 zscnprobe(struct consdev * cp) 940 { 941 extern u_long IOBase; 942 int maj, unit, i; 943 extern const struct cdevsw zstty_cdevsw; 944 945 maj = cdevsw_lookup_major(&zstty_cdevsw); 946 if (maj != -1) { 947 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 948 if (mac68k_machine.serial_console != 0) { 949 cp->cn_pri = CN_REMOTE; /* Higher than CN_INTERNAL */ 950 mac68k_machine.serial_boot_echo =0; 951 } 952 953 unit = (mac68k_machine.serial_console == 1) ? 0 : 1; 954 zs_consunit = unit; 955 zs_conschan = (struct zschan *) -1; /* dummy flag for zs_init() */ 956 957 mac68k_zsdev = cp->cn_dev = makedev(maj, unit); 958 } 959 if (mac68k_machine.serial_boot_echo) { 960 /* 961 * at this point, we know that we don't have a serial 962 * console, but are doing echo 963 */ 964 zs_conschan = (struct zschan *) -1; /* dummy flag for zs_init() */ 965 zs_consunit = 1; 966 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 967 } 968 969 if ((i = mac68k_machine.modem_d_speed) > 0) { 970 if (zs_cn_check_speed(i)) 971 zs_defspeed[0][0] = i; 972 } 973 if ((i = mac68k_machine.print_d_speed) > 0) { 974 if (zs_cn_check_speed(i)) 975 zs_defspeed[0][1] = i; 976 } 977 mac68k_set_io_offsets(IOBase); 978 zs_init(); 979 /* 980 * zsinit will set up the addresses of the scc. It will also, if 981 * zs_conschan != 0, calculate the new address of the conschan for 982 * unit zs_consunit. So if we are (or think we are) going to use the 983 * chip for console I/O, we just set up the internal addresses for it. 984 * 985 * Now turn off interrupts for the chip. Note: using sccA to get at 986 * the chip is the only vestage of the NetBSD 1.0 ser driver. :-) 987 */ 988 unit = sccA[2]; /* reset reg. access */ 989 unit = sccA[0]; 990 sccA[2] = 9; sccA[2] = 0; /* write 0 to reg. 9, clearing MIE */ 991 sccA[2] = ZSWR0_CLR_INTR; unit = sccA[2]; /* reset any pending ints. */ 992 sccA[0] = ZSWR0_CLR_INTR; unit = sccA[0]; 993 994 if (mac68k_machine.serial_boot_echo) 995 zscnsetup(); 996 return; 997 } 998 999 void 1000 zscninit(struct consdev * cp) 1001 { 1002 1003 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 1004 /* 1005 * zsinit will set up the addresses of the scc. It will also, if 1006 * zs_conschan != 0, calculate the new address of the conschan for 1007 * unit zs_consunit. So zs_init implicitly sets zs_conschan to the right 1008 * number. :-) 1009 */ 1010 zscnsetup(); 1011 printf("\nNetBSD/mac68k console\n"); 1012 } 1013 1014 1015 /* 1016 * Polled input char. 1017 */ 1018 int 1019 zs_getc(arg) 1020 void *arg; 1021 { 1022 volatile struct zschan *zc = arg; 1023 int s, c, rr0; 1024 1025 s = splhigh(); 1026 /* Wait for a character to arrive. */ 1027 do { 1028 rr0 = zc->zc_csr; 1029 ZS_DELAY(); 1030 } while ((rr0 & ZSRR0_RX_READY) == 0); 1031 1032 c = zc->zc_data; 1033 ZS_DELAY(); 1034 splx(s); 1035 1036 /* 1037 * This is used by the kd driver to read scan codes, 1038 * so don't translate '\r' ==> '\n' here... 1039 */ 1040 return (c); 1041 } 1042 1043 /* 1044 * Polled output char. 1045 */ 1046 void 1047 zs_putc(arg, c) 1048 void *arg; 1049 int c; 1050 { 1051 volatile struct zschan *zc = arg; 1052 int s, rr0; 1053 long wait = 0; 1054 1055 s = splhigh(); 1056 /* Wait for transmitter to become ready. */ 1057 do { 1058 rr0 = zc->zc_csr; 1059 ZS_DELAY(); 1060 } while (((rr0 & ZSRR0_TX_READY) == 0) && (wait++ < 1000000)); 1061 1062 if ((rr0 & ZSRR0_TX_READY) != 0) { 1063 zc->zc_data = c; 1064 ZS_DELAY(); 1065 } 1066 splx(s); 1067 } 1068 1069 1070 /* 1071 * Polled console input putchar. 1072 */ 1073 int 1074 zscngetc(dev) 1075 dev_t dev; 1076 { 1077 struct zschan *zc = zs_conschan; 1078 int c; 1079 1080 c = zs_getc(zc); 1081 return (c); 1082 } 1083 1084 /* 1085 * Polled console output putchar. 1086 */ 1087 void 1088 zscnputc(dev, c) 1089 dev_t dev; 1090 int c; 1091 { 1092 struct zschan *zc = zs_conschan; 1093 1094 zs_putc(zc, c); 1095 } 1096 1097 1098 1099 /* 1100 * Handle user request to enter kernel debugger. 1101 */ 1102 void 1103 zs_abort(cs) 1104 struct zs_chanstate *cs; 1105 { 1106 volatile struct zschan *zc = zs_conschan; 1107 int rr0; 1108 long wait = 0; 1109 1110 if (zs_cons_canabort == 0) 1111 return; 1112 1113 /* Wait for end of break to avoid PROM abort. */ 1114 do { 1115 rr0 = zc->zc_csr; 1116 ZS_DELAY(); 1117 } while ((rr0 & ZSRR0_BREAK) && (wait++ < ZSABORT_DELAY)); 1118 1119 if (wait > ZSABORT_DELAY) { 1120 zs_cons_canabort = 0; 1121 /* If we time out, turn off the abort ability! */ 1122 } 1123 1124 #ifdef DDB 1125 Debugger(); 1126 #endif 1127 } 1128 1129