1 /* $NetBSD: if_mc_obio.c,v 1.7 2000/06/29 08:15:14 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym@bga.com> 5 * All rights reserved. 6 * 7 * Portions of this code are based on code by Denton Gentry <denny1@home.com> 8 * and Yanagisawa Takeshi <yanagisw@aa.ap.titech.ac.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 /* 32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra 33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940 34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem 35 * Controller) for DMA to and from the MACE. 36 */ 37 38 #include "opt_ddb.h" 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/socket.h> 44 #include <sys/systm.h> 45 46 #include <net/if.h> 47 #include <net/if_ether.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/bus.h> 52 #include <machine/psc.h> 53 54 #include <mac68k/obio/obiovar.h> 55 #include <mac68k/dev/if_mcreg.h> 56 #include <mac68k/dev/if_mcvar.h> 57 58 #define MACE_REG_BASE 0x50F1C000 59 #define MACE_PROM_BASE 0x50F08000 60 61 hide int mc_obio_match __P((struct device *, struct cfdata *, void *)); 62 hide void mc_obio_attach __P((struct device *, struct device *, void *)); 63 hide void mc_obio_init __P((struct mc_softc *sc)); 64 hide void mc_obio_put __P((struct mc_softc *sc, u_int len)); 65 hide int mc_dmaintr __P((void *arg)); 66 hide void mc_reset_rxdma __P((struct mc_softc *sc)); 67 hide void mc_reset_rxdma_set __P((struct mc_softc *, int set)); 68 hide void mc_reset_txdma __P((struct mc_softc *sc)); 69 hide int mc_obio_getaddr __P((struct mc_softc *, u_int8_t *)); 70 71 extern int kvtop __P((register caddr_t addr)); 72 73 struct cfattach mc_obio_ca = { 74 sizeof(struct mc_softc), mc_obio_match, mc_obio_attach 75 }; 76 77 hide int 78 mc_obio_match(parent, cf, aux) 79 struct device *parent; 80 struct cfdata *cf; 81 void *aux; 82 { 83 struct obio_attach_args *oa = aux; 84 bus_space_handle_t bsh; 85 int found = 0; 86 87 if (current_mac_model->class != MACH_CLASSAV) 88 return 0; 89 90 if (bus_space_map(oa->oa_tag, MACE_REG_BASE, MC_REGSIZE, 0, &bsh)) 91 return 0; 92 93 /* 94 * Make sure the MACE's I/O space is readable, and if it is, 95 * try to read the CHIPID register. A MACE will always have 96 * 0x?940, where the ? depends on the chip version. 97 */ 98 if (mac68k_bus_space_probe(oa->oa_tag, bsh, 0, 1)) { 99 if ((bus_space_read_1( 100 oa->oa_tag, bsh, MACE_REG(MACE_CHIPIDL)) == 0x40) && 101 ((bus_space_read_1( 102 oa->oa_tag, bsh, MACE_REG(MACE_CHIPIDH)) & 0xf) == 9)) 103 found = 1; 104 } 105 106 bus_space_unmap(oa->oa_tag, bsh, MC_REGSIZE); 107 108 return found; 109 } 110 111 hide void 112 mc_obio_attach(parent, self, aux) 113 struct device *parent, *self; 114 void *aux; 115 { 116 struct obio_attach_args *oa = (struct obio_attach_args *)aux; 117 struct mc_softc *sc = (void *)self; 118 u_int8_t myaddr[ETHER_ADDR_LEN]; 119 int i, noncontig = 0; 120 121 sc->sc_regt = oa->oa_tag; 122 sc->sc_biucc = XMTSP_64; 123 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 124 XMTBRST | RCVBRST; 125 sc->sc_plscc = PORTSEL_AUI; 126 127 if (bus_space_map(sc->sc_regt, MACE_REG_BASE, MC_REGSIZE, 0, 128 &sc->sc_regh)) { 129 printf(": failed to map space for MACE regs.\n"); 130 return; 131 } 132 133 if (mc_obio_getaddr(sc, myaddr)) { 134 printf(": failed to get MAC address.\n"); 135 return; 136 } 137 138 /* allocate memory for transmit buffer and mark it non-cacheable */ 139 sc->sc_txbuf = malloc(NBPG, M_DEVBUF, M_WAITOK); 140 sc->sc_txbuf_phys = kvtop(sc->sc_txbuf); 141 physaccess (sc->sc_txbuf, (caddr_t)sc->sc_txbuf_phys, NBPG, 142 PG_V | PG_RW | PG_CI); 143 144 /* 145 * allocate memory for receive buffer and mark it non-cacheable 146 * XXX This should use the bus_dma interface, since the buffer 147 * needs to be physically contiguous. However, it seems that 148 * at least on my system, malloc() does allocate contiguous 149 * memory. If it's not, suggest reducing the number of buffers 150 * to 2, which will fit in one 4K page. 151 */ 152 sc->sc_rxbuf = malloc(MC_NPAGES * NBPG, M_DEVBUF, M_WAITOK); 153 sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf); 154 for (i = 0; i < MC_NPAGES; i++) { 155 int pa; 156 157 pa = kvtop(sc->sc_rxbuf + NBPG*i); 158 physaccess (sc->sc_rxbuf + NBPG*i, (caddr_t)pa, NBPG, 159 PG_V | PG_RW | PG_CI); 160 if (pa != sc->sc_rxbuf_phys + NBPG*i) 161 noncontig = 1; 162 } 163 164 if (noncontig) { 165 printf("%s: receive DMA buffer not contiguous! " 166 "Try compiling with \"options MC_RXDMABUFS=2\"\n", 167 sc->sc_dev.dv_xname); 168 return; 169 } 170 171 sc->sc_bus_init = mc_obio_init; 172 sc->sc_putpacket = mc_obio_put; 173 174 /* disable receive DMA */ 175 psc_reg2(PSC_ENETRD_CTL) = 0x8800; 176 psc_reg2(PSC_ENETRD_CTL) = 0x1000; 177 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x1100; 178 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x1100; 179 180 /* disable transmit DMA */ 181 psc_reg2(PSC_ENETWR_CTL) = 0x8800; 182 psc_reg2(PSC_ENETWR_CTL) = 0x1000; 183 psc_reg2(PSC_ENETWR_CMD + PSC_SET0) = 0x1100; 184 psc_reg2(PSC_ENETWR_CMD + PSC_SET1) = 0x1100; 185 186 /* install interrupt handlers */ 187 add_psc_lev4_intr(PSCINTR_ENET_DMA, mc_dmaintr, sc); 188 add_psc_lev3_intr(mcintr, sc); 189 190 /* enable MACE DMA interrupts */ 191 psc_reg1(PSC_LEV4_IER) = 0x80 | (1 << PSCINTR_ENET_DMA); 192 193 /* don't know what this does */ 194 psc_reg2(PSC_ENETWR_CTL) = 0x9000; 195 psc_reg2(PSC_ENETRD_CTL) = 0x9000; 196 psc_reg2(PSC_ENETWR_CTL) = 0x0400; 197 psc_reg2(PSC_ENETRD_CTL) = 0x0400; 198 199 /* enable MACE interrupts */ 200 psc_reg1(PSC_LEV3_IER) = 0x80 | (1 << PSCINTR_ENET); 201 202 /* mcsetup returns 1 if something fails */ 203 if (mcsetup(sc, myaddr)) { 204 /* disable interrupts */ 205 psc_reg1(PSC_LEV4_IER) = (1 << PSCINTR_ENET_DMA); 206 psc_reg1(PSC_LEV3_IER) = (1 << PSCINTR_ENET); 207 /* remove interrupt handlers */ 208 remove_psc_lev4_intr(PSCINTR_ENET_DMA); 209 remove_psc_lev3_intr(); 210 211 bus_space_unmap(sc->sc_regt, sc->sc_regh, MC_REGSIZE); 212 return; 213 } 214 } 215 216 /* Bus-specific initialization */ 217 hide void 218 mc_obio_init(sc) 219 struct mc_softc *sc; 220 { 221 mc_reset_rxdma(sc); 222 mc_reset_txdma(sc); 223 } 224 225 hide void 226 mc_obio_put(sc, len) 227 struct mc_softc *sc; 228 u_int len; 229 { 230 psc_reg4(PSC_ENETWR_ADDR + sc->sc_txset) = sc->sc_txbuf_phys; 231 psc_reg4(PSC_ENETWR_LEN + sc->sc_txset) = len; 232 psc_reg2(PSC_ENETWR_CMD + sc->sc_txset) = 0x9800; 233 234 sc->sc_txset ^= 0x10; 235 } 236 237 /* 238 * Interrupt handler for the MACE DMA completion interrupts 239 */ 240 int 241 mc_dmaintr(arg) 242 void *arg; 243 { 244 struct mc_softc *sc = arg; 245 u_int16_t status; 246 u_int32_t bufsleft, which; 247 int head; 248 249 /* 250 * Not sure what this does... figure out if this interrupt is 251 * really ours? 252 */ 253 while ((which = psc_reg4(0x804)) != psc_reg4(0x804)) 254 ; 255 if ((which & 0x60000000) == 0) 256 return 0; 257 258 /* Get the read channel status */ 259 status = psc_reg2(PSC_ENETRD_CTL); 260 if (status & 0x2000) { 261 /* I think this is an exceptional condition. Reset the DMA */ 262 mc_reset_rxdma(sc); 263 #ifdef MCDEBUG 264 printf("%s: resetting receive DMA channel (status 0x%04x)\n", 265 sc->sc_dev.dv_xname, status); 266 #endif 267 } else if (status & 0x100) { 268 /* We've received some packets from the MACE */ 269 int offset; 270 271 /* Clear the interrupt */ 272 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x1100; 273 274 /* See how may receive buffers are left */ 275 bufsleft = psc_reg4(PSC_ENETRD_LEN + sc->sc_rxset); 276 head = MC_RXDMABUFS - bufsleft; 277 278 #if 0 /* I don't think this should ever happen */ 279 if (head == sc->sc_tail) { 280 #ifdef MCDEBUG 281 printf("%s: head == tail: suspending DMA?\n", 282 sc->sc_dev.dv_xname); 283 #endif 284 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9000; 285 } 286 #endif 287 288 /* Loop through, processing each of the packets */ 289 for (; sc->sc_tail < head; sc->sc_tail++) { 290 offset = sc->sc_tail * 0x800; 291 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[offset]; 292 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[offset+2]; 293 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[offset+4]; 294 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[offset+6]; 295 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset + 16; 296 297 mc_rint(sc); 298 } 299 300 /* 301 * If we're out of buffers, reset this register set 302 * and switch to the other one. Otherwise, reactivate 303 * this set. 304 */ 305 if (bufsleft == 0) { 306 mc_reset_rxdma_set(sc, sc->sc_rxset); 307 sc->sc_rxset ^= 0x10; 308 } else 309 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9800; 310 } 311 312 /* Get the write channel status */ 313 status = psc_reg2(PSC_ENETWR_CTL); 314 if (status & 0x2000) { 315 /* I think this is an exceptional condition. Reset the DMA */ 316 mc_reset_txdma(sc); 317 #ifdef MCDEBUG 318 printf("%s: resetting transmit DMA channel (status 0x%04x)\n", 319 sc->sc_dev.dv_xname, status); 320 #endif 321 } else if (status & 0x100) { 322 /* Clear the interrupt and switch register sets */ 323 psc_reg2(PSC_ENETWR_CMD + sc->sc_txseti) = 0x100; 324 sc->sc_txseti ^= 0x10; 325 } 326 327 return 1; 328 } 329 330 331 hide void 332 mc_reset_rxdma(sc) 333 struct mc_softc *sc; 334 { 335 u_int8_t maccc; 336 337 /* Disable receiver, reset the DMA channels */ 338 maccc = NIC_GET(sc, MACE_MACCC); 339 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 340 psc_reg2(PSC_ENETRD_CTL) = 0x8800; 341 mc_reset_rxdma_set(sc, 0); 342 psc_reg2(PSC_ENETRD_CTL) = 0x400; 343 344 psc_reg2(PSC_ENETRD_CTL) = 0x8800; 345 mc_reset_rxdma_set(sc, 0x10); 346 psc_reg2(PSC_ENETRD_CTL) = 0x400; 347 348 /* Reenable receiver, reenable DMA */ 349 NIC_PUT(sc, MACE_MACCC, maccc); 350 sc->sc_rxset = 0; 351 352 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x9800; 353 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x9800; 354 } 355 356 hide void 357 mc_reset_rxdma_set(sc, set) 358 struct mc_softc *sc; 359 int set; 360 { 361 /* disable DMA while modifying the registers, then reenable DMA */ 362 psc_reg2(PSC_ENETRD_CMD + set) = 0x0100; 363 psc_reg4(PSC_ENETRD_ADDR + set) = sc->sc_rxbuf_phys; 364 psc_reg4(PSC_ENETRD_LEN + set) = MC_RXDMABUFS; 365 psc_reg2(PSC_ENETRD_CMD + set) = 0x9800; 366 sc->sc_tail = 0; 367 } 368 369 hide void 370 mc_reset_txdma(sc) 371 struct mc_softc *sc; 372 { 373 u_int8_t maccc; 374 375 psc_reg2(PSC_ENETWR_CTL) = 0x8800; 376 maccc = NIC_GET(sc, MACE_MACCC); 377 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 378 sc->sc_txset = sc->sc_txseti = 0; 379 psc_reg2(PSC_ENETWR_CTL) = 0x400; 380 NIC_PUT(sc, MACE_MACCC, maccc); 381 } 382 383 hide int 384 mc_obio_getaddr(sc, lladdr) 385 struct mc_softc *sc; 386 u_int8_t *lladdr; 387 { 388 bus_space_handle_t bsh; 389 u_char csum; 390 391 if (bus_space_map(sc->sc_regt, MACE_PROM_BASE, 8*16, 0, &bsh)) { 392 printf(": failed to map space to read MACE address.\n%s", 393 sc->sc_dev.dv_xname); 394 return (-1); 395 } 396 397 if (!mac68k_bus_space_probe(sc->sc_regt, bsh, 0, 1)) { 398 bus_space_unmap(sc->sc_regt, bsh, 8*16); 399 return (-1); 400 } 401 402 csum = mc_get_enaddr(sc->sc_regt, bsh, 1, lladdr); 403 if (csum != 0xff) 404 printf(": ethernet PROM checksum failed (0x%x != 0xff)\n%s", 405 (int)csum, sc->sc_dev.dv_xname); 406 407 bus_space_unmap(sc->sc_regt, bsh, 8*16); 408 409 return (csum == 0xff ? 0 : -1); 410 } 411