1 /* $NetBSD: dbdma.c,v 1.4 2001/06/08 00:32:02 matt Exp $ */ 2 3 /* 4 * Copyright 1991-1998 by Open Software Foundation, Inc. 5 * All Rights Reserved 6 * 7 * Permission to use, copy, modify, and distribute this software and 8 * its documentation for any purpose and without fee is hereby granted, 9 * provided that the above copyright notice appears in all copies and 10 * that both the copyright notice and this permission notice appear in 11 * supporting documentation. 12 * 13 * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 14 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 15 * FOR A PARTICULAR PURPOSE. 16 * 17 * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 18 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 19 * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 20 * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 21 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 22 * 23 */ 24 25 #include <sys/param.h> 26 #include <sys/malloc.h> 27 #include <sys/systm.h> 28 29 #include <uvm/uvm_extern.h> 30 31 #include <machine/pio.h> 32 #include <macppc/dev/dbdma.h> 33 34 #define eieio() __asm__ volatile("eieio") 35 36 37 dbdma_command_t *dbdma_alloc_commands = NULL; 38 39 void 40 dbdma_start(dmap, commands) 41 dbdma_regmap_t *dmap; 42 dbdma_command_t *commands; 43 { 44 unsigned long addr = vtophys((vaddr_t)commands); 45 46 if (addr & 0xf) 47 panic("dbdma_start command structure not 16-byte aligned"); 48 49 dmap->d_intselect = 0xff; /* Endian magic - clear out interrupts */ 50 DBDMA_ST4_ENDIAN(&dmap->d_control, 51 DBDMA_CLEAR_CNTRL( (DBDMA_CNTRL_ACTIVE | 52 DBDMA_CNTRL_DEAD | 53 DBDMA_CNTRL_WAKE | 54 DBDMA_CNTRL_FLUSH | 55 DBDMA_CNTRL_PAUSE | 56 DBDMA_CNTRL_RUN ))); 57 eieio(); 58 59 while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE) 60 eieio(); 61 62 dmap->d_cmdptrhi = 0; eieio();/* 64-bit not yet */ 63 DBDMA_ST4_ENDIAN(&dmap->d_cmdptrlo, addr); eieio(); 64 65 DBDMA_ST4_ENDIAN(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_RUN)); 66 eieio(); 67 } 68 69 void 70 dbdma_stop(dmap) 71 dbdma_regmap_t *dmap; 72 { 73 out32rb(&dmap->d_control, DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_RUN) | 74 DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH)); 75 76 while (in32rb(&dmap->d_status) & 77 (DBDMA_CNTRL_ACTIVE|DBDMA_CNTRL_FLUSH)); 78 } 79 80 void 81 dbdma_flush(dmap) 82 dbdma_regmap_t *dmap; 83 { 84 out32rb(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH)); 85 86 while (in32rb(&dmap->d_status) & (DBDMA_CNTRL_FLUSH)); 87 } 88 89 void 90 dbdma_reset(dmap) 91 dbdma_regmap_t *dmap; 92 { 93 out32rb(&dmap->d_control, 94 DBDMA_CLEAR_CNTRL( (DBDMA_CNTRL_ACTIVE | 95 DBDMA_CNTRL_DEAD | 96 DBDMA_CNTRL_WAKE | 97 DBDMA_CNTRL_FLUSH | 98 DBDMA_CNTRL_PAUSE | 99 DBDMA_CNTRL_RUN ))); 100 101 while (in32rb(&dmap->d_status) & DBDMA_CNTRL_RUN); 102 } 103 104 void 105 dbdma_continue(dmap) 106 dbdma_regmap_t *dmap; 107 { 108 out32rb(&dmap->d_control, 109 DBDMA_SET_CNTRL(DBDMA_CNTRL_RUN | DBDMA_CNTRL_WAKE) | 110 DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_PAUSE | DBDMA_CNTRL_DEAD)); 111 } 112 113 void 114 dbdma_pause(dmap) 115 dbdma_regmap_t *dmap; 116 { 117 DBDMA_ST4_ENDIAN(&dmap->d_control,DBDMA_SET_CNTRL(DBDMA_CNTRL_PAUSE)); 118 eieio(); 119 120 while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE) 121 eieio(); 122 } 123 124 dbdma_command_t * 125 dbdma_alloc(size) 126 int size; 127 { 128 u_int buf; 129 130 buf = (u_int)malloc(size + 0x0f, M_DEVBUF, M_WAITOK); 131 buf = (buf + 0x0f) & ~0x0f; 132 133 return (dbdma_command_t *)buf; 134 } 135