1 /* $NetBSD: dbdma.h,v 1.3 2001/06/19 12:02:56 simonb Exp $ */ 2 3 /* 4 * Copyright 1991-1998 by Open Software Foundation, Inc. 5 * All Rights Reserved 6 * 7 * Permission to use, copy, modify, and distribute this software and 8 * its documentation for any purpose and without fee is hereby granted, 9 * provided that the above copyright notice appears in all copies and 10 * that both the copyright notice and this permission notice appear in 11 * supporting documentation. 12 * 13 * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 14 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 15 * FOR A PARTICULAR PURPOSE. 16 * 17 * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 18 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 19 * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 20 * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 21 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 22 * 23 */ 24 25 #ifndef _POWERMAC_DBDMA_H_ 26 #define _POWERMAC_DBDMA_H_ 27 28 #define DBDMA_CMD_OUT_MORE 0 29 #define DBDMA_CMD_OUT_LAST 1 30 #define DBDMA_CMD_IN_MORE 2 31 #define DBDMA_CMD_IN_LAST 3 32 #define DBDMA_CMD_STORE_QUAD 4 33 #define DBDMA_CMD_LOAD_QUAD 5 34 #define DBDMA_CMD_NOP 6 35 #define DBDMA_CMD_STOP 7 36 37 /* Keys */ 38 39 #define DBDMA_KEY_STREAM0 0 40 #define DBDMA_KEY_STREAM1 1 41 #define DBDMA_KEY_STREAM2 2 42 #define DBDMA_KEY_STREAM3 3 43 44 /* value 4 is reserved */ 45 #define DBDMA_KEY_REGS 5 46 #define DBDMA_KEY_SYSTEM 6 47 #define DBDMA_KEY_DEVICE 7 48 49 #define DBDMA_INT_NEVER 0 50 #define DBDMA_INT_IF_TRUE 1 51 #define DBDMA_INT_IF_FALSE 2 52 #define DBDMA_INT_ALWAYS 3 53 54 #define DBDMA_BRANCH_NEVER 0 55 #define DBDMA_BRANCH_IF_TRUE 1 56 #define DBDMA_BRANCH_IF_FALSE 2 57 #define DBDMA_BRANCH_ALWAYS 3 58 59 #define DBDMA_WAIT_NEVER 0 60 #define DBDMA_WAIT_IF_TRUE 1 61 #define DBDMA_WAIT_IF_FALSE 2 62 #define DBDMA_WAIT_ALWAYS 3 63 64 65 /* Channels */ 66 67 #define DBDMA_SCSI0 0x0 68 #define DBDMA_CURIO_SCSI DBDMA_SCSI0 69 #define DBDMA_FLOPPY 0x1 70 #define DBDMA_ETHERNET_TX 0x2 71 #define DBDMA_ETHERNET_RV 0x3 72 #define DBDMA_SCC_XMIT_A 0x4 73 #define DBDMA_SCC_RECV_A 0x5 74 #define DBDMA_SCC_XMIT_B 0x6 75 #define DBDMA_SCC_RECV_B 0x7 76 #define DBDMA_AUDIO_OUT 0x8 77 #define DBDMA_AUDIO_IN 0x9 78 #define DBDMA_SCSI1 0xA 79 80 /* Control register values (in little endian) */ 81 82 #define DBDMA_STATUS_MASK 0x000000ff /* Status Mask */ 83 #define DBDMA_CNTRL_BRANCH 0x00000100 84 /* 0x200 reserved */ 85 #define DBDMA_CNTRL_ACTIVE 0x00000400 86 #define DBDMA_CNTRL_DEAD 0x00000800 87 #define DBDMA_CNTRL_WAKE 0x00001000 88 #define DBDMA_CNTRL_FLUSH 0x00002000 89 #define DBDMA_CNTRL_PAUSE 0x00004000 90 #define DBDMA_CNTRL_RUN 0x00008000 91 92 #define DBDMA_SET_CNTRL(x) ( ((x) | (x) << 16) ) 93 #define DBDMA_CLEAR_CNTRL(x) ( (x) << 16) 94 95 96 #define DBDMA_REGMAP(channel) \ 97 (dbdma_regmap_t *)((v_u_char *) POWERMAC_IO(PCI_DMA_BASE_PHYS) \ 98 + (channel << 8)) 99 100 /* This struct is layout in little endian format */ 101 102 struct dbdma_command { 103 u_int16_t d_count; 104 u_int16_t d_command; 105 u_int32_t d_address; 106 u_int32_t d_cmddep; 107 u_int16_t d_resid; 108 u_int16_t d_status; 109 }; 110 111 typedef struct dbdma_command dbdma_command_t; 112 113 #define DBDMA_BUILD_CMD(d, cmd, key, interrupt, wait, branch) { \ 114 dbdma_st16(&(d)->d_command, \ 115 ((cmd) << 12) | ((key) << 8) | \ 116 ((interrupt) << 4) | \ 117 ((branch) << 2) | (wait)); \ 118 } 119 120 #define DBDMA_BUILD(d, cmd, key, count, address, interrupt, wait, branch) { \ 121 dbdma_st16(&(d)->d_count, count); \ 122 dbdma_st32(&(d)->d_address, address); \ 123 (d)->d_resid = 0; \ 124 (d)->d_status = 0; \ 125 (d)->d_cmddep = 0; \ 126 dbdma_st16(&(d)->d_command, \ 127 ((cmd) << 12) | ((key) << 8) | \ 128 ((interrupt) << 4) | \ 129 ((branch) << 2) | (wait)); \ 130 } 131 132 static __inline__ void dbdma_st32(volatile u_int32_t *, u_int32_t); 133 static __inline__ void dbdma_st16(volatile u_int16_t *, u_int16_t); 134 static __inline__ u_int32_t dbdma_ld32(volatile u_int32_t *); 135 static __inline__ u_int16_t dbdma_ld16(volatile u_int16_t *); 136 137 static __inline__ void 138 dbdma_st32(a, x) 139 volatile u_int32_t *a; 140 u_int32_t x; 141 { 142 __asm__ volatile 143 ("stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory"); 144 } 145 146 static __inline__ void 147 dbdma_st16(a, x) 148 volatile u_int16_t *a; 149 u_int16_t x; 150 { 151 __asm__ volatile 152 ("sthbrx %0,0,%1" : : "r" (x), "r" (a) : "memory"); 153 } 154 155 static __inline__ u_int32_t 156 dbdma_ld32(a) 157 volatile u_int32_t *a; 158 { 159 u_int32_t swap; 160 161 __asm__ volatile 162 ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a)); 163 164 return swap; 165 } 166 167 static __inline__ u_int16_t 168 dbdma_ld16(a) 169 volatile u_int16_t *a; 170 { 171 u_int16_t swap; 172 173 __asm__ volatile 174 ("lhbrx %0,0,%1" : "=r" (swap) : "r" (a)); 175 176 return swap; 177 } 178 179 #define DBDMA_LD4_ENDIAN(a) dbdma_ld32(a) 180 #define DBDMA_ST4_ENDIAN(a, x) dbdma_st32(a, x) 181 182 /* 183 * DBDMA Channel layout 184 * 185 * NOTE - This structure is in little-endian format. 186 */ 187 188 struct dbdma_regmap { 189 u_int32_t d_control; /* Control Register */ 190 u_int32_t d_status; /* DBDMA Status Register */ 191 u_int32_t d_cmdptrhi; /* MSB of command pointer (not used yet) */ 192 u_int32_t d_cmdptrlo; /* LSB of command pointer */ 193 u_int32_t d_intselect; /* Interrupt Select */ 194 u_int32_t d_branch; /* Branch selection */ 195 u_int32_t d_wait; /* Wait selection */ 196 u_int32_t d_transmode; /* Transfer modes */ 197 u_int32_t d_dataptrhi; /* MSB of Data Pointer */ 198 u_int32_t d_dataptrlo; /* LSB of Data Pointer */ 199 u_int32_t d_reserved; /* Reserved for the moment */ 200 u_int32_t d_branchptrhi; /* MSB of Branch Pointer */ 201 u_int32_t d_branchptrlo; /* LSB of Branch Pointer */ 202 /* The remaining fields are undefinied and unimplemented */ 203 }; 204 205 typedef volatile struct dbdma_regmap dbdma_regmap_t; 206 207 /* DBDMA routines */ 208 209 void dbdma_start(dbdma_regmap_t *channel, dbdma_command_t *commands); 210 void dbdma_stop(dbdma_regmap_t *channel); 211 void dbdma_flush(dbdma_regmap_t *channel); 212 void dbdma_reset(dbdma_regmap_t *channel); 213 void dbdma_continue(dbdma_regmap_t *channel); 214 void dbdma_pause(dbdma_regmap_t *channel); 215 216 dbdma_command_t *dbdma_alloc(int); /* Allocate command structures */ 217 218 #endif /* !defined(_POWERMAC_DBDMA_H_) */ 219