1 /* $NetBSD: esp.c,v 1.13 2001/04/25 17:53:15 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian@tfs.com) and 76 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/errno.h> 84 #include <sys/ioctl.h> 85 #include <sys/device.h> 86 #include <sys/buf.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/queue.h> 90 #include <sys/malloc.h> 91 92 #include <uvm/uvm_param.h> /* for trunc_page */ 93 94 #include <dev/scsipi/scsi_all.h> 95 #include <dev/scsipi/scsipi_all.h> 96 #include <dev/scsipi/scsiconf.h> 97 #include <dev/scsipi/scsi_message.h> 98 99 #include <dev/ofw/openfirm.h> 100 101 #include <machine/cpu.h> 102 #include <machine/autoconf.h> 103 #include <machine/pio.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <macppc/dev/dbdma.h> 109 #include <macppc/dev/espvar.h> 110 111 void espattach __P((struct device *, struct device *, void *)); 112 int espmatch __P((struct device *, struct cfdata *, void *)); 113 114 /* Linkup to the rest of the kernel */ 115 struct cfattach esp_ca = { 116 sizeof(struct esp_softc), espmatch, espattach 117 }; 118 119 /* 120 * Functions and the switch for the MI code. 121 */ 122 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 123 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 124 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 125 void esp_dma_reset __P((struct ncr53c9x_softc *)); 126 int esp_dma_intr __P((struct ncr53c9x_softc *)); 127 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 128 size_t *, int, size_t *)); 129 void esp_dma_go __P((struct ncr53c9x_softc *)); 130 void esp_dma_stop __P((struct ncr53c9x_softc *)); 131 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 132 133 struct ncr53c9x_glue esp_glue = { 134 esp_read_reg, 135 esp_write_reg, 136 esp_dma_isintr, 137 esp_dma_reset, 138 esp_dma_intr, 139 esp_dma_setup, 140 esp_dma_go, 141 esp_dma_stop, 142 esp_dma_isactive, 143 NULL, /* gl_clear_latched_intr */ 144 }; 145 146 static int espdmaintr __P((struct esp_softc *)); 147 static void esp_shutdownhook __P((void *)); 148 149 int 150 espmatch(parent, cf, aux) 151 struct device *parent; 152 struct cfdata *cf; 153 void *aux; 154 { 155 struct confargs *ca = aux; 156 157 if (strcmp(ca->ca_name, "53c94") != 0) 158 return 0; 159 160 if (ca->ca_nreg != 16) 161 return 0; 162 if (ca->ca_nintr != 8) 163 return 0; 164 165 return 1; 166 } 167 168 /* 169 * Attach this instance, and then all the sub-devices 170 */ 171 void 172 espattach(parent, self, aux) 173 struct device *parent, *self; 174 void *aux; 175 { 176 register struct confargs *ca = aux; 177 struct esp_softc *esc = (void *)self; 178 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 179 u_int *reg; 180 int sz; 181 182 /* 183 * Set up glue for MI code early; we use some of it here. 184 */ 185 sc->sc_glue = &esp_glue; 186 187 esc->sc_node = ca->ca_node; 188 esc->sc_pri = ca->ca_intr[0]; 189 printf(" irq %d", esc->sc_pri); 190 191 /* 192 * Map my registers in. 193 */ 194 reg = ca->ca_reg; 195 esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1]); 196 esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3]); 197 198 /* Allocate 16-byte aligned dma command space */ 199 esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 200 201 /* Other settings */ 202 sc->sc_id = 7; 203 sz = OF_getprop(ca->ca_node, "clock-frequency", 204 &sc->sc_freq, sizeof(int)); 205 if (sz != sizeof(int)) 206 sc->sc_freq = 25000000; 207 208 /* gimme Mhz */ 209 sc->sc_freq /= 1000000; 210 211 /* esc->sc_dma->sc_esp = esc;*/ 212 213 /* 214 * XXX More of this should be in ncr53c9x_attach(), but 215 * XXX should we really poke around the chip that much in 216 * XXX the MI code? Think about this more... 217 */ 218 219 /* 220 * Set up static configuration info. 221 */ 222 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 223 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 224 sc->sc_cfg3 = NCRCFG3_CDB; 225 sc->sc_rev = NCR_VARIANT_NCR53C94; 226 227 /* 228 * XXX minsync and maxxfer _should_ be set up in MI code, 229 * XXX but it appears to have some dependency on what sort 230 * XXX of DMA we're hooked up to, etc. 231 */ 232 233 /* 234 * This is the value used to start sync negotiations 235 * Note that the NCR register "SYNCTP" is programmed 236 * in "clocks per byte", and has a minimum value of 4. 237 * The SCSI period used in negotiation is one-fourth 238 * of the time (in nanoseconds) needed to transfer one byte. 239 * Since the chip's clock is given in MHz, we have the following 240 * formula: 4 * period = (1000 / freq) * 4 241 */ 242 sc->sc_minsync = 1000 / sc->sc_freq; 243 244 sc->sc_maxxfer = 64 * 1024; 245 246 /* and the interuppts */ 247 intr_establish(esc->sc_pri, IST_LEVEL, IPL_BIO, ncr53c9x_intr, sc); 248 249 /* Reset SCSI bus when halt. */ 250 shutdownhook_establish(esp_shutdownhook, sc); 251 252 /* Do the common parts of attachment. */ 253 sc->sc_adapter.adapt_minphys = minphys; 254 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 255 ncr53c9x_attach(sc); 256 257 /* Turn on target selection using the `dma' method */ 258 sc->sc_features |= NCR_F_DMASELECT; 259 } 260 261 /* 262 * Glue functions. 263 */ 264 265 u_char 266 esp_read_reg(sc, reg) 267 struct ncr53c9x_softc *sc; 268 int reg; 269 { 270 struct esp_softc *esc = (struct esp_softc *)sc; 271 272 return in8(&esc->sc_reg[reg * 16]); 273 /*return (esc->sc_reg[reg * 16]);*/ 274 } 275 276 void 277 esp_write_reg(sc, reg, val) 278 struct ncr53c9x_softc *sc; 279 int reg; 280 u_char val; 281 { 282 struct esp_softc *esc = (struct esp_softc *)sc; 283 u_char v = val; 284 285 out8(&esc->sc_reg[reg * 16], v); 286 /*esc->sc_reg[reg * 16] = v;*/ 287 } 288 289 int 290 esp_dma_isintr(sc) 291 struct ncr53c9x_softc *sc; 292 { 293 return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 294 } 295 296 void 297 esp_dma_reset(sc) 298 struct ncr53c9x_softc *sc; 299 { 300 struct esp_softc *esc = (struct esp_softc *)sc; 301 302 dbdma_stop(esc->sc_dmareg); 303 esc->sc_dmaactive = 0; 304 } 305 306 int 307 esp_dma_intr(sc) 308 struct ncr53c9x_softc *sc; 309 { 310 struct esp_softc *esc = (struct esp_softc *)sc; 311 312 return (espdmaintr(esc)); 313 } 314 315 int 316 esp_dma_setup(sc, addr, len, datain, dmasize) 317 struct ncr53c9x_softc *sc; 318 caddr_t *addr; 319 size_t *len; 320 int datain; 321 size_t *dmasize; 322 { 323 struct esp_softc *esc = (struct esp_softc *)sc; 324 dbdma_command_t *cmdp; 325 u_int cmd; 326 u_int va; 327 int count, offset; 328 329 cmdp = esc->sc_dmacmd; 330 cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 331 332 count = *dmasize; 333 334 if (count / NBPG > 32) 335 panic("esp: transfer size >= 128k"); 336 337 esc->sc_dmaaddr = addr; 338 esc->sc_dmalen = len; 339 esc->sc_dmasize = count; 340 341 va = (u_int)*esc->sc_dmaaddr; 342 offset = va & PGOFSET; 343 344 /* if va is not page-aligned, setup the first page */ 345 if (offset != 0) { 346 int rest = NBPG - offset; /* the rest of the page */ 347 348 if (count > rest) { /* if continues to next page */ 349 DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((caddr_t)va), 350 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 351 DBDMA_BRANCH_NEVER); 352 count -= rest; 353 va += rest; 354 cmdp++; 355 } 356 } 357 358 /* now va is page-aligned */ 359 while (count > NBPG) { 360 DBDMA_BUILD(cmdp, cmd, 0, NBPG, kvtop((caddr_t)va), 361 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 362 count -= NBPG; 363 va += NBPG; 364 cmdp++; 365 } 366 367 /* the last page (count <= NBPG here) */ 368 cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 369 DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((caddr_t)va), 370 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 371 cmdp++; 372 373 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 374 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 375 376 esc->sc_dma_direction = datain ? D_WRITE : 0; 377 378 return 0; 379 } 380 381 void 382 esp_dma_go(sc) 383 struct ncr53c9x_softc *sc; 384 { 385 struct esp_softc *esc = (struct esp_softc *)sc; 386 387 dbdma_start(esc->sc_dmareg, esc->sc_dmacmd); 388 esc->sc_dmaactive = 1; 389 } 390 391 void 392 esp_dma_stop(sc) 393 struct ncr53c9x_softc *sc; 394 { 395 struct esp_softc *esc = (struct esp_softc *)sc; 396 397 dbdma_stop(esc->sc_dmareg); 398 esc->sc_dmaactive = 0; 399 } 400 401 int 402 esp_dma_isactive(sc) 403 struct ncr53c9x_softc *sc; 404 { 405 struct esp_softc *esc = (struct esp_softc *)sc; 406 407 return (esc->sc_dmaactive); 408 } 409 410 411 /* 412 * Pseudo (chained) interrupt from the esp driver to kick the 413 * current running DMA transfer. I am replying on espintr() to 414 * pickup and clean errors for now 415 * 416 * return 1 if it was a DMA continue. 417 */ 418 int 419 espdmaintr(sc) 420 struct esp_softc *sc; 421 { 422 struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc; 423 int trans, resid; 424 u_long csr = sc->sc_dma_direction; 425 426 #if 0 427 if (csr & D_ERR_PEND) { 428 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 429 DMACSR(sc) |= D_INVALIDATE; 430 printf("%s: error: csr=%s\n", nsc->sc_dev.dv_xname, 431 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 432 return -1; 433 } 434 #endif 435 436 /* This is an "assertion" :) */ 437 if (sc->sc_dmaactive == 0) 438 panic("dmaintr: DMA wasn't active"); 439 440 /* dbdma_flush(sc->sc_dmareg); */ 441 442 /* DMA has stopped */ 443 dbdma_stop(sc->sc_dmareg); 444 sc->sc_dmaactive = 0; 445 446 if (sc->sc_dmasize == 0) { 447 /* A "Transfer Pad" operation completed */ 448 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 449 NCR_READ_REG(nsc, NCR_TCL) | 450 (NCR_READ_REG(nsc, NCR_TCM) << 8), 451 NCR_READ_REG(nsc, NCR_TCL), 452 NCR_READ_REG(nsc, NCR_TCM))); 453 return 0; 454 } 455 456 resid = 0; 457 /* 458 * If a transfer onto the SCSI bus gets interrupted by the device 459 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 460 * as residual since the ESP counter registers get decremented as 461 * bytes are clocked into the FIFO. 462 */ 463 if (!(csr & D_WRITE) && 464 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 465 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 466 } 467 468 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 469 /* 470 * `Terminal count' is off, so read the residue 471 * out of the ESP counter registers. 472 */ 473 resid += (NCR_READ_REG(nsc, NCR_TCL) | 474 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 475 ((nsc->sc_cfg2 & NCRCFG2_FE) 476 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 477 : 0)); 478 479 if (resid == 0 && sc->sc_dmasize == 65536 && 480 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 481 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 482 resid = 65536; 483 } 484 485 trans = sc->sc_dmasize - resid; 486 if (trans < 0) { /* transferred < 0 ? */ 487 #if 0 488 /* 489 * This situation can happen in perfectly normal operation 490 * if the ESP is reselected while using DMA to select 491 * another target. As such, don't print the warning. 492 */ 493 printf("%s: xfer (%d) > req (%d)\n", 494 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 495 #endif 496 trans = sc->sc_dmasize; 497 } 498 499 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 500 NCR_READ_REG(nsc, NCR_TCL), 501 NCR_READ_REG(nsc, NCR_TCM), 502 (nsc->sc_cfg2 & NCRCFG2_FE) 503 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 504 trans, resid)); 505 506 #if 0 507 if (csr & D_WRITE) 508 flushcache(*sc->sc_dmaaddr, trans); 509 #endif 510 511 *sc->sc_dmalen -= trans; 512 *sc->sc_dmaaddr += trans; 513 514 #if 0 /* this is not normal operation just yet */ 515 if (*sc->sc_dmalen == 0 || 516 nsc->sc_phase != nsc->sc_prevphase) 517 return 0; 518 519 /* and again */ 520 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 521 return 1; 522 #endif 523 return 0; 524 } 525 526 void 527 esp_shutdownhook(arg) 528 void *arg; 529 { 530 struct ncr53c9x_softc *sc = arg; 531 532 NCRCMD(sc, NCRCMD_RSTSCSI); 533 } 534