1 /* $NetBSD: esp.c,v 1.15 2002/10/02 05:30:41 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian@tfs.com) and 76 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 #include <sys/types.h> 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/errno.h> 84 #include <sys/ioctl.h> 85 #include <sys/device.h> 86 #include <sys/buf.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/queue.h> 90 #include <sys/malloc.h> 91 92 #include <uvm/uvm_param.h> /* for trunc_page */ 93 94 #include <dev/scsipi/scsi_all.h> 95 #include <dev/scsipi/scsipi_all.h> 96 #include <dev/scsipi/scsiconf.h> 97 #include <dev/scsipi/scsi_message.h> 98 99 #include <dev/ofw/openfirm.h> 100 101 #include <machine/cpu.h> 102 #include <machine/autoconf.h> 103 #include <machine/pio.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <macppc/dev/dbdma.h> 109 #include <macppc/dev/espvar.h> 110 111 void espattach __P((struct device *, struct device *, void *)); 112 int espmatch __P((struct device *, struct cfdata *, void *)); 113 114 /* Linkup to the rest of the kernel */ 115 CFATTACH_DECL(esp, sizeof(struct esp_softc), 116 espmatch, espattach, NULL, NULL); 117 118 /* 119 * Functions and the switch for the MI code. 120 */ 121 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 122 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 123 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 124 void esp_dma_reset __P((struct ncr53c9x_softc *)); 125 int esp_dma_intr __P((struct ncr53c9x_softc *)); 126 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 127 size_t *, int, size_t *)); 128 void esp_dma_go __P((struct ncr53c9x_softc *)); 129 void esp_dma_stop __P((struct ncr53c9x_softc *)); 130 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 131 132 struct ncr53c9x_glue esp_glue = { 133 esp_read_reg, 134 esp_write_reg, 135 esp_dma_isintr, 136 esp_dma_reset, 137 esp_dma_intr, 138 esp_dma_setup, 139 esp_dma_go, 140 esp_dma_stop, 141 esp_dma_isactive, 142 NULL, /* gl_clear_latched_intr */ 143 }; 144 145 static int espdmaintr __P((struct esp_softc *)); 146 static void esp_shutdownhook __P((void *)); 147 148 int 149 espmatch(parent, cf, aux) 150 struct device *parent; 151 struct cfdata *cf; 152 void *aux; 153 { 154 struct confargs *ca = aux; 155 156 if (strcmp(ca->ca_name, "53c94") != 0) 157 return 0; 158 159 if (ca->ca_nreg != 16) 160 return 0; 161 if (ca->ca_nintr != 8) 162 return 0; 163 164 return 1; 165 } 166 167 /* 168 * Attach this instance, and then all the sub-devices 169 */ 170 void 171 espattach(parent, self, aux) 172 struct device *parent, *self; 173 void *aux; 174 { 175 register struct confargs *ca = aux; 176 struct esp_softc *esc = (void *)self; 177 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 178 u_int *reg; 179 int sz; 180 181 /* 182 * Set up glue for MI code early; we use some of it here. 183 */ 184 sc->sc_glue = &esp_glue; 185 186 esc->sc_node = ca->ca_node; 187 esc->sc_pri = ca->ca_intr[0]; 188 printf(" irq %d", esc->sc_pri); 189 190 /* 191 * Map my registers in. 192 */ 193 reg = ca->ca_reg; 194 esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1]); 195 esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3]); 196 197 /* Allocate 16-byte aligned dma command space */ 198 esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 199 200 /* Other settings */ 201 sc->sc_id = 7; 202 sz = OF_getprop(ca->ca_node, "clock-frequency", 203 &sc->sc_freq, sizeof(int)); 204 if (sz != sizeof(int)) 205 sc->sc_freq = 25000000; 206 207 /* gimme Mhz */ 208 sc->sc_freq /= 1000000; 209 210 /* esc->sc_dma->sc_esp = esc;*/ 211 212 /* 213 * XXX More of this should be in ncr53c9x_attach(), but 214 * XXX should we really poke around the chip that much in 215 * XXX the MI code? Think about this more... 216 */ 217 218 /* 219 * Set up static configuration info. 220 */ 221 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 222 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 223 sc->sc_cfg3 = NCRCFG3_CDB; 224 sc->sc_rev = NCR_VARIANT_NCR53C94; 225 226 /* 227 * XXX minsync and maxxfer _should_ be set up in MI code, 228 * XXX but it appears to have some dependency on what sort 229 * XXX of DMA we're hooked up to, etc. 230 */ 231 232 /* 233 * This is the value used to start sync negotiations 234 * Note that the NCR register "SYNCTP" is programmed 235 * in "clocks per byte", and has a minimum value of 4. 236 * The SCSI period used in negotiation is one-fourth 237 * of the time (in nanoseconds) needed to transfer one byte. 238 * Since the chip's clock is given in MHz, we have the following 239 * formula: 4 * period = (1000 / freq) * 4 240 */ 241 sc->sc_minsync = 1000 / sc->sc_freq; 242 243 sc->sc_maxxfer = 64 * 1024; 244 245 /* and the interuppts */ 246 intr_establish(esc->sc_pri, IST_LEVEL, IPL_BIO, ncr53c9x_intr, sc); 247 248 /* Reset SCSI bus when halt. */ 249 shutdownhook_establish(esp_shutdownhook, sc); 250 251 /* Do the common parts of attachment. */ 252 sc->sc_adapter.adapt_minphys = minphys; 253 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 254 ncr53c9x_attach(sc); 255 256 /* Turn on target selection using the `dma' method */ 257 sc->sc_features |= NCR_F_DMASELECT; 258 } 259 260 /* 261 * Glue functions. 262 */ 263 264 u_char 265 esp_read_reg(sc, reg) 266 struct ncr53c9x_softc *sc; 267 int reg; 268 { 269 struct esp_softc *esc = (struct esp_softc *)sc; 270 271 return in8(&esc->sc_reg[reg * 16]); 272 /*return (esc->sc_reg[reg * 16]);*/ 273 } 274 275 void 276 esp_write_reg(sc, reg, val) 277 struct ncr53c9x_softc *sc; 278 int reg; 279 u_char val; 280 { 281 struct esp_softc *esc = (struct esp_softc *)sc; 282 u_char v = val; 283 284 out8(&esc->sc_reg[reg * 16], v); 285 /*esc->sc_reg[reg * 16] = v;*/ 286 } 287 288 int 289 esp_dma_isintr(sc) 290 struct ncr53c9x_softc *sc; 291 { 292 return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 293 } 294 295 void 296 esp_dma_reset(sc) 297 struct ncr53c9x_softc *sc; 298 { 299 struct esp_softc *esc = (struct esp_softc *)sc; 300 301 dbdma_stop(esc->sc_dmareg); 302 esc->sc_dmaactive = 0; 303 } 304 305 int 306 esp_dma_intr(sc) 307 struct ncr53c9x_softc *sc; 308 { 309 struct esp_softc *esc = (struct esp_softc *)sc; 310 311 return (espdmaintr(esc)); 312 } 313 314 int 315 esp_dma_setup(sc, addr, len, datain, dmasize) 316 struct ncr53c9x_softc *sc; 317 caddr_t *addr; 318 size_t *len; 319 int datain; 320 size_t *dmasize; 321 { 322 struct esp_softc *esc = (struct esp_softc *)sc; 323 dbdma_command_t *cmdp; 324 u_int cmd; 325 u_int va; 326 int count, offset; 327 328 cmdp = esc->sc_dmacmd; 329 cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 330 331 count = *dmasize; 332 333 if (count / NBPG > 32) 334 panic("esp: transfer size >= 128k"); 335 336 esc->sc_dmaaddr = addr; 337 esc->sc_dmalen = len; 338 esc->sc_dmasize = count; 339 340 va = (u_int)*esc->sc_dmaaddr; 341 offset = va & PGOFSET; 342 343 /* if va is not page-aligned, setup the first page */ 344 if (offset != 0) { 345 int rest = NBPG - offset; /* the rest of the page */ 346 347 if (count > rest) { /* if continues to next page */ 348 DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((caddr_t)va), 349 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 350 DBDMA_BRANCH_NEVER); 351 count -= rest; 352 va += rest; 353 cmdp++; 354 } 355 } 356 357 /* now va is page-aligned */ 358 while (count > NBPG) { 359 DBDMA_BUILD(cmdp, cmd, 0, NBPG, kvtop((caddr_t)va), 360 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 361 count -= NBPG; 362 va += NBPG; 363 cmdp++; 364 } 365 366 /* the last page (count <= NBPG here) */ 367 cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 368 DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((caddr_t)va), 369 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 370 cmdp++; 371 372 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 373 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 374 375 esc->sc_dma_direction = datain ? D_WRITE : 0; 376 377 return 0; 378 } 379 380 void 381 esp_dma_go(sc) 382 struct ncr53c9x_softc *sc; 383 { 384 struct esp_softc *esc = (struct esp_softc *)sc; 385 386 dbdma_start(esc->sc_dmareg, esc->sc_dmacmd); 387 esc->sc_dmaactive = 1; 388 } 389 390 void 391 esp_dma_stop(sc) 392 struct ncr53c9x_softc *sc; 393 { 394 struct esp_softc *esc = (struct esp_softc *)sc; 395 396 dbdma_stop(esc->sc_dmareg); 397 esc->sc_dmaactive = 0; 398 } 399 400 int 401 esp_dma_isactive(sc) 402 struct ncr53c9x_softc *sc; 403 { 404 struct esp_softc *esc = (struct esp_softc *)sc; 405 406 return (esc->sc_dmaactive); 407 } 408 409 410 /* 411 * Pseudo (chained) interrupt from the esp driver to kick the 412 * current running DMA transfer. I am replying on espintr() to 413 * pickup and clean errors for now 414 * 415 * return 1 if it was a DMA continue. 416 */ 417 int 418 espdmaintr(sc) 419 struct esp_softc *sc; 420 { 421 struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc; 422 int trans, resid; 423 u_long csr = sc->sc_dma_direction; 424 425 #if 0 426 if (csr & D_ERR_PEND) { 427 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 428 DMACSR(sc) |= D_INVALIDATE; 429 printf("%s: error: csr=%s\n", nsc->sc_dev.dv_xname, 430 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 431 return -1; 432 } 433 #endif 434 435 /* This is an "assertion" :) */ 436 if (sc->sc_dmaactive == 0) 437 panic("dmaintr: DMA wasn't active"); 438 439 /* dbdma_flush(sc->sc_dmareg); */ 440 441 /* DMA has stopped */ 442 dbdma_stop(sc->sc_dmareg); 443 sc->sc_dmaactive = 0; 444 445 if (sc->sc_dmasize == 0) { 446 /* A "Transfer Pad" operation completed */ 447 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 448 NCR_READ_REG(nsc, NCR_TCL) | 449 (NCR_READ_REG(nsc, NCR_TCM) << 8), 450 NCR_READ_REG(nsc, NCR_TCL), 451 NCR_READ_REG(nsc, NCR_TCM))); 452 return 0; 453 } 454 455 resid = 0; 456 /* 457 * If a transfer onto the SCSI bus gets interrupted by the device 458 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 459 * as residual since the ESP counter registers get decremented as 460 * bytes are clocked into the FIFO. 461 */ 462 if (!(csr & D_WRITE) && 463 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 464 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 465 } 466 467 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 468 /* 469 * `Terminal count' is off, so read the residue 470 * out of the ESP counter registers. 471 */ 472 resid += (NCR_READ_REG(nsc, NCR_TCL) | 473 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 474 ((nsc->sc_cfg2 & NCRCFG2_FE) 475 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 476 : 0)); 477 478 if (resid == 0 && sc->sc_dmasize == 65536 && 479 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 480 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 481 resid = 65536; 482 } 483 484 trans = sc->sc_dmasize - resid; 485 if (trans < 0) { /* transferred < 0 ? */ 486 #if 0 487 /* 488 * This situation can happen in perfectly normal operation 489 * if the ESP is reselected while using DMA to select 490 * another target. As such, don't print the warning. 491 */ 492 printf("%s: xfer (%d) > req (%d)\n", 493 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 494 #endif 495 trans = sc->sc_dmasize; 496 } 497 498 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 499 NCR_READ_REG(nsc, NCR_TCL), 500 NCR_READ_REG(nsc, NCR_TCM), 501 (nsc->sc_cfg2 & NCRCFG2_FE) 502 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 503 trans, resid)); 504 505 #if 0 506 if (csr & D_WRITE) 507 flushcache(*sc->sc_dmaaddr, trans); 508 #endif 509 510 *sc->sc_dmalen -= trans; 511 *sc->sc_dmaaddr += trans; 512 513 #if 0 /* this is not normal operation just yet */ 514 if (*sc->sc_dmalen == 0 || 515 nsc->sc_phase != nsc->sc_prevphase) 516 return 0; 517 518 /* and again */ 519 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 520 return 1; 521 #endif 522 return 0; 523 } 524 525 void 526 esp_shutdownhook(arg) 527 void *arg; 528 { 529 struct ncr53c9x_softc *sc = arg; 530 531 NCRCMD(sc, NCRCMD_RSTSCSI); 532 } 533