1 /* $NetBSD: if_mc.c,v 1.18 2010/12/20 00:25:37 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym@bga.com> 5 * All rights reserved. 6 * 7 * Portions of this code are based on code by Denton Gentry <denny1@home.com> 8 * and Yanagisawa Takeshi <yanagisw@aa.ap.titech.ac.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 /* 32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra 33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940 34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem 35 * Controller) for DMA to and from the MACE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_mc.c,v 1.18 2010/12/20 00:25:37 matt Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/socket.h> 45 #include <sys/systm.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <dev/ofw/openfirm.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/pio.h> 56 57 #include <macppc/dev/am79c950reg.h> 58 #include <macppc/dev/if_mcvar.h> 59 60 #define MC_BUFSIZE 0x800 61 62 hide int mc_match(struct device *, struct cfdata *, void *); 63 hide void mc_attach(struct device *, struct device *, void *); 64 hide void mc_init(struct mc_softc *sc); 65 hide void mc_putpacket(struct mc_softc *sc, u_int len); 66 hide int mc_dmaintr(void *arg); 67 hide void mc_reset_rxdma(struct mc_softc *sc); 68 hide void mc_reset_txdma(struct mc_softc *sc); 69 hide void mc_select_utp(struct mc_softc *sc); 70 hide void mc_select_aui(struct mc_softc *sc); 71 hide int mc_mediachange(struct mc_softc *sc); 72 hide void mc_mediastatus(struct mc_softc *sc, struct ifmediareq *); 73 74 int mc_supmedia[] = { 75 IFM_ETHER | IFM_10_T, 76 IFM_ETHER | IFM_10_5, 77 /*IFM_ETHER | IFM_AUTO,*/ 78 }; 79 80 #define N_SUPMEDIA (sizeof(mc_supmedia) / sizeof(int)); 81 82 CFATTACH_DECL(mc, sizeof(struct mc_softc), 83 mc_match, mc_attach, NULL, NULL); 84 85 hide int 86 mc_match(struct device *parent, struct cfdata *cf, void *aux) 87 { 88 struct confargs *ca = aux; 89 90 if (strcmp(ca->ca_name, "mace") != 0) 91 return 0; 92 93 /* requires 6 regs */ 94 if (ca->ca_nreg / sizeof(int) != 6) 95 return 0; 96 97 /* requires 3 intrs */ 98 if (ca->ca_nintr / sizeof(int) != 3) 99 return 0; 100 101 return 1; 102 } 103 104 hide void 105 mc_attach(struct device *parent, struct device *self, void *aux) 106 { 107 struct confargs *ca = aux; 108 struct mc_softc *sc = (struct mc_softc *)self; 109 u_int8_t myaddr[ETHER_ADDR_LEN]; 110 u_int *reg; 111 112 sc->sc_node = ca->ca_node; 113 sc->sc_regt = ca->ca_tag; 114 115 reg = ca->ca_reg; 116 reg[0] += ca->ca_baseaddr; 117 reg[2] += ca->ca_baseaddr; 118 reg[4] += ca->ca_baseaddr; 119 120 sc->sc_txdma = mapiodev(reg[2], reg[3]); 121 sc->sc_rxdma = mapiodev(reg[4], reg[5]); 122 bus_space_map(sc->sc_regt, reg[0], reg[1], 0, &sc->sc_regh); 123 124 sc->sc_tail = 0; 125 sc->sc_txdmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 2); 126 sc->sc_rxdmacmd = (void *)dbdma_alloc(sizeof(dbdma_command_t) * 8); 127 memset(sc->sc_txdmacmd, 0, sizeof(dbdma_command_t) * 2); 128 memset(sc->sc_rxdmacmd, 0, sizeof(dbdma_command_t) * 8); 129 130 printf(": irq %d,%d,%d", 131 ca->ca_intr[0], ca->ca_intr[1], ca->ca_intr[2]); 132 133 if (OF_getprop(sc->sc_node, "local-mac-address", myaddr, 6) != 6) { 134 printf(": failed to get MAC address.\n"); 135 return; 136 } 137 138 /* allocate memory for transmit buffer and mark it non-cacheable */ 139 sc->sc_txbuf = malloc(PAGE_SIZE, M_DEVBUF, M_WAITOK); 140 sc->sc_txbuf_phys = kvtop(sc->sc_txbuf); 141 memset(sc->sc_txbuf, 0, PAGE_SIZE); 142 143 /* 144 * allocate memory for receive buffer and mark it non-cacheable 145 * XXX This should use the bus_dma interface, since the buffer 146 * needs to be physically contiguous. However, it seems that 147 * at least on my system, malloc() does allocate contiguous 148 * memory. If it's not, suggest reducing the number of buffers 149 * to 2, which will fit in one 4K page. 150 */ 151 sc->sc_rxbuf = malloc(MC_NPAGES * PAGE_SIZE, M_DEVBUF, M_WAITOK); 152 sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf); 153 memset(sc->sc_rxbuf, 0, MC_NPAGES * PAGE_SIZE); 154 155 if ((int)sc->sc_txbuf & PGOFSET) 156 printf("txbuf is not page-aligned\n"); 157 if ((int)sc->sc_rxbuf & PGOFSET) 158 printf("rxbuf is not page-aligned\n"); 159 160 sc->sc_bus_init = mc_init; 161 sc->sc_putpacket = mc_putpacket; 162 163 164 /* disable receive DMA */ 165 dbdma_reset(sc->sc_rxdma); 166 167 /* disable transmit DMA */ 168 dbdma_reset(sc->sc_txdma); 169 170 /* install interrupt handlers */ 171 /*intr_establish(ca->ca_intr[1], IST_EDGE, IPL_NET, mc_dmaintr, sc);*/ 172 intr_establish(ca->ca_intr[2], IST_EDGE, IPL_NET, mc_dmaintr, sc); 173 intr_establish(ca->ca_intr[0], IST_EDGE, IPL_NET, mcintr, sc); 174 175 sc->sc_biucc = XMTSP_64; 176 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 177 XMTBRST | RCVBRST; 178 /*sc->sc_plscc = PORTSEL_10BT;*/ 179 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 180 181 /* mcsetup returns 1 if something fails */ 182 if (mcsetup(sc, myaddr)) { 183 printf("mcsetup returns non zero\n"); 184 return; 185 } 186 #ifdef NOTYET 187 sc->sc_mediachange = mc_mediachange; 188 sc->sc_mediastatus = mc_mediastatus; 189 sc->sc_supmedia = mc_supmedia; 190 sc->sc_nsupmedia = N_SUPMEDIA; 191 sc->sc_defaultmedia = IFM_ETHER | IFM_10_T; 192 #endif 193 } 194 195 /* Bus-specific initialization */ 196 hide void 197 mc_init(struct mc_softc *sc) 198 { 199 mc_reset_rxdma(sc); 200 mc_reset_txdma(sc); 201 } 202 203 hide void 204 mc_putpacket(struct mc_softc *sc, u_int len) 205 { 206 dbdma_command_t *cmd = sc->sc_txdmacmd; 207 208 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_phys, 209 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 210 211 dbdma_start(sc->sc_txdma, sc->sc_txdmacmd); 212 } 213 214 /* 215 * Interrupt handler for the MACE DMA completion interrupts 216 */ 217 int 218 mc_dmaintr(void *arg) 219 { 220 struct mc_softc *sc = arg; 221 int status, offset, statoff; 222 int datalen, resid; 223 int i, n; 224 dbdma_command_t *cmd; 225 226 /* We've received some packets from the MACE */ 227 228 /* Loop through, processing each of the packets */ 229 i = sc->sc_tail; 230 for (n = 0; n < MC_RXDMABUFS; n++, i++) { 231 if (i == MC_RXDMABUFS) 232 i = 0; 233 234 cmd = &sc->sc_rxdmacmd[i]; 235 /* flushcache(cmd, sizeof(dbdma_command_t)); */ 236 status = in16rb(&cmd->d_status); 237 resid = in16rb(&cmd->d_resid); 238 239 /*if ((status & D_ACTIVE) == 0)*/ 240 if ((status & 0x40) == 0) 241 continue; 242 243 #if 1 244 if (in16rb(&cmd->d_count) != ETHERMTU + 22) 245 printf("bad d_count\n"); 246 #endif 247 248 datalen = in16rb(&cmd->d_count) - resid; 249 datalen -= 4; /* 4 == status bytes */ 250 251 if (datalen < 4 + sizeof(struct ether_header)) { 252 printf("short packet len=%d\n", datalen); 253 /* continue; */ 254 goto next; 255 } 256 257 offset = i * MC_BUFSIZE; 258 statoff = offset + datalen; 259 260 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 261 __asm volatile("eieio"); 262 263 /* flushcache(sc->sc_rxbuf + offset, datalen + 4); */ 264 265 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0]; 266 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1]; 267 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2]; 268 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3]; 269 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset; 270 271 mc_rint(sc); 272 273 next: 274 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 275 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 276 __asm volatile("eieio"); 277 cmd->d_status = 0; 278 cmd->d_resid = 0; 279 sc->sc_tail = i + 1; 280 } 281 282 dbdma_continue(sc->sc_rxdma); 283 284 return 1; 285 } 286 287 hide void 288 mc_reset_rxdma(struct mc_softc *sc) 289 { 290 dbdma_command_t *cmd = sc->sc_rxdmacmd; 291 dbdma_regmap_t *dmareg = sc->sc_rxdma; 292 int i; 293 u_int8_t maccc; 294 295 /* Disable receiver, reset the DMA channels */ 296 maccc = NIC_GET(sc, MACE_MACCC); 297 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 298 299 dbdma_reset(dmareg); 300 301 for (i = 0; i < MC_RXDMABUFS; i++) { 302 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, ETHERMTU + 22, 303 sc->sc_rxbuf_phys + MC_BUFSIZE * i, DBDMA_INT_ALWAYS, 304 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 305 cmd++; 306 } 307 308 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 309 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 310 out32rb(&cmd->d_cmddep, kvtop((void *)sc->sc_rxdmacmd)); 311 cmd++; 312 313 dbdma_start(dmareg, sc->sc_rxdmacmd); 314 315 sc->sc_tail = 0; 316 317 /* Reenable receiver, reenable DMA */ 318 NIC_PUT(sc, MACE_MACCC, maccc); 319 } 320 321 hide void 322 mc_reset_txdma(struct mc_softc *sc) 323 { 324 dbdma_command_t *cmd = sc->sc_txdmacmd; 325 dbdma_regmap_t *dmareg = sc->sc_txdma; 326 u_int8_t maccc; 327 328 /* disable transmitter */ 329 maccc = NIC_GET(sc, MACE_MACCC); 330 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 331 332 dbdma_reset(dmareg); 333 334 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_phys, 335 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 336 cmd++; 337 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 338 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 339 340 out32rb(&dmareg->d_cmdptrhi, 0); 341 out32rb(&dmareg->d_cmdptrlo, kvtop((void *)sc->sc_txdmacmd)); 342 343 /* restore old value */ 344 NIC_PUT(sc, MACE_MACCC, maccc); 345 } 346 347 void 348 mc_select_utp(struct mc_softc *sc) 349 { 350 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 351 } 352 353 void 354 mc_select_aui(struct mc_softc *sc) 355 { 356 sc->sc_plscc = PORTSEL_AUI; 357 } 358 359 int 360 mc_mediachange(struct mc_softc *sc) 361 { 362 struct ifmedia *ifm = &sc->sc_media; 363 364 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 365 return EINVAL; 366 367 switch (IFM_SUBTYPE(ifm->ifm_media)) { 368 369 case IFM_10_T: 370 mc_select_utp(sc); 371 break; 372 373 case IFM_10_5: 374 mc_select_aui(sc); 375 break; 376 377 default: 378 return EINVAL; 379 } 380 381 return 0; 382 } 383 384 void 385 mc_mediastatus(struct mc_softc *sc, struct ifmediareq *ifmr) 386 { 387 if (sc->sc_plscc == PORTSEL_AUI) 388 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 389 else 390 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 391 } 392