1 /* $NetBSD: if_aumac.c,v 1.6 2002/10/02 15:52:24 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.6 2002/10/02 15:52:24 thorpej Exp $"); 50 51 #include "bpfilter.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/ioctl.h> 61 #include <sys/errno.h> 62 #include <sys/device.h> 63 #include <sys/queue.h> 64 65 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_ether.h> 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 #include <machine/endian.h> 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <mips/alchemy/include/aureg.h> 84 #include <mips/alchemy/include/auvar.h> 85 #include <mips/alchemy/include/aubusvar.h> 86 #include <mips/alchemy/dev/if_aumacreg.h> 87 88 /* 89 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 90 * must consist of a single DMA segment, and must be aligned to a 2K 91 * boundary. Therefore, this driver does not perform DMA directly 92 * to/from mbufs. Instead, we copy the data to/from buffers allocated 93 * at device attach time. 94 * 95 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 96 * there's little point in not making assumptions based on the CPU type. 97 * We also program the Au1X00 cache to be DMA coherent, so the buffers 98 * are accessed via KSEG0 addresses. 99 */ 100 #define AUMAC_NTXDESC 4 101 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 102 103 #define AUMAC_NRXDESC 4 104 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 105 106 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 107 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 108 109 #define AUMAC_TXBUF_OFFSET 0 110 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 111 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 112 113 struct aumac_buf { 114 caddr_t buf_vaddr; /* virtual address of buffer */ 115 bus_addr_t buf_paddr; /* DMA address of buffer */ 116 }; 117 118 /* 119 * Software state per device. 120 */ 121 struct aumac_softc { 122 struct device sc_dev; /* generic device information */ 123 bus_space_tag_t sc_st; /* bus space tag */ 124 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 125 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 126 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 127 struct ethercom sc_ethercom; /* Ethernet common data */ 128 void *sc_sdhook; /* shutdown hook */ 129 130 void *sc_ih; /* interrupt cookie */ 131 132 struct mii_data sc_mii; /* MII/media information */ 133 134 struct callout sc_tick_ch; /* tick callout */ 135 136 /* Transmit and receive buffers */ 137 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 138 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 139 caddr_t sc_bufaddr; 140 141 int sc_txfree; /* number of free Tx descriptors */ 142 int sc_txnext; /* next Tx descriptor to use */ 143 int sc_txdirty; /* first dirty Tx descriptor */ 144 145 int sc_rxptr; /* next ready Rx descriptor */ 146 147 #ifdef AUMAC_EVENT_COUNTERS 148 struct evcnt sc_ev_txstall; /* Tx stalled */ 149 struct evcnt sc_ev_rxstall; /* Rx stalled */ 150 struct evcnt sc_ev_txintr; /* Tx interrupts */ 151 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 152 #endif 153 154 uint32_t sc_control; /* MAC_CONTROL contents */ 155 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 156 }; 157 158 #ifdef AUMAC_EVENT_COUNTERS 159 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 160 #endif 161 162 #define AUMAC_INIT_RXDESC(sc, x) \ 163 do { \ 164 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 165 MACDMA_RX_STAT((x)), 0); \ 166 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 167 MACDMA_RX_ADDR((x)), \ 168 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 169 } while (/*CONSTCOND*/0) 170 171 static void aumac_start(struct ifnet *); 172 static void aumac_watchdog(struct ifnet *); 173 static int aumac_ioctl(struct ifnet *, u_long, caddr_t); 174 static int aumac_init(struct ifnet *); 175 static void aumac_stop(struct ifnet *, int); 176 177 static void aumac_shutdown(void *); 178 179 static void aumac_tick(void *); 180 181 static void aumac_set_filter(struct aumac_softc *); 182 183 static void aumac_powerup(struct aumac_softc *); 184 static void aumac_powerdown(struct aumac_softc *); 185 186 static int aumac_intr(void *); 187 static void aumac_txintr(struct aumac_softc *); 188 static void aumac_rxintr(struct aumac_softc *); 189 190 static int aumac_mii_readreg(struct device *, int, int); 191 static void aumac_mii_writereg(struct device *, int, int, int); 192 static void aumac_mii_statchg(struct device *); 193 static int aumac_mii_wait(struct aumac_softc *, const char *); 194 195 static int aumac_mediachange(struct ifnet *); 196 static void aumac_mediastatus(struct ifnet *, struct ifmediareq *); 197 198 static int aumac_match(struct device *, struct cfdata *, void *); 199 static void aumac_attach(struct device *, struct device *, void *); 200 201 int aumac_copy_small = 0; 202 203 CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 204 aumac_match, aumac_attach, NULL, NULL); 205 206 static const struct { 207 bus_addr_t mac_base; 208 bus_addr_t macen_base; 209 bus_addr_t macdma_base; 210 } regmap[] = { 211 { MAC0_BASE, MAC0_ENABLE, MAC0_DMA_BASE }, 212 { MAC1_BASE, MAC1_ENABLE, MAC1_DMA_BASE }, 213 }; 214 215 static int 216 aumac_match(struct device *parent, struct cfdata *cf, void *aux) 217 { 218 struct aubus_attach_args *aa = aux; 219 220 if (strcmp(aa->aa_name, cf->cf_name) == 0) 221 return (1); 222 223 return (0); 224 } 225 226 static void 227 aumac_attach(struct device *parent, struct device *self, void *aux) 228 { 229 char prop_name[sizeof("0xffffffff:mac-addr") + 1]; 230 uint8_t enaddr[ETHER_ADDR_LEN]; 231 struct aumac_softc *sc = (void *) self; 232 struct aubus_attach_args *aa = aux; 233 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 234 struct pglist pglist; 235 paddr_t bufaddr; 236 caddr_t vbufaddr; 237 int i; 238 239 callout_init(&sc->sc_tick_ch); 240 241 printf(": Au1X00 10/100 Ethernet\n"); 242 243 sc->sc_st = aa->aa_st; 244 245 /* Get the MAC address. */ 246 snprintf(prop_name, sizeof(prop_name), "%p:mac-addr", self); 247 if (alchemy_info_get(prop_name, enaddr, sizeof(enaddr)) == -1) { 248 printf("%s: unable to determine MAC address\n", 249 sc->sc_dev.dv_xname); 250 return; 251 } 252 253 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 254 ether_sprintf(enaddr)); 255 256 /* Map the device. */ 257 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 258 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 259 printf("%s: unable to map MAC registers\n", 260 sc->sc_dev.dv_xname); 261 return; 262 } 263 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 264 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 265 printf("%s: unable to map MACEN registers\n", 266 sc->sc_dev.dv_xname); 267 return; 268 } 269 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 270 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 271 printf("%s: unable to map MACDMA registers\n", 272 sc->sc_dev.dv_xname); 273 return; 274 } 275 276 /* Make sure the MAC is powered off. */ 277 aumac_powerdown(sc); 278 279 /* Hook up the interrupt handler. */ 280 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 281 aumac_intr, sc); 282 if (sc->sc_ih == NULL) { 283 printf("%s: unable to register interrupt handler\n", 284 sc->sc_dev.dv_xname); 285 return; 286 } 287 288 /* 289 * Allocate space for the transmit and receive buffers. 290 */ 291 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 292 &pglist, 1, 0)) 293 return; 294 295 bufaddr = TAILQ_FIRST(&pglist)->phys_addr; 296 vbufaddr = (void *)MIPS_PHYS_TO_KSEG0(bufaddr); 297 298 for (i = 0; i < AUMAC_NTXDESC; i++) { 299 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 300 301 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 302 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 303 } 304 305 for (i = 0; i < AUMAC_NRXDESC; i++) { 306 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 307 308 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 309 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 310 } 311 312 /* 313 * Power up the MAC before accessing any MAC registers (including 314 * MII configuration. 315 */ 316 aumac_powerup(sc); 317 318 /* 319 * Initialize the media structures and probe the MII. 320 */ 321 sc->sc_mii.mii_ifp = ifp; 322 sc->sc_mii.mii_readreg = aumac_mii_readreg; 323 sc->sc_mii.mii_writereg = aumac_mii_writereg; 324 sc->sc_mii.mii_statchg = aumac_mii_statchg; 325 ifmedia_init(&sc->sc_mii.mii_media, 0, aumac_mediachange, 326 aumac_mediastatus); 327 328 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 329 MII_OFFSET_ANY, 0); 330 331 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 332 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 333 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 334 } else 335 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 336 337 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 338 ifp->if_softc = sc; 339 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 340 ifp->if_ioctl = aumac_ioctl; 341 ifp->if_start = aumac_start; 342 ifp->if_watchdog = aumac_watchdog; 343 ifp->if_init = aumac_init; 344 ifp->if_stop = aumac_stop; 345 IFQ_SET_READY(&ifp->if_snd); 346 347 /* Attach the interface. */ 348 if_attach(ifp); 349 ether_ifattach(ifp, enaddr); 350 351 #ifdef AUMAC_EVENT_COUNTERS 352 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 353 NULL, sc->sc_dev.dv_xname, "txstall"); 354 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 355 NULL, sc->sc_dev.dv_xname, "rxstall"); 356 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 357 NULL, sc->sc_dev.dv_xname, "txintr"); 358 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 359 NULL, sc->sc_dev.dv_xname, "txintr"); 360 #endif 361 362 /* Make sure the interface is shutdown during reboot. */ 363 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 364 if (sc->sc_sdhook == NULL) 365 printf("%s: WARNING: unable to establish shutdown hook\n", 366 sc->sc_dev.dv_xname); 367 return; 368 } 369 370 /* 371 * aumac_shutdown: 372 * 373 * Make sure the interface is stopped at reboot time. 374 */ 375 static void 376 aumac_shutdown(void *arg) 377 { 378 struct aumac_softc *sc = arg; 379 380 aumac_stop(&sc->sc_ethercom.ec_if, 1); 381 382 /* 383 * XXX aumac_stop leaves device powered up at the moment 384 * XXX but this still isn't enough to keep yamon happy... :-( 385 */ 386 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 387 } 388 389 /* 390 * aumac_start: [ifnet interface function] 391 * 392 * Start packet transmission on the interface. 393 */ 394 static void 395 aumac_start(struct ifnet *ifp) 396 { 397 struct aumac_softc *sc = ifp->if_softc; 398 struct mbuf *m; 399 int nexttx; 400 401 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 402 return; 403 404 /* 405 * Loop through the send queue, setting up transmit descriptors 406 * unitl we drain the queue, or use up all available transmit 407 * descriptors. 408 */ 409 for (;;) { 410 /* Grab a packet off the queue. */ 411 IFQ_POLL(&ifp->if_snd, m); 412 if (m == NULL) 413 return; 414 415 /* Get a spare descriptor. */ 416 if (sc->sc_txfree == 0) { 417 /* No more slots left; notify upper layer. */ 418 ifp->if_flags |= IFF_OACTIVE; 419 #ifdef AUMAC_EVENT_COUNTERS 420 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 421 #endif 422 return; 423 } 424 nexttx = sc->sc_txnext; 425 426 IFQ_DEQUEUE(&ifp->if_snd, m); 427 428 /* 429 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 430 */ 431 432 m_copydata(m, 0, m->m_pkthdr.len, 433 sc->sc_txbufs[nexttx].buf_vaddr); 434 435 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 436 MACDMA_TX_STAT(nexttx), 0); 437 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 438 MACDMA_TX_LEN(nexttx), 439 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 440 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 441 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 442 MACDMA_TX_ADDR(nexttx), 443 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 444 /* XXX - needed?? we should be coherent */ 445 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 446 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 447 448 /* Advance the Tx pointer. */ 449 sc->sc_txfree--; 450 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 451 452 #if NBPFILTER > 0 453 /* Pass the packet to any BPF listeners. */ 454 if (ifp->if_bpf) 455 bpf_mtap(ifp->if_bpf, m); 456 #endif /* NBPFILTER */ 457 458 m_freem(m); 459 460 /* Set a watchdog timer in case the chip flakes out. */ 461 ifp->if_timer = 5; 462 } 463 /* NOTREACHED */ 464 } 465 466 /* 467 * aumac_watchdog: [ifnet interface function] 468 * 469 * Watchdog timer handler. 470 */ 471 static void 472 aumac_watchdog(struct ifnet *ifp) 473 { 474 struct aumac_softc *sc = ifp->if_softc; 475 476 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 477 (void) aumac_init(ifp); 478 479 /* Try to get more packets going. */ 480 aumac_start(ifp); 481 } 482 483 /* 484 * aumac_ioctl: [ifnet interface function] 485 * 486 * Handle control requests from the operator. 487 */ 488 static int 489 aumac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 490 { 491 struct aumac_softc *sc = ifp->if_softc; 492 struct ifreq *ifr = (struct ifreq *) data; 493 int s, error; 494 495 s = splnet(); 496 497 switch (cmd) { 498 case SIOCSIFMEDIA: 499 case SIOCGIFMEDIA: 500 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 501 break; 502 503 default: 504 error = ether_ioctl(ifp, cmd, data); 505 if (error == ENETRESET) { 506 /* 507 * Multicast list has changed; set the hardware filter 508 * accordingly. 509 */ 510 aumac_set_filter(sc); 511 } 512 break; 513 } 514 515 /* Try to get more packets going. */ 516 aumac_start(ifp); 517 518 splx(s); 519 return (error); 520 } 521 522 /* 523 * aumac_intr: 524 * 525 * Interrupt service routine. 526 */ 527 static int 528 aumac_intr(void *arg) 529 { 530 struct aumac_softc *sc = arg; 531 532 /* 533 * There aren't really any interrupt status bits on the 534 * Au1X00 MAC, and each MAC has a dedicated interrupt 535 * in the CPU's built-in interrupt controller. Just 536 * check for new incoming packets, and then Tx completions 537 * (for status updating). 538 */ 539 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 540 return (0); 541 542 aumac_rxintr(sc); 543 aumac_txintr(sc); 544 545 return (1); 546 } 547 548 /* 549 * aumac_txintr: 550 * 551 * Helper; handle transmit interrupts. 552 */ 553 static void 554 aumac_txintr(struct aumac_softc *sc) 555 { 556 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 557 uint32_t stat; 558 int i; 559 #ifdef AUMAC_EVENT_COUNTERS 560 int gotone = 0; 561 #endif 562 563 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 564 i = AUMAC_NEXTTX(i)) { 565 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 566 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 567 break; 568 #ifdef AUMAC_EVENT_COUNTERS 569 gotone = 1; 570 #endif 571 572 /* ACK interrupt. */ 573 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 574 MACDMA_TX_ADDR(i), 0); 575 576 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 577 MACDMA_TX_STAT(i)); 578 579 if (stat & TX_STAT_FA) { 580 /* XXX STATS */ 581 ifp->if_oerrors++; 582 } else 583 ifp->if_opackets++; 584 585 if (stat & TX_STAT_EC) 586 ifp->if_collisions += 16; 587 else 588 ifp->if_collisions += TX_STAT_CC(stat); 589 590 sc->sc_txfree++; 591 ifp->if_flags &= ~IFF_OACTIVE; 592 593 /* Try to queue more packets. */ 594 aumac_start(ifp); 595 } 596 597 #ifdef AUMAC_EVENT_COUNTERS 598 if (gotone) 599 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 600 #endif 601 602 /* Update the dirty descriptor pointer. */ 603 sc->sc_txdirty = i; 604 605 /* 606 * If there are no more pending transmissions, cancel the watchdog 607 * timer. 608 */ 609 if (sc->sc_txfree == AUMAC_NTXDESC) 610 ifp->if_timer = 0; 611 } 612 613 /* 614 * aumac_rxintr: 615 * 616 * Helper; handle receive interrupts. 617 */ 618 static void 619 aumac_rxintr(struct aumac_softc *sc) 620 { 621 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 622 struct mbuf *m; 623 uint32_t stat; 624 int i, len; 625 #ifdef AUMAC_EVENT_COUNTERS 626 int pkts = 0; 627 #endif 628 629 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 630 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 631 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 632 break; 633 #ifdef AUMAC_EVENT_COUNTERS 634 pkts++; 635 #endif 636 637 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 638 MACDMA_RX_STAT(i)); 639 640 #define PRINTERR(str) \ 641 do { \ 642 error++; \ 643 printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 644 } while (0) 645 646 if (stat & RX_STAT_ERRS) { 647 int error = 0; 648 649 if (stat & RX_STAT_MI) 650 PRINTERR("missed frame"); 651 if (stat & RX_STAT_UC) 652 PRINTERR("unknown control frame"); 653 if (stat & RX_STAT_LE) 654 PRINTERR("short frame"); 655 if (stat & RX_STAT_CR) 656 PRINTERR("CRC error"); 657 if (stat & RX_STAT_ME) 658 PRINTERR("medium error"); 659 if (stat & RX_STAT_CS) 660 PRINTERR("late collision"); 661 if (stat & RX_STAT_FL) 662 PRINTERR("frame too big"); 663 if (stat & RX_STAT_RF) 664 PRINTERR("runt frame (collision)"); 665 if (stat & RX_STAT_WT) 666 PRINTERR("watch dog"); 667 if (stat & RX_STAT_DB) { 668 if (stat & (RX_STAT_CS | RX_STAT_RF | 669 RX_STAT_CR)) { 670 if (!error) 671 goto pktok; 672 } else 673 PRINTERR("dribbling bit"); 674 } 675 #undef PRINTERR 676 ifp->if_ierrors++; 677 678 dropit: 679 /* reuse the current descriptor */ 680 AUMAC_INIT_RXDESC(sc, i); 681 continue; 682 } 683 pktok: 684 len = RX_STAT_L(stat); 685 686 /* 687 * The Au1X00 MAC includes the CRC with every packet; 688 * trim it off here. 689 */ 690 len -= ETHER_CRC_LEN; 691 692 /* 693 * Truncate the packet if it's too big to fit in 694 * a single mbuf cluster. 695 */ 696 if (len > MCLBYTES - 2) 697 len = MCLBYTES - 2; 698 699 MGETHDR(m, M_DONTWAIT, MT_DATA); 700 if (m == NULL) { 701 printf("%s: unable to allocate Rx mbuf\n", 702 sc->sc_dev.dv_xname); 703 goto dropit; 704 } 705 if (len > MHLEN - 2) { 706 MCLGET(m, M_DONTWAIT); 707 if ((m->m_flags & M_EXT) == 0) { 708 printf("%s: unable to allocate Rx cluster\n", 709 sc->sc_dev.dv_xname); 710 m_freem(m); 711 goto dropit; 712 } 713 } 714 715 m->m_data += 2; /* align payload */ 716 memcpy(mtod(m, caddr_t), 717 sc->sc_rxbufs[i].buf_vaddr, len); 718 AUMAC_INIT_RXDESC(sc, i); 719 720 m->m_pkthdr.rcvif = ifp; 721 m->m_pkthdr.len = m->m_len = len; 722 723 #if NBPFILTER > 0 724 /* Pass this up to any BPF listeners. */ 725 if (ifp->if_bpf) 726 bpf_mtap(ifp->if_bpf, m); 727 #endif /* NBPFILTER > 0 */ 728 729 /* Pass it on. */ 730 (*ifp->if_input)(ifp, m); 731 ifp->if_ipackets++; 732 } 733 #ifdef AUMAC_EVENT_COUNTERS 734 if (pkts) 735 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 736 if (pkts == AUMAC_NRXDESC) 737 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 738 #endif 739 740 /* Update the receive pointer. */ 741 sc->sc_rxptr = i; 742 } 743 744 /* 745 * aumac_tick: 746 * 747 * One second timer, used to tick the MII. 748 */ 749 static void 750 aumac_tick(void *arg) 751 { 752 struct aumac_softc *sc = arg; 753 int s; 754 755 s = splnet(); 756 mii_tick(&sc->sc_mii); 757 splx(s); 758 759 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 760 } 761 762 /* 763 * aumac_init: [ifnet interface function] 764 * 765 * Initialize the interface. Must be called at splnet(). 766 */ 767 static int 768 aumac_init(struct ifnet *ifp) 769 { 770 struct aumac_softc *sc = ifp->if_softc; 771 int i, error = 0; 772 773 /* Cancel any pending I/O, reset MAC. */ 774 aumac_stop(ifp, 0); 775 776 /* Set up the transmit ring. */ 777 for (i = 0; i < AUMAC_NTXDESC; i++) { 778 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 779 MACDMA_TX_STAT(i), 0); 780 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 781 MACDMA_TX_LEN(i), 0); 782 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 783 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 784 } 785 sc->sc_txfree = AUMAC_NTXDESC; 786 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 787 MACDMA_TX_ADDR(0))); 788 sc->sc_txdirty = sc->sc_txnext; 789 790 /* Set up the receive ring. */ 791 for (i = 0; i < AUMAC_NRXDESC; i++) 792 AUMAC_INIT_RXDESC(sc, i); 793 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 794 MACDMA_RX_ADDR(0))); 795 796 /* 797 * Power up the MAC. 798 */ 799 aumac_powerup(sc); 800 801 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 802 #if _BYTE_ORDER == _BIG_ENDIAN 803 sc->sc_control |= CONTROL_EM; 804 #endif 805 806 /* Set the media. */ 807 aumac_mediachange(ifp); 808 809 /* 810 * Set the receive filter. This will actually start the transmit 811 * and receive processes. 812 */ 813 aumac_set_filter(sc); 814 815 /* Start the one second clock. */ 816 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 817 818 /* ...all done! */ 819 ifp->if_flags |= IFF_RUNNING; 820 ifp->if_flags &= ~IFF_OACTIVE; 821 822 if (error) 823 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 824 return (error); 825 } 826 827 /* 828 * aumac_stop: [ifnet interface function] 829 * 830 * Stop transmission on the interface. 831 */ 832 static void 833 aumac_stop(struct ifnet *ifp, int disable) 834 { 835 struct aumac_softc *sc = ifp->if_softc; 836 837 /* Stop the one-second clock. */ 838 callout_stop(&sc->sc_tick_ch); 839 840 /* Down the MII. */ 841 mii_down(&sc->sc_mii); 842 843 /* Stop the transmit and receive processes. */ 844 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 845 846 /* Power down/reset the MAC. */ 847 aumac_powerdown(sc); 848 849 /* Mark the interface as down and cancel the watchdog timer. */ 850 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 851 ifp->if_timer = 0; 852 } 853 854 /* 855 * aumac_powerdown: 856 * 857 * Power down the MAC. 858 */ 859 static void 860 aumac_powerdown(struct aumac_softc *sc) 861 { 862 863 /* Disable the MAC clocks, and place the device in reset. */ 864 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 865 866 // delay(10000); 867 } 868 869 /* 870 * aumac_powerup: 871 * 872 * Bring the device out of reset. 873 */ 874 static void 875 aumac_powerup(struct aumac_softc *sc) 876 { 877 878 /* Enable clocks to the MAC. */ 879 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 880 881 /* Enable MAC, coherent transactions, pass only valid frames. */ 882 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 883 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 884 885 delay(20000); 886 } 887 888 /* 889 * aumac_set_filter: 890 * 891 * Set up the receive filter. 892 */ 893 static void 894 aumac_set_filter(struct aumac_softc *sc) 895 { 896 struct ethercom *ec = &sc->sc_ethercom; 897 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 898 struct ether_multi *enm; 899 struct ether_multistep step; 900 const uint8_t *enaddr = LLADDR(ifp->if_sadl); 901 uint32_t mchash[2], crc; 902 903 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 904 905 /* Stop the receiver. */ 906 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 907 sc->sc_control & ~CONTROL_RE); 908 909 if (ifp->if_flags & IFF_PROMISC) { 910 sc->sc_control |= CONTROL_PR; 911 goto allmulti; 912 } 913 914 /* Set the station address. */ 915 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 916 enaddr[4] | (enaddr[5] << 8)); 917 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 918 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 919 (enaddr[3] << 24)); 920 921 sc->sc_control |= CONTROL_HP; 922 923 mchash[0] = mchash[1] = 0; 924 925 /* 926 * Set up the multicast address filter by passing all multicast 927 * addresses through a CRC generator, and then using the high 928 * order 6 bits as an index into the 64-bit multicast hash table. 929 * The high order bits select the word, while the rest of the bits 930 * select the bit within the word. 931 */ 932 ETHER_FIRST_MULTI(step, ec, enm); 933 while (enm != NULL) { 934 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 935 /* 936 * We must listen to a range of multicast addresses. 937 * For now, just accept all multicasts, rather than 938 * trying to set only those filter bits needed to match 939 * the range. (At this time, the only use of address 940 * ranges is for IP multicast routing, for which the 941 * range is large enough to require all bits set.) 942 */ 943 goto allmulti; 944 } 945 946 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 947 948 /* Just want the 6 most significant bits. */ 949 crc >>= 26; 950 951 /* Set the corresponding bit in the filter. */ 952 mchash[crc >> 5] |= 1U << (crc & 0x1f); 953 954 ETHER_NEXT_MULTI(step, enm); 955 } 956 957 ifp->if_flags &= ~IFF_ALLMULTI; 958 959 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 960 mchash[1]); 961 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 962 mchash[0]); 963 964 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 965 sc->sc_control); 966 return; 967 968 allmulti: 969 sc->sc_control |= CONTROL_PM; 970 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 971 sc->sc_control); 972 } 973 974 /* 975 * aumac_mediastatus: [ifmedia interface function] 976 * 977 * Get the current interface media status. 978 */ 979 static void 980 aumac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 981 { 982 struct aumac_softc *sc = ifp->if_softc; 983 984 mii_pollstat(&sc->sc_mii); 985 ifmr->ifm_status = sc->sc_mii.mii_media_status; 986 ifmr->ifm_active = sc->sc_mii.mii_media_active; 987 } 988 989 /* 990 * aumac_mediachange: [ifmedia interface function] 991 * 992 * Set hardware to newly selected media. 993 */ 994 static int 995 aumac_mediachange(struct ifnet *ifp) 996 { 997 struct aumac_softc *sc = ifp->if_softc; 998 999 if (ifp->if_flags & IFF_UP) 1000 mii_mediachg(&sc->sc_mii); 1001 return (0); 1002 } 1003 1004 /* 1005 * aumac_mii_wait: 1006 * 1007 * Wait for the MII interface to not be busy. 1008 */ 1009 static int 1010 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 1011 { 1012 int i; 1013 1014 for (i = 0; i < 10000; i++) { 1015 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 1016 MAC_MIICTRL) & MIICTRL_MB) == 0) 1017 return (0); 1018 delay(10); 1019 } 1020 1021 printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 1022 return (1); 1023 } 1024 1025 /* 1026 * aumac_mii_readreg: [mii interface function] 1027 * 1028 * Read a PHY register on the MII. 1029 */ 1030 static int 1031 aumac_mii_readreg(struct device *self, int phy, int reg) 1032 { 1033 struct aumac_softc *sc = (void *) self; 1034 1035 if (aumac_mii_wait(sc, "become ready")) 1036 return (0); 1037 1038 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1039 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1040 1041 if (aumac_mii_wait(sc, "complete")) 1042 return (0); 1043 1044 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1045 MIIDATA_MASK); 1046 } 1047 1048 /* 1049 * aumac_mii_writereg: [mii interface function] 1050 * 1051 * Write a PHY register on the MII. 1052 */ 1053 static void 1054 aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1055 { 1056 struct aumac_softc *sc = (void *) self; 1057 1058 if (aumac_mii_wait(sc, "become ready")) 1059 return; 1060 1061 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1062 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1063 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1064 1065 (void) aumac_mii_wait(sc, "complete"); 1066 } 1067 1068 /* 1069 * aumac_mii_statchg: [mii interface function] 1070 * 1071 * Callback from MII layer when media changes. 1072 */ 1073 static void 1074 aumac_mii_statchg(struct device *self) 1075 { 1076 struct aumac_softc *sc = (void *) self; 1077 1078 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1079 sc->sc_control |= CONTROL_F; 1080 else 1081 sc->sc_control &= ~CONTROL_F; 1082 1083 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1084 sc->sc_control); 1085 } 1086