1*ca42af5eSsimonb /* $NetBSD: if_aumacreg.h,v 1.1 2002/07/29 15:39:14 simonb Exp $ */ 2*ca42af5eSsimonb 3*ca42af5eSsimonb /* 4*ca42af5eSsimonb * Copyright (c) 2001 Wasabi Systems, Inc. 5*ca42af5eSsimonb * All rights reserved. 6*ca42af5eSsimonb * 7*ca42af5eSsimonb * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8*ca42af5eSsimonb * 9*ca42af5eSsimonb * Redistribution and use in source and binary forms, with or without 10*ca42af5eSsimonb * modification, are permitted provided that the following conditions 11*ca42af5eSsimonb * are met: 12*ca42af5eSsimonb * 1. Redistributions of source code must retain the above copyright 13*ca42af5eSsimonb * notice, this list of conditions and the following disclaimer. 14*ca42af5eSsimonb * 2. Redistributions in binary form must reproduce the above copyright 15*ca42af5eSsimonb * notice, this list of conditions and the following disclaimer in the 16*ca42af5eSsimonb * documentation and/or other materials provided with the distribution. 17*ca42af5eSsimonb * 3. All advertising materials mentioning features or use of this software 18*ca42af5eSsimonb * must display the following acknowledgement: 19*ca42af5eSsimonb * This product includes software developed for the NetBSD Project by 20*ca42af5eSsimonb * Wasabi Systems, Inc. 21*ca42af5eSsimonb * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22*ca42af5eSsimonb * or promote products derived from this software without specific prior 23*ca42af5eSsimonb * written permission. 24*ca42af5eSsimonb * 25*ca42af5eSsimonb * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26*ca42af5eSsimonb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27*ca42af5eSsimonb * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28*ca42af5eSsimonb * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29*ca42af5eSsimonb * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30*ca42af5eSsimonb * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31*ca42af5eSsimonb * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32*ca42af5eSsimonb * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33*ca42af5eSsimonb * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34*ca42af5eSsimonb * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35*ca42af5eSsimonb * POSSIBILITY OF SUCH DAMAGE. 36*ca42af5eSsimonb */ 37*ca42af5eSsimonb 38*ca42af5eSsimonb #ifndef _MIPS_ALCHEMY_DEV_AUMACREG_H_ 39*ca42af5eSsimonb #define _MIPS_ALCHEMY_DEV_AUMACREG_H_ 40*ca42af5eSsimonb 41*ca42af5eSsimonb /* 42*ca42af5eSsimonb * Register description for the Alchemy Semiconductor Au1X00 43*ca42af5eSsimonb * Ethernet Media Access Controllers. 44*ca42af5eSsimonb */ 45*ca42af5eSsimonb 46*ca42af5eSsimonb #define MAC_BUFLEN 0x0800 47*ca42af5eSsimonb #define MAC_BUFLEN_JUMBO 0x2800 48*ca42af5eSsimonb 49*ca42af5eSsimonb /* 50*ca42af5eSsimonb * MAC registers. 51*ca42af5eSsimonb */ 52*ca42af5eSsimonb 53*ca42af5eSsimonb #define MAC_CONTROL 0x0000 /* MAC control */ 54*ca42af5eSsimonb #define CONTROL_RA (1U << 31) /* receive all */ 55*ca42af5eSsimonb #define CONTROL_EM (1U << 30) /* 1 = big endian */ 56*ca42af5eSsimonb #define CONTROL_DO (1U << 23) /* disable receive own */ 57*ca42af5eSsimonb #define CONTROL_LM(x) ((x) << 21) /* loopback mode */ 58*ca42af5eSsimonb /* 0 = normal */ 59*ca42af5eSsimonb /* 1 = internal loopback */ 60*ca42af5eSsimonb /* 2 = external loopback */ 61*ca42af5eSsimonb /* 3 = reserved */ 62*ca42af5eSsimonb #define CONTROL_F (1U << 20) /* full-duplex mode */ 63*ca42af5eSsimonb #define CONTROL_PM (1U << 19) /* pass all multicast */ 64*ca42af5eSsimonb #define CONTROL_PR (1U << 18) /* promiscuous mode */ 65*ca42af5eSsimonb #define CONTROL_IF (1U << 17) /* inverse filtering */ 66*ca42af5eSsimonb #define CONTROL_PB (1U << 16) /* pass bad frames */ 67*ca42af5eSsimonb #define CONTROL_HO (1U << 15) /* hash-only filtering */ 68*ca42af5eSsimonb #define CONTROL_HP (1U << 13) /* hash-perfect filtering */ 69*ca42af5eSsimonb #define CONTROL_LC (1U << 12) /* re-tx on late collision */ 70*ca42af5eSsimonb #define CONTROL_DB (1U << 11) /* disable broadcast frames */ 71*ca42af5eSsimonb #define CONTROL_DR (1U << 10) /* disable retry */ 72*ca42af5eSsimonb #define CONTROL_AP (1U << 8) /* automatic pad stripping */ 73*ca42af5eSsimonb #define CONTROL_BL(x) ((x) << 6) /* backoff limit */ 74*ca42af5eSsimonb #define CONTROL_DC (1U << 5) /* deferral check */ 75*ca42af5eSsimonb #define CONTROL_TE (1U << 3) /* transmitter enable */ 76*ca42af5eSsimonb #define CONTROL_RE (1U << 2) /* receiver enable */ 77*ca42af5eSsimonb 78*ca42af5eSsimonb #define MAC_ADDRHIGH 0x0004 /* high 16 bits of station address */ 79*ca42af5eSsimonb 80*ca42af5eSsimonb #define MAC_ADDRLOW 0x0008 /* low 32 bits of station address */ 81*ca42af5eSsimonb 82*ca42af5eSsimonb #define MAC_HASHHIGH 0x000c /* high 32 bits of multicast hash */ 83*ca42af5eSsimonb 84*ca42af5eSsimonb #define MAC_HASHLOW 0x0010 /* low 32 bits of multicast hash */ 85*ca42af5eSsimonb 86*ca42af5eSsimonb #define MAC_MIICTRL 0x0014 /* MII PHY control */ 87*ca42af5eSsimonb #define MIICTRL_PHYADDR(x) ((x) << 11) /* PHY address */ 88*ca42af5eSsimonb #define MIICTRL_MIIREG(x) ((x) << 6) /* MII register */ 89*ca42af5eSsimonb #define MIICTRL_MW (1U << 1) /* MII write */ 90*ca42af5eSsimonb #define MIICTRL_MB (1U << 0) /* MII busy */ 91*ca42af5eSsimonb 92*ca42af5eSsimonb #define MAC_MIIDATA 0x0018 /* MII PHY data */ 93*ca42af5eSsimonb #define MIIDATA_MASK 0xffff /* MII data bits */ 94*ca42af5eSsimonb 95*ca42af5eSsimonb #define MAC_FLOWCTRL 0x001c /* control frame generation control */ 96*ca42af5eSsimonb #define FLOWCTRL_PT(x) ((x) << 16) /* pause time */ 97*ca42af5eSsimonb #define FLOWCTRL_PC (1U << 2) /* pass control frame */ 98*ca42af5eSsimonb #define FLOWCTRL_FE (1U << 1) /* flow control enable */ 99*ca42af5eSsimonb #define FLOWCTRL_FB (1U << 0) /* flow control busy */ 100*ca42af5eSsimonb 101*ca42af5eSsimonb #define MAC_VLAN1 0x0020 /* VLAN1 tag */ 102*ca42af5eSsimonb 103*ca42af5eSsimonb #define MAC_VLAN2 0x0024 /* VLAN2 tag */ 104*ca42af5eSsimonb 105*ca42af5eSsimonb /* 106*ca42af5eSsimonb * MAC Enable registers. 107*ca42af5eSsimonb */ 108*ca42af5eSsimonb 109*ca42af5eSsimonb #define MACEN_JP (1U << 6) /* jumbo packet enable */ 110*ca42af5eSsimonb #define MACEN_E2 (1U << 5) /* enable2 */ 111*ca42af5eSsimonb #define MACEN_E1 (1U << 4) /* enable1 */ 112*ca42af5eSsimonb #define MACEN_C (1U << 3) /* 0 == coherent */ 113*ca42af5eSsimonb #define MACEN_TS (1U << 2) /* disable toss */ 114*ca42af5eSsimonb #define MACEN_E0 (1U << 1) /* enable0 */ 115*ca42af5eSsimonb #define MACEN_CE (1U << 0) /* clock enable */ 116*ca42af5eSsimonb 117*ca42af5eSsimonb /* 118*ca42af5eSsimonb * MAC DMA registers. 119*ca42af5eSsimonb */ 120*ca42af5eSsimonb 121*ca42af5eSsimonb #define MACDMA_TX_ENTRY(x) ((x) << 4) 122*ca42af5eSsimonb #define MACDMA_RX_ENTRY(x) (((x) << 4) + 0x100) 123*ca42af5eSsimonb 124*ca42af5eSsimonb #define MACDMA_TX_STAT(x) (MACDMA_TX_ENTRY(x) + 0x00) 125*ca42af5eSsimonb #define MACDMA_TX_ADDR(x) (MACDMA_TX_ENTRY(x) + 0x04) 126*ca42af5eSsimonb #define MACDMA_TX_LEN(x) (MACDMA_TX_ENTRY(x) + 0x08) 127*ca42af5eSsimonb 128*ca42af5eSsimonb #define MACDMA_RX_STAT(x) (MACDMA_RX_ENTRY(x) + 0x00) 129*ca42af5eSsimonb #define MACDMA_RX_ADDR(x) (MACDMA_RX_ENTRY(x) + 0x04) 130*ca42af5eSsimonb 131*ca42af5eSsimonb #define RX_STAT_MI (1U << 31) /* missed frame */ 132*ca42af5eSsimonb #define RX_STAT_PF (1U << 30) /* packet filter pass */ 133*ca42af5eSsimonb #define RX_STAT_FF (1U << 29) /* filtering fail */ 134*ca42af5eSsimonb #define RX_STAT_BF (1U << 28) /* broadcast frame */ 135*ca42af5eSsimonb #define RX_STAT_MF (1U << 27) /* multicast frame */ 136*ca42af5eSsimonb #define RX_STAT_UC (1U << 26) /* unsupported control frame */ 137*ca42af5eSsimonb #define RX_STAT_CF (1U << 25) /* control frame */ 138*ca42af5eSsimonb #define RX_STAT_LE (1U << 24) /* length error */ 139*ca42af5eSsimonb #define RX_STAT_V2 (1U << 23) /* VLAN2 match */ 140*ca42af5eSsimonb #define RX_STAT_V1 (1U << 22) /* VLAN1 match */ 141*ca42af5eSsimonb #define RX_STAT_CR (1U << 21) /* CRC error */ 142*ca42af5eSsimonb #define RX_STAT_DB (1U << 20) /* dribbling bit */ 143*ca42af5eSsimonb #define RX_STAT_ME (1U << 19) /* MII error */ 144*ca42af5eSsimonb #define RX_STAT_FT (1U << 18) /* 0 = 802.3, 1 = Ethernet */ 145*ca42af5eSsimonb #define RX_STAT_CS (1U << 17) /* collision seen */ 146*ca42af5eSsimonb #define RX_STAT_FL (1U << 16) /* frame too long */ 147*ca42af5eSsimonb #define RX_STAT_RF (1U << 15) /* runt frame */ 148*ca42af5eSsimonb #define RX_STAT_WT (1U << 14) /* watchdog timeout */ 149*ca42af5eSsimonb #define RX_STAT_L(x) ((x) & 0x3fff) /* frame length */ 150*ca42af5eSsimonb 151*ca42af5eSsimonb #define RX_STAT_ERRS (RX_STAT_MI | RX_STAT_UC | RX_STAT_LE | RX_STAT_CR | \ 152*ca42af5eSsimonb RX_STAT_DB | RX_STAT_ME | RX_STAT_CS | RX_STAT_FL | \ 153*ca42af5eSsimonb RX_STAT_RF | RX_STAT_WT) 154*ca42af5eSsimonb 155*ca42af5eSsimonb #define RX_ADDR_CB(x) (((x) >> 2) & 3)/* current buffer */ 156*ca42af5eSsimonb #define RX_ADDR_DN (1U << 1) /* transaction done */ 157*ca42af5eSsimonb #define RX_ADDR_EN (1U << 0) /* enable this buffer */ 158*ca42af5eSsimonb 159*ca42af5eSsimonb #define TX_STAT_PR (1U << 31) /* packet retry */ 160*ca42af5eSsimonb #define TX_STAT_CC(x) (((x) >> 10) & 0xf) /* collision count */ 161*ca42af5eSsimonb #define TX_STAT_LO (1U << 9) /* late collision observed */ 162*ca42af5eSsimonb #define TX_STAT_DF (1U << 8) /* deferred transmission */ 163*ca42af5eSsimonb #define TX_STAT_UR (1U << 7) /* data underrun */ 164*ca42af5eSsimonb #define TX_STAT_EC (1U << 6) /* excessive collisions */ 165*ca42af5eSsimonb #define TX_STAT_LC (1U << 5) /* late collision */ 166*ca42af5eSsimonb #define TX_STAT_ED (1U << 4) /* excessive deferral */ 167*ca42af5eSsimonb #define TX_STAT_LS (1U << 3) /* loss of carrier */ 168*ca42af5eSsimonb #define TX_STAT_NC (1U << 2) /* no carrier */ 169*ca42af5eSsimonb #define TX_STAT_JT (1U << 1) /* jabber timeout */ 170*ca42af5eSsimonb #define TX_STAT_FA (1U << 0) /* frame aborted */ 171*ca42af5eSsimonb 172*ca42af5eSsimonb #define TX_ADDR_CB(x) (((x) >> 2) & 3)/* current buffer */ 173*ca42af5eSsimonb #define TX_ADDR_DN (1U << 1) /* transaction done */ 174*ca42af5eSsimonb #define TX_ADDR_EN (1U << 0) /* enable this buffer */ 175*ca42af5eSsimonb 176*ca42af5eSsimonb #endif /* _MIPS_ALCHEMY_DEV_AUMACREG_H_ */ 177