1 /* $NetBSD: lock.h,v 1.4 2002/12/05 02:56:51 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Wayne Knowles. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Machine-dependent spin lock operations for MIPS R4000 Processors. 41 * 42 * Note: R3000 doesn't have any atomic update instructions 43 */ 44 45 #ifndef _MIPS_LOCK_H_ 46 #define _MIPS_LOCK_H_ 47 48 typedef __volatile int __cpu_simple_lock_t; 49 50 #define __SIMPLELOCK_LOCKED 1 51 #define __SIMPLELOCK_UNLOCKED 0 52 53 static __inline void 54 __cpu_simple_lock_init(__cpu_simple_lock_t *lp) 55 { 56 57 __asm __volatile( 58 "# -- BEGIN __cpu_simple_lock_init\n" 59 " .set push \n" 60 " .set mips2 \n" 61 " sw $0, %0 \n" 62 " sync \n" 63 " .set pop \n" 64 "# -- END __cpu_simple_lock_init\n" 65 : "=m" (*lp)); 66 } 67 68 static __inline void 69 __cpu_simple_lock(__cpu_simple_lock_t *lp) 70 { 71 unsigned long t0; 72 73 /* 74 * Note, if we detect that the lock is held when 75 * we do the initial load-locked, we spin using 76 * a non-locked load to save the coherency logic 77 * some work. 78 */ 79 80 __asm __volatile( 81 "# -- BEGIN __cpu_simple_lock \n" 82 " .set push \n" 83 " .set mips2 \n" 84 "1: ll %0, %3 \n" 85 " bnez %0, 2f \n" 86 " nop # BDslot \n" 87 " li %0, %2 \n" 88 " sc %0, %1 \n" 89 " beqz %0, 1b \n" 90 " nop # BDslot \n" 91 " nop \n" 92 " sync \n" 93 " j 3f \n" 94 " nop \n" 95 " nop \n" 96 "2: lw %0, %3 \n" 97 " bnez %0, 2b \n" 98 " nop # BDslot \n" 99 " j 1b \n" 100 " nop \n" 101 "3: \n" 102 " .set pop \n" 103 "# -- END __cpu_simple_lock \n" 104 : "=r" (t0), "+m" (*lp) 105 : "i" (__SIMPLELOCK_LOCKED), "1" (*lp)); 106 } 107 108 static __inline int 109 __cpu_simple_lock_try(__cpu_simple_lock_t *lp) 110 { 111 unsigned long t0, v0; 112 113 __asm __volatile( 114 "# -- BEGIN __cpu_simple_lock_try\n" 115 " .set push \n" 116 " .set mips2 \n" 117 "1: ll %0, %4 \n" 118 " bnez %0, 2f \n" 119 " nop # BDslot \n" 120 " li %0, %3 \n" 121 " sc %0, %2 \n" 122 " beqz %0, 2f \n" 123 " nop # BDslot \n" 124 " li %1, 1 \n" 125 " sync \n" 126 " j 3f \n" 127 " nop \n" 128 " nop \n" 129 "2: li %1, 0 \n" 130 "3: \n" 131 " .set pop \n" 132 "# -- END __cpu_simple_lock_try \n" 133 : "=r" (t0), "=r" (v0), "+m" (*lp) 134 : "i" (__SIMPLELOCK_LOCKED), "2" (*lp)); 135 136 return (v0 != 0); 137 } 138 139 static __inline void 140 __cpu_simple_unlock(__cpu_simple_lock_t *lp) 141 { 142 143 __asm __volatile( 144 "# -- BEGIN __cpu_simple_unlock \n" 145 " .set push \n" 146 " .set mips2 \n" 147 " sync \n" 148 " sw $0, %0 \n" 149 " .set pop \n" 150 "# -- END __cpu_simple_unlock \n" 151 : "=m" (*lp)); 152 } 153 #endif /* _MIPS_LOCK_H_ */ 154