xref: /netbsd/sys/arch/mips/include/mips1_pte.h (revision bf9ec67e)
1 /*	$NetBSD: mips1_pte.h,v 1.13 2000/06/09 05:51:42 soda Exp $	*/
2 
3 /*
4  * Copyright (c) 1988 University of Utah.
5  * Copyright (c) 1992, 1993
6  *	The Regents of the University of California.  All rights reserved.
7  *
8  * This code is derived from software contributed to Berkeley by
9  * the Systems Programming Group of the University of Utah Computer
10  * Science Department and Ralph Campbell.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  *    must display the following acknowledgement:
22  *	This product includes software developed by the University of
23  *	California, Berkeley and its contributors.
24  * 4. Neither the name of the University nor the names of its contributors
25  *    may be used to endorse or promote products derived from this software
26  *    without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  * from: Utah Hdr: pte.h 1.11 89/09/03
41  *
42  *	@(#)pte.h	8.1 (Berkeley) 6/10/93
43  */
44 
45 /*
46  * R2000 hardware page table entry
47  */
48 
49 #ifndef _LOCORE
50 struct mips1_pte {
51 #if BYTE_ORDER == BIG_ENDIAN
52 unsigned int	pg_pfnum:20,		/* HW: core page frame number or 0 */
53 		pg_n:1,			/* HW: non-cacheable bit */
54 		pg_m:1,			/* HW: dirty bit */
55 		pg_v:1,			/* HW: valid bit */
56 		pg_g:1,			/* HW: ignore pid bit */
57 		:4,
58 		pg_swapm:1,		/* SW: page must be forced to swap */
59 		pg_fod:1,		/* SW: is fill on demand (=0) */
60 		pg_prot:2;		/* SW: access control */
61 #endif
62 #if BYTE_ORDER == LITTLE_ENDIAN
63 unsigned int	pg_prot:2,		/* SW: access control */
64 		pg_fod:1,		/* SW: is fill on demand (=0) */
65 		pg_swapm:1,		/* SW: page must be forced to swap */
66 		:4,
67 		pg_g:1,			/* HW: ignore pid bit */
68 		pg_v:1,			/* HW: valid bit */
69 		pg_m:1,			/* HW: dirty bit */
70 		pg_n:1,			/* HW: non-cacheable bit */
71 		pg_pfnum:20;		/* HW: core page frame number or 0 */
72 #endif
73 };
74 #endif /* _LOCORE */
75 
76 #define	MIPS1_PG_PROT	0x00000003
77 #define MIPS1_PG_RW	0x00000000
78 #define MIPS1_PG_RO	0x00000001
79 #define MIPS1_PG_WIRED	0x00000002
80 #define	MIPS1_PG_G	0x00000100
81 #define	MIPS1_PG_V	0x00000200
82 #define	MIPS1_PG_NV	0x00000000
83 #define	MIPS1_PG_D	0x00000400
84 #define	MIPS1_PG_N	0x00000800
85 #define	MIPS1_PG_FRAME	0xfffff000
86 #define MIPS1_PG_SHIFT	12
87 #define	MIPS1_PG_PFNUM(x) (((x) & MIPS1_PG_FRAME) >> MIPS1_PG_SHIFT)
88 
89 #define	MIPS1_PG_ROPAGE	MIPS1_PG_V
90 #define	MIPS1_PG_RWPAGE	MIPS1_PG_D
91 #define	MIPS1_PG_CWPAGE	0
92 #define	MIPS1_PG_IOPAGE	(MIPS1_PG_D | MIPS1_PG_N)
93 
94 #define	mips1_tlbpfn_to_paddr(x)	((x) & MIPS1_PG_FRAME)
95 #define	mips1_paddr_to_tlbpfn(x)	(x)
96 
97 #define	MIPS1_PTE_TO_PADDR(pte) ((unsigned)(pte) & MIPS1_PG_FRAME)
98 #define MIPS1_PAGE_IS_RDONLY(pte,va) ((int)(pte) & MIPS1_PG_RO)
99