1 /* $NetBSD: mipsNN.h,v 1.1 2002/03/05 16:07:10 simonb Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. Neither the "Broadcom Corporation" name nor any 19 * trademark or logo of Broadcom Corporation may be used to endorse or 20 * promote products derived from this software without the prior written 21 * permission of Broadcom Corporation. 22 * 23 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 26 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 27 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 28 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Values related to the MIPS32/MIPS64 Privileged Resource Architecture. 38 */ 39 40 #define _MIPSNN_SHIFT(reg) __MIPSNN_SHIFT(reg) 41 #define __MIPSNN_SHIFT(reg) MIPSNN_ ## reg ## _SHIFT 42 #define _MIPSNN_MASK(reg) __MIPSNN_MASK(reg) 43 #define __MIPSNN_MASK(reg) MIPSNN_ ## reg ## _MASK 44 45 #define MIPSNN_GET(reg, x) \ 46 ((unsigned)((x) & _MIPSNN_MASK(reg)) >> _MIPSNN_SHIFT(reg)) 47 #define MIPSNN_PUT(reg, val) \ 48 (((x) << _MIPSNN_SHIFT(reg)) & _MIPSNN_MASK(reg)) 49 50 /* 51 * Values in Configuration Register (CP0 Register 16, Select 0) 52 */ 53 54 /* "M" (R): Configuration Register 1 present if set. Defined as always set. */ 55 #define MIPSNN_CFG_M 0x80000000 56 57 /* Reserved for CPU implementations. */ 58 // reserved 0x7fff0000 59 60 /* "BE" (R): Big endian if set, little endian if clear. */ 61 #define MIPSNN_CFG_BE 0x00008000 62 63 /* "AT" (R): architecture type implemented by processor */ 64 #define MIPSNN_CFG_AT_MASK 0x00006000 65 #define MIPSNN_CFG_AT_SHIFT 13 66 67 #define MIPSNN_CFG_AT_MIPS32 0 /* MIPS32 */ 68 #define MIPSNN_CFG_AT_MIPS64S 1 /* MIPS64S */ 69 #define MIPSNN_CFG_AT_MIPS64 2 /* MIPS64 */ 70 // reserved 3 71 72 /* "AR" (R): Architecture revision level implemented by proc. */ 73 #define MIPSNN_CFG_AR_MASK 0x00001c00 74 #define MIPSNN_CFG_AR_SHIFT 10 75 76 #define MIPSNN_CFG_AR_REV1 0 /* Revision 1 */ 77 // reserved other values 78 79 /* "MT" (R): MMU type implemented by processor */ 80 #define MIPSNN_CFG_MT_MASK 0x00000380 81 #define MIPSNN_CFG_MT_SHIFT 7 82 83 #define MIPSNN_CFG_MT_NONE 0 /* No MMU */ 84 #define MIPSNN_CFG_MT_TLB 1 /* Std TLB */ 85 #define MIPSNN_CFG_MT_BAT 2 /* Std BAT */ 86 #define MIPSNN_CFG_MT_FIXED 3 /* Std Fixed mapping */ 87 // reserved other values 88 89 /* Reserved. Write as 0, reads as 0. */ 90 // reserved 0x00000078 91 92 /* "K0" (RW): Kseg0 coherency algorithm. (values are TLB_ATTRs) */ 93 #define MIPSNN_CFG_K0_MASK 0x00000007 94 #define MIPSNN_CFG_K0_SHIFT 0 95 96 97 /* 98 * Values in Configuration Register 1 (CP0 Register 16, Select 1) 99 */ 100 101 /* Reserved for Configuration Register 2 present. Write as 0, reads as 0. */ 102 // reserved 0x80000000 103 104 /* MS (R): Number of TLB entries - 1. */ 105 #define MIPSNN_CFG1_MS_MASK 0x7e000000 106 #define MIPSNN_CFG1_MS_SHIFT 25 107 108 #define MIPSNN_CFG1_MS(x) (MIPSNN_GET(CFG1_MS, (x)) + 1) 109 110 /* "IS" (R): (Primary) I-cache sets per way. */ 111 #define MIPSNN_CFG1_IS_MASK 0x01c00000 112 #define MIPSNN_CFG1_IS_SHIFT 22 113 114 #define MIPSNN_CFG1_IS_RSVD 7 /* rsvd value, otherwise: */ 115 #define MIPSNN_CFG1_IS(x) (64 << MIPSNN_GET(CFG1_IS, (x))) 116 117 /* "IL" (R): (Primary) I-cache line size. */ 118 #define MIPSNN_CFG1_IL_MASK 0x00380000 119 #define MIPSNN_CFG1_IL_SHIFT 19 120 121 #define MIPSNN_CFG1_IL_NONE 0 /* No I-cache, */ 122 #define MIPSNN_CFG1_IL_RSVD 7 /* rsvd value, otherwise: */ 123 #define MIPSNN_CFG1_IL(x) (2 << MIPSNN_GET(CFG1_IL, (x))) 124 125 /* "IA" (R): (Primary) I-cache associativity (ways - 1). */ 126 #define MIPSNN_CFG1_IA_MASK 0x00070000 127 #define MIPSNN_CFG1_IA_SHIFT 16 128 129 #define MIPSNN_CFG1_IA(x) MIPSNN_GET(CFG1_IA, (x)) 130 131 /* "DS" (R): (Primary) D-cache sets per way. */ 132 #define MIPSNN_CFG1_DS_MASK 0x0000e000 133 #define MIPSNN_CFG1_DS_SHIFT 13 134 135 #define MIPSNN_CFG1_DS_RSVD 7 /* rsvd value, otherwise: */ 136 #define MIPSNN_CFG1_DS(x) (64 << MIPSNN_GET(CFG1_DS, (x))) 137 138 /* "DL" (R): (Primary) D-cache line size. */ 139 #define MIPSNN_CFG1_DL_MASK 0x00001c00 140 #define MIPSNN_CFG1_DL_SHIFT 10 141 142 #define MIPSNN_CFG1_DL_NONE 0 /* No D-cache, */ 143 #define MIPSNN_CFG1_DL_RSVD 7 /* rsvd value, otherwise: */ 144 #define MIPSNN_CFG1_DL(x) (2 << MIPSNN_GET(CFG1_DL, (x))) 145 146 /* "DA" (R): (Primary) D-cache associativity (ways - 1). */ 147 #define MIPSNN_CFG1_DA_MASK 0x00000380 148 #define MIPSNN_CFG1_DA_SHIFT 7 149 150 #define MIPSNN_CFG1_DA(x) MIPSNN_GET(CFG1_DA, (x)) 151 152 /* Reserved. Write as 0, reads as 0. */ 153 // reserved 0x00000060 154 155 /* "PC" (R): Performance Counters implemented if set. */ 156 #define MIPSNN_CFG1_PC 0x00000010 157 158 /* "WR" (R): Watch registers implemented if set. */ 159 #define MIPSNN_CFG1_WR 0x00000008 160 161 /* "CA" (R): Code compressiong (MIPS16) implemented if set. */ 162 #define MIPSNN_CFG1_CA 0x00000004 163 164 /* "EP" (R): EJTAG implemented if set. */ 165 #define MIPSNN_CFG1_EP 0x00000002 166 167 /* "FP" (R): FPU implemented if set. */ 168 #define MIPSNN_CFG1_FP 0x00000001 169