1 /* $NetBSD: pte.h,v 1.12 2002/03/05 15:39:31 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright 1996 The Board of Trustees of The Leland Stanford 42 * Junior University. All Rights Reserved. 43 * 44 * Permission to use, copy, modify, and distribute this 45 * software and its documentation for any purpose and without 46 * fee is hereby granted, provided that the above copyright 47 * notice appear in all copies. Stanford University 48 * makes no representations about the suitability of this 49 * software for any purpose. It is provided "as is" without 50 * express or implied warranty. 51 */ 52 53 #ifndef __MIPS_PTE_H__ 54 #define __MIPS_PTE_H__ 55 56 #include <mips/mips1_pte.h> 57 #include <mips/mips3_pte.h> 58 59 #define PG_ASID 0x000000ff /* Address space ID */ 60 61 #ifndef _LOCORE 62 #include <mips/cpu.h> 63 64 typedef union pt_entry { 65 unsigned int pt_entry; /* for copying, etc. */ 66 struct mips1_pte pt_mips1_pte; /* for getting to bits by name */ 67 struct mips3_pte pt_mips3_pte; 68 } pt_entry_t; 69 70 #define PT_ENTRY_NULL ((pt_entry_t *) 0) 71 72 /* 73 * Macros/inline functions to hide PTE format differences. 74 */ 75 76 #define mips_pg_nv_bit() (MIPS1_PG_NV) /* same on mips1 and mips3 */ 77 78 79 int pmap_is_page_ro(pmap_t, vaddr_t, int); 80 81 82 /* MIPS1-only */ 83 #if defined(MIPS1) && !defined(MIPS3_PLUS) 84 #define mips_pg_v(entry) ((entry) & MIPS1_PG_V) 85 #define mips_pg_wired(entry) ((entry) & MIPS1_PG_WIRED) 86 87 #define mips_pg_m_bit() (MIPS1_PG_D) 88 #define mips_pg_rw_bit() (MIPS1_PG_RW) /* no RW bits for mips1 */ 89 #define mips_pg_ro_bit() (MIPS1_PG_RO) 90 #define mips_pg_ropage_bit() (MIPS1_PG_RO) /* XXX not MIPS1_PG_ROPAGE? */ 91 #define mips_pg_rwpage_bit() (MIPS1_PG_RWPAGE) 92 #define mips_pg_cwpage_bit() (MIPS1_PG_CWPAGE) 93 #define mips_pg_global_bit() (MIPS1_PG_G) 94 #define mips_pg_wired_bit() (MIPS1_PG_WIRED) 95 96 #define PTE_TO_PADDR(pte) MIPS1_PTE_TO_PADDR((pte)) 97 #define PAGE_IS_RDONLY(pte, va) MIPS1_PAGE_IS_RDONLY((pte), (va)) 98 99 #define mips_tlbpfn_to_paddr(x) mips1_tlbpfn_to_paddr((vaddr_t)(x)) 100 #define mips_paddr_to_tlbpfn(x) mips1_paddr_to_tlbpfn((x)) 101 #endif /* mips1 */ 102 103 104 /* MIPS3 (or greater) only */ 105 #if !defined(MIPS1) && defined(MIPS3_PLUS) 106 #define mips_pg_v(entry) ((entry) & MIPS3_PG_V) 107 #define mips_pg_wired(entry) ((entry) & MIPS3_PG_WIRED) 108 109 #define mips_pg_m_bit() (MIPS3_PG_D) 110 #define mips_pg_rw_bit() (MIPS3_PG_D) 111 #define mips_pg_ro_bit() (MIPS3_PG_RO) 112 #define mips_pg_ropage_bit() (MIPS3_PG_ROPAGE) 113 #define mips_pg_rwpage_bit() (MIPS3_PG_RWPAGE) 114 #define mips_pg_cwpage_bit() (MIPS3_PG_CWPAGE) 115 #define mips_pg_global_bit() (MIPS3_PG_G) 116 #define mips_pg_wired_bit() (MIPS3_PG_WIRED) 117 118 #define PTE_TO_PADDR(pte) MIPS3_PTE_TO_PADDR((pte)) 119 #define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va)) 120 121 #define mips_tlbpfn_to_paddr(x) mips3_tlbpfn_to_paddr((vaddr_t)(x)) 122 #define mips_paddr_to_tlbpfn(x) mips3_paddr_to_tlbpfn((x)) 123 #endif /* mips3 */ 124 125 /* MIPS1 and MIPS3 (or greater) */ 126 #if defined(MIPS1) && defined(MIPS3_PLUS) 127 128 static __inline int 129 mips_pg_v(unsigned int entry), 130 mips_pg_wired(unsigned int entry), 131 PAGE_IS_RDONLY(unsigned int pte, vaddr_t va); 132 133 static __inline unsigned int 134 mips_pg_wired_bit(void), mips_pg_m_bit(void), 135 mips_pg_ro_bit(void), mips_pg_rw_bit(void), 136 mips_pg_ropage_bit(void), 137 mips_pg_cwpage_bit(void), 138 mips_pg_rwpage_bit(void), 139 mips_pg_global_bit(void); 140 static __inline paddr_t PTE_TO_PADDR(unsigned int pte); 141 142 static __inline paddr_t mips_tlbpfn_to_paddr(unsigned int pfn); 143 static __inline unsigned int mips_paddr_to_tlbpfn(paddr_t pa); 144 145 146 static __inline int 147 mips_pg_v(entry) 148 unsigned int entry; 149 { 150 if (MIPS_HAS_R4K_MMU) 151 return (entry & MIPS3_PG_V); 152 return (entry & MIPS1_PG_V); 153 } 154 155 static __inline int 156 mips_pg_wired(entry) 157 unsigned int entry; 158 { 159 if (MIPS_HAS_R4K_MMU) 160 return (entry & MIPS3_PG_WIRED); 161 return (entry & MIPS1_PG_WIRED); 162 } 163 164 static __inline unsigned int 165 mips_pg_m_bit() 166 { 167 if (MIPS_HAS_R4K_MMU) 168 return (MIPS3_PG_D); 169 return (MIPS1_PG_D); 170 } 171 172 static __inline unsigned int 173 mips_pg_ro_bit() 174 { 175 if (MIPS_HAS_R4K_MMU) 176 return (MIPS3_PG_RO); 177 return (MIPS1_PG_RO); 178 } 179 180 static __inline unsigned int 181 mips_pg_rw_bit() 182 { 183 if (MIPS_HAS_R4K_MMU) 184 return (MIPS3_PG_D); 185 return (MIPS1_PG_RW); 186 } 187 188 static __inline unsigned int 189 mips_pg_ropage_bit() 190 { 191 if (MIPS_HAS_R4K_MMU) 192 return (MIPS3_PG_ROPAGE); 193 return (MIPS1_PG_RO); 194 } 195 196 static __inline unsigned int 197 mips_pg_rwpage_bit() 198 { 199 if (MIPS_HAS_R4K_MMU) 200 return (MIPS3_PG_RWPAGE); 201 return (MIPS1_PG_RWPAGE); 202 } 203 204 static __inline unsigned int 205 mips_pg_cwpage_bit() 206 { 207 if (MIPS_HAS_R4K_MMU) 208 return (MIPS3_PG_CWPAGE); 209 return (MIPS1_PG_CWPAGE); 210 } 211 212 213 static __inline unsigned int 214 mips_pg_global_bit() 215 { 216 if (MIPS_HAS_R4K_MMU) 217 return (MIPS3_PG_G); 218 return (MIPS1_PG_G); 219 } 220 221 static __inline unsigned int 222 mips_pg_wired_bit() 223 { 224 if (MIPS_HAS_R4K_MMU) 225 return (MIPS3_PG_WIRED); 226 return (MIPS1_PG_WIRED); 227 } 228 229 static __inline paddr_t 230 PTE_TO_PADDR(pte) 231 unsigned int pte; 232 { 233 if (MIPS_HAS_R4K_MMU) 234 return (MIPS3_PTE_TO_PADDR(pte)); 235 return (MIPS1_PTE_TO_PADDR(pte)); 236 } 237 238 static __inline int 239 PAGE_IS_RDONLY(pte, va) 240 unsigned int pte; 241 vaddr_t va; 242 { 243 if (MIPS_HAS_R4K_MMU) 244 return (MIPS3_PAGE_IS_RDONLY(pte, va)); 245 return (MIPS1_PAGE_IS_RDONLY(pte, va)); 246 } 247 248 static __inline paddr_t 249 mips_tlbpfn_to_paddr(pfn) 250 unsigned int pfn; 251 { 252 if (MIPS_HAS_R4K_MMU) 253 return (mips3_tlbpfn_to_paddr(pfn)); 254 return (mips1_tlbpfn_to_paddr(pfn)); 255 } 256 257 static __inline unsigned int 258 mips_paddr_to_tlbpfn(pa) 259 paddr_t pa; 260 { 261 if (MIPS_HAS_R4K_MMU) 262 return (mips3_paddr_to_tlbpfn(pa)); 263 return (mips1_paddr_to_tlbpfn(pa)); 264 } 265 #endif 266 267 #endif /* ! _LOCORE */ 268 269 #if defined(_KERNEL) && !defined(_LOCORE) 270 /* 271 * Kernel virtual address to page table entry and visa versa. 272 */ 273 #define kvtopte(va) \ 274 (Sysmap + (((vaddr_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT)) 275 #define ptetokv(pte) \ 276 ((((pt_entry_t *)(pte) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 277 278 extern pt_entry_t *Sysmap; /* kernel pte table */ 279 extern u_int Sysmapsize; /* number of pte's in Sysmap */ 280 #endif /* defined(_KERNEL) && !defined(_LOCORE) */ 281 #endif /* __MIPS_PTE_H__ */ 282