1 /* $NetBSD: pte.h,v 1.13 2002/10/14 05:11:23 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright 1996 The Board of Trustees of The Leland Stanford 42 * Junior University. All Rights Reserved. 43 * 44 * Permission to use, copy, modify, and distribute this 45 * software and its documentation for any purpose and without 46 * fee is hereby granted, provided that the above copyright 47 * notice appear in all copies. Stanford University 48 * makes no representations about the suitability of this 49 * software for any purpose. It is provided "as is" without 50 * express or implied warranty. 51 */ 52 53 #ifndef __MIPS_PTE_H__ 54 #define __MIPS_PTE_H__ 55 56 #include <mips/mips1_pte.h> 57 #include <mips/mips3_pte.h> 58 59 #define PG_ASID 0x000000ff /* Address space ID */ 60 61 #ifndef _LOCORE 62 #include <mips/cpu.h> 63 64 typedef union pt_entry { 65 unsigned int pt_entry; /* for copying, etc. */ 66 struct mips1_pte pt_mips1_pte; /* for getting to bits by name */ 67 struct mips3_pte pt_mips3_pte; 68 } pt_entry_t; 69 70 /* 71 * Macros/inline functions to hide PTE format differences. 72 */ 73 74 #define mips_pg_nv_bit() (MIPS1_PG_NV) /* same on mips1 and mips3 */ 75 76 77 int pmap_is_page_ro(pmap_t, vaddr_t, int); 78 79 80 /* MIPS1-only */ 81 #if defined(MIPS1) && !defined(MIPS3_PLUS) 82 #define mips_pg_v(entry) ((entry) & MIPS1_PG_V) 83 #define mips_pg_wired(entry) ((entry) & MIPS1_PG_WIRED) 84 85 #define mips_pg_m_bit() (MIPS1_PG_D) 86 #define mips_pg_rw_bit() (MIPS1_PG_RW) /* no RW bits for mips1 */ 87 #define mips_pg_ro_bit() (MIPS1_PG_RO) 88 #define mips_pg_ropage_bit() (MIPS1_PG_RO) /* XXX not MIPS1_PG_ROPAGE? */ 89 #define mips_pg_rwpage_bit() (MIPS1_PG_RWPAGE) 90 #define mips_pg_cwpage_bit() (MIPS1_PG_CWPAGE) 91 #define mips_pg_global_bit() (MIPS1_PG_G) 92 #define mips_pg_wired_bit() (MIPS1_PG_WIRED) 93 94 #define PTE_TO_PADDR(pte) MIPS1_PTE_TO_PADDR((pte)) 95 #define PAGE_IS_RDONLY(pte, va) MIPS1_PAGE_IS_RDONLY((pte), (va)) 96 97 #define mips_tlbpfn_to_paddr(x) mips1_tlbpfn_to_paddr((vaddr_t)(x)) 98 #define mips_paddr_to_tlbpfn(x) mips1_paddr_to_tlbpfn((x)) 99 #endif /* mips1 */ 100 101 102 /* MIPS3 (or greater) only */ 103 #if !defined(MIPS1) && defined(MIPS3_PLUS) 104 #define mips_pg_v(entry) ((entry) & MIPS3_PG_V) 105 #define mips_pg_wired(entry) ((entry) & MIPS3_PG_WIRED) 106 107 #define mips_pg_m_bit() (MIPS3_PG_D) 108 #define mips_pg_rw_bit() (MIPS3_PG_D) 109 #define mips_pg_ro_bit() (MIPS3_PG_RO) 110 #define mips_pg_ropage_bit() (MIPS3_PG_ROPAGE) 111 #define mips_pg_rwpage_bit() (MIPS3_PG_RWPAGE) 112 #define mips_pg_cwpage_bit() (MIPS3_PG_CWPAGE) 113 #define mips_pg_global_bit() (MIPS3_PG_G) 114 #define mips_pg_wired_bit() (MIPS3_PG_WIRED) 115 116 #define PTE_TO_PADDR(pte) MIPS3_PTE_TO_PADDR((pte)) 117 #define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va)) 118 119 #define mips_tlbpfn_to_paddr(x) mips3_tlbpfn_to_paddr((vaddr_t)(x)) 120 #define mips_paddr_to_tlbpfn(x) mips3_paddr_to_tlbpfn((x)) 121 #endif /* mips3 */ 122 123 /* MIPS1 and MIPS3 (or greater) */ 124 #if defined(MIPS1) && defined(MIPS3_PLUS) 125 126 static __inline int 127 mips_pg_v(unsigned int entry), 128 mips_pg_wired(unsigned int entry), 129 PAGE_IS_RDONLY(unsigned int pte, vaddr_t va); 130 131 static __inline unsigned int 132 mips_pg_wired_bit(void), mips_pg_m_bit(void), 133 mips_pg_ro_bit(void), mips_pg_rw_bit(void), 134 mips_pg_ropage_bit(void), 135 mips_pg_cwpage_bit(void), 136 mips_pg_rwpage_bit(void), 137 mips_pg_global_bit(void); 138 static __inline paddr_t PTE_TO_PADDR(unsigned int pte); 139 140 static __inline paddr_t mips_tlbpfn_to_paddr(unsigned int pfn); 141 static __inline unsigned int mips_paddr_to_tlbpfn(paddr_t pa); 142 143 144 static __inline int 145 mips_pg_v(entry) 146 unsigned int entry; 147 { 148 if (MIPS_HAS_R4K_MMU) 149 return (entry & MIPS3_PG_V); 150 return (entry & MIPS1_PG_V); 151 } 152 153 static __inline int 154 mips_pg_wired(entry) 155 unsigned int entry; 156 { 157 if (MIPS_HAS_R4K_MMU) 158 return (entry & MIPS3_PG_WIRED); 159 return (entry & MIPS1_PG_WIRED); 160 } 161 162 static __inline unsigned int 163 mips_pg_m_bit() 164 { 165 if (MIPS_HAS_R4K_MMU) 166 return (MIPS3_PG_D); 167 return (MIPS1_PG_D); 168 } 169 170 static __inline unsigned int 171 mips_pg_ro_bit() 172 { 173 if (MIPS_HAS_R4K_MMU) 174 return (MIPS3_PG_RO); 175 return (MIPS1_PG_RO); 176 } 177 178 static __inline unsigned int 179 mips_pg_rw_bit() 180 { 181 if (MIPS_HAS_R4K_MMU) 182 return (MIPS3_PG_D); 183 return (MIPS1_PG_RW); 184 } 185 186 static __inline unsigned int 187 mips_pg_ropage_bit() 188 { 189 if (MIPS_HAS_R4K_MMU) 190 return (MIPS3_PG_ROPAGE); 191 return (MIPS1_PG_RO); 192 } 193 194 static __inline unsigned int 195 mips_pg_rwpage_bit() 196 { 197 if (MIPS_HAS_R4K_MMU) 198 return (MIPS3_PG_RWPAGE); 199 return (MIPS1_PG_RWPAGE); 200 } 201 202 static __inline unsigned int 203 mips_pg_cwpage_bit() 204 { 205 if (MIPS_HAS_R4K_MMU) 206 return (MIPS3_PG_CWPAGE); 207 return (MIPS1_PG_CWPAGE); 208 } 209 210 211 static __inline unsigned int 212 mips_pg_global_bit() 213 { 214 if (MIPS_HAS_R4K_MMU) 215 return (MIPS3_PG_G); 216 return (MIPS1_PG_G); 217 } 218 219 static __inline unsigned int 220 mips_pg_wired_bit() 221 { 222 if (MIPS_HAS_R4K_MMU) 223 return (MIPS3_PG_WIRED); 224 return (MIPS1_PG_WIRED); 225 } 226 227 static __inline paddr_t 228 PTE_TO_PADDR(pte) 229 unsigned int pte; 230 { 231 if (MIPS_HAS_R4K_MMU) 232 return (MIPS3_PTE_TO_PADDR(pte)); 233 return (MIPS1_PTE_TO_PADDR(pte)); 234 } 235 236 static __inline int 237 PAGE_IS_RDONLY(pte, va) 238 unsigned int pte; 239 vaddr_t va; 240 { 241 if (MIPS_HAS_R4K_MMU) 242 return (MIPS3_PAGE_IS_RDONLY(pte, va)); 243 return (MIPS1_PAGE_IS_RDONLY(pte, va)); 244 } 245 246 static __inline paddr_t 247 mips_tlbpfn_to_paddr(pfn) 248 unsigned int pfn; 249 { 250 if (MIPS_HAS_R4K_MMU) 251 return (mips3_tlbpfn_to_paddr(pfn)); 252 return (mips1_tlbpfn_to_paddr(pfn)); 253 } 254 255 static __inline unsigned int 256 mips_paddr_to_tlbpfn(pa) 257 paddr_t pa; 258 { 259 if (MIPS_HAS_R4K_MMU) 260 return (mips3_paddr_to_tlbpfn(pa)); 261 return (mips1_paddr_to_tlbpfn(pa)); 262 } 263 #endif 264 265 #endif /* ! _LOCORE */ 266 267 #if defined(_KERNEL) && !defined(_LOCORE) 268 /* 269 * Kernel virtual address to page table entry and visa versa. 270 */ 271 #define kvtopte(va) \ 272 (Sysmap + (((vaddr_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT)) 273 #define ptetokv(pte) \ 274 ((((pt_entry_t *)(pte) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 275 276 extern pt_entry_t *Sysmap; /* kernel pte table */ 277 extern u_int Sysmapsize; /* number of pte's in Sysmap */ 278 #endif /* defined(_KERNEL) && !defined(_LOCORE) */ 279 #endif /* __MIPS_PTE_H__ */ 280