xref: /netbsd/sys/arch/mips/mips/cache_r3k.c (revision bf9ec67e)
1 /*	$NetBSD: cache_r3k.c,v 1.2 2001/11/14 18:26:23 thorpej Exp $	*/
2 
3 /*
4  * Copyright 2001 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #include <sys/param.h>
39 
40 #include <mips/cache.h>
41 #include <mips/cache_r3k.h>
42 
43 /*
44  * Cache operations for R3000-style caches:
45  *
46  *	- Direct-mapped
47  *	- Write-through
48  *	- Physically indexed, physically tagged
49  */
50 
51 #define	round_line(x)		(((x) + 31) & ~31)
52 #define	trunc_line(x)		((x) & ~31)
53 
54 void
55 r3k_icache_sync_all(void)
56 {
57 	vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
58 	vaddr_t eva = va + mips_picache_size;
59 
60 	r3k_picache_do_inv(va, eva);
61 }
62 
63 void
64 r3k_icache_sync_range(vaddr_t va, vsize_t size)
65 {
66 	vaddr_t eva = round_line(va + size);
67 
68 	va = trunc_line(va);
69 
70 	if ((eva - va) >= mips_picache_size) {
71 		r3k_icache_sync_all();
72 		return;
73 	}
74 
75 	r3k_picache_do_inv(va, eva);
76 }
77 
78 void
79 r3k_pdcache_wbinv_all(void)
80 {
81 	vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
82 	vaddr_t eva = va + mips_pdcache_size;
83 
84 	/* Cache is write-through. */
85 
86 	r3k_pdcache_do_inv(va, eva);
87 }
88 
89 void
90 r3k_pdcache_inv_range(vaddr_t va, vsize_t size)
91 {
92 	vaddr_t eva = round_line(va + size);
93 
94 	va = trunc_line(va);
95 
96 	if ((eva - va) >= mips_pdcache_size) {
97 		r3k_pdcache_wbinv_all();
98 		return;
99 	}
100 
101 	r3k_pdcache_do_inv(va, eva);
102 }
103 
104 void
105 r3k_pdcache_wb_range(vaddr_t va, vsize_t size)
106 {
107 
108 	/* Cache is write-though. */
109 }
110 
111 #undef round_line
112 #undef trunc_line
113