1/* $NetBSD: cache_r3k_subr.S,v 1.2 2001/11/14 18:26:23 thorpej Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Digital Equipment Corporation and Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permited provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * Copyright (C) 1989 Digital Equipment Corporation. 39 * Permission to use, copy, modify, and distribute this software and 40 * its documentation for any purpose and without fee is hereby granted, 41 * provided that the above copyright notice appears in all copies. 42 * Digital Equipment Corporation makes no representations about the 43 * suitability of this software for any purpose. It is provided "as is" 44 * without express or implied warranty. 45 * 46 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s, 47 * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL) 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s, 49 * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s, 51 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL) 52 * 53 * @(#)locore.s 8.5 (Berkeley) 1/4/94 54 */ 55 56#include <mips/asm.h> 57#include <mips/cpuregs.h> 58 59 .set noreorder 60 61/* 62 * r3k_size_cache: 63 * 64 * This works by writing marker values repeatedly at possible 65 * cache boundaries (256K to 512). Since the cache is direct-mapped 66 * and the address ranges have aliased with given cache size, 67 * whatever value is found at cache location zero indicates the size. 68 */ 69LEAF_NOPROFILE(r3k_size_cache) 70 la v0, 1f 71 or v0, MIPS_KSEG1_START 72 j v0 # run uncached 73 mfc0 v1, MIPS_COP_0_STATUS 741: 75 mtc0 a0, MIPS_COP_0_STATUS # disable interrupts, 76 nop # isolating cache 77 nop 78 nop 79 nop 80 81 li t1, 512 # minimum cache size 82 li t2, 256*1024 # maximum cache size 83 842: sw t2, MIPS_KSEG0_START(t2) 85 bne t2, t1, 2b 86 srl t2, 1 # BDSLOT 87 lw v0, MIPS_KSEG0_START(zero) # magic! cache size is there 88 89 li t1, MIPS_KSEG0_START 90 addu t2, t1, v0 91 923: sw zero, 0(t1) # clear parity 93 sw zero, 4(t1) 94 sw zero, 8(t1) 95 sw zero, 12(t1) 96 sb zero, 0(t1) # invalidate 97 sb zero, 4(t1) 98 sb zero, 8(t1) 99 addu t1, 16 100 bne t1, t2, 3b 101 sb zero, -4(t1) # BDSLOT 102 103 # 4 cycles to pipeline to drain. 104 nop 105 nop 106 nop 107 nop 108 109 mtc0 v1, MIPS_COP_0_STATUS 110 nop 111 nop 112 nop 113 nop 114 115 j ra 116 nop 117END(r3k_size_cache) 118 119/* 120 * r3k_picache_size: 121 * 122 * Determine the size of the R3000 I-cache. 123 */ 124LEAF_NOPROFILE(r3k_picache_size) 125 li a0, MIPS1_ISOL_CACHES|MIPS1_SWAP_CACHES 126 j _C_LABEL(r3k_size_cache) 127 nop 128END(r3k_picache_size) 129 130/* 131 * r3k_pdcache_size: 132 * 133 * Determine the size of the R3000 D-cache. 134 */ 135LEAF_NOPROFILE(r3k_pdcache_size) 136 li a0, MIPS1_ISOL_CACHES 137 j _C_LABEL(r3k_size_cache) 138 nop 139END(r3k_pdcache_size) 140 141/* 142 * r3k_picache_do_inv: 143 * 144 * Invalidate a range from the R3000 I-cache. 145 * 146 * Arguments: a0 starting address 147 * a1 ending address 148 * 149 * Addresses must already be cache-line aligned. 150 */ 151LEAF(r3k_picache_do_inv) 152 mfc0 t0, MIPS_COP_0_STATUS # Save SR. 153 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts. 154 155 la v1, 1f 156 or v1, MIPS_KSEG1_START # Run uncached. 157 j v1 158 nop 159 1601: 161 # Swap the caches (so we store to I$) and isolate them from memory. 162 li v1, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES 163 mtc0 v1, MIPS_COP_0_STATUS 164 nop 165 nop 1661: 167 addu a0, a0, 4 168 bne a0, a1, 1b 169 sb zero, -4(a0) 170 171 # 4 cycles to wait for pipeline to drain. 172 173 nop 174 nop 175 176 mtc0 t0, MIPS_COP_0_STATUS # Restore SR. 177 nop 178 nop 179 j ra # Jumps back to cached address. 180 nop 181END(r3k_picache_do_inv) 182 183/* 184 * r3k_pdcache_do_inv: 185 * 186 * Invalidate a range from the R3000 D-cache. 187 * 188 * Arguments: a0 starting address 189 * a1 ending address 190 * 191 * Addresses must already be cache-line aligned. 192 */ 193LEAF(r3k_pdcache_do_inv) 194 mfc0 t0, MIPS_COP_0_STATUS # Save SR. 195 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts. 196 nop 197 198 # Isolate the caches from memory. 199 li v1, MIPS_SR_ISOL_CACHES 200 mtc0 v1, MIPS_COP_0_STATUS 201 nop 202 nop 2031: 204 sb zero, 0(a0) 205 sb zero, 4(a0) 206 sb zero, 8(a0) 207 sb zero, 12(a0) 208 sb zero, 16(a0) 209 sb zero, 20(a0) 210 sb zero, 24(a0) 211 addu a0, 32 212 bltu a0, a1, 1b 213 sb zero, -4(a0) 214 215 # 4 cycles to wait for pipeline to drain. 216 217 nop 218 nop 219 220 mtc0 t0, MIPS_COP_0_STATUS # Restore SR. 221 nop 222 nop 223 j ra # Jumps back to cached address. 224 nop 225END(r3k_pdcache_do_inv) 226