1/* $NetBSD: cache_tx39_subr.S,v 1.3 2008/04/28 20:23:28 martin Exp $ */ 2 3/*- 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi; and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * XXX THIS IS NOT YET COMPLETE. 34 */ 35 36#include <mips/asm.h> 37#include <mips/cpuregs.h> 38#include <mips/r3900regs.h> 39#include <mips/cache_tx39.h> 40 41 .set noreorder 42 43/* 44 * tx3900_icache_do_inv_index_16: 45 * 46 * Do an Index Invalidate of the I-cache for the specified 47 * range. 48 * 49 * Arguments: a0 starting address 50 * a1 ending address 51 * 52 * Addresses must already be cache-line aligned. 53 */ 54LEAF(tx3900_icache_do_inv_index_16) 55 mfc0 t0, MIPS_COP_0_STATUS # Save SR. 56 nop 57 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts. 58 nop 59 60 # Disable the I-cache. 61 li t1, ~R3900_CONFIG_ICE 62 mfc0 t2, R3900_COP_0_CONFIG 63 and t1, t1, t2 64 nop 65 mtc0 t1, R3900_COP_0_CONFIG 66 67 # Break the I-stream. 68 j 1f 69 nop 70 71 .set push 72 .set mips3 731: 74 cache CACHE_TX39_I|CACHEOP_TX3900_INDEX_INV, 0(a0) 75 addiu a0, a0, 16 76 bltu a0, a1, 1b 77 nop 78 .set pop 79 80 # Re-enable I-cache. 81 nop 82 mtc0 t2, R3900_COP_0_CONFIG 83 nop 84 mtc0 t0, MIPS_COP_0_STATUS # Restore SR. 85 86 j ra 87 nop 88END(tx3900_icache_do_inv_index_16) 89 90/* 91 * tx3920_icache_do_inv_16: 92 * 93 * Do a Hit Invalidate of the I-cache for the specified 94 * range. 95 * 96 * Arguments: a0 starting address 97 * a1 ending address 98 * 99 * Addresses must already be cache-line aligned. 100 */ 101LEAF(tx3920_icache_do_inv_16) 102 mfc0 t0, MIPS_COP_0_STATUS # Save SR. 103 nop 104 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts. 105 nop 106 107 # Disable the I-cache. 108 li t1, ~R3900_CONFIG_ICE 109 mfc0 t2, R3900_COP_0_CONFIG 110 and t1, t1, t2 111 nop 112 mtc0 t1, R3900_COP_0_CONFIG 113 114 # Break the I-stream. 115 j 1f 116 nop 117 118 .set push 119 .set mips3 1201: 121 cache CACHE_TX39_I|CACHEOP_TX3920_HIT_INV, 0(a0) 122 addiu a0, a0, 16 123 bltu a0, a1, 1b 124 nop 125 .set pop 126 127 # Re-enable I-cache. 128 nop 129 mtc0 t2, R3900_COP_0_CONFIG 130 nop 131 mtc0 t0, MIPS_COP_0_STATUS # Restore SR. 132 133 j ra 134 nop 135END(tx3920_icache_do_inv_16) 136