1 /* $NetBSD: sbmac.c,v 1.2 2002/03/06 00:05:06 simonb Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. Neither the "Broadcom Corporation" name nor any 19 * trademark or logo of Broadcom Corporation may be used to endorse or 20 * promote products derived from this software without the prior written 21 * permission of Broadcom Corporation. 22 * 23 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 26 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 27 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 28 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include "bpfilter.h" 37 #include "opt_inet.h" 38 #include "opt_ns.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/queue.h> 48 #include <sys/device.h> 49 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_ether.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 56 #if NBPFILTER > 0 57 #include <net/bpf.h> 58 #endif 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/if_inarp.h> 63 #endif 64 65 #ifdef NS 66 #include <netns/ns.h> 67 #include <netns/ns_if.h> 68 #endif 69 70 #include <machine/locore.h> 71 72 #include "sbobiovar.h" 73 74 #include <dev/mii/mii.h> 75 #include <dev/mii/miivar.h> 76 #include <dev/mii/mii_bitbang.h> 77 78 #include <mips/sibyte/include/sb1250_defs.h> 79 #include <mips/sibyte/include/sb1250_regs.h> 80 #include <mips/sibyte/include/sb1250_mac.h> 81 #include <mips/sibyte/include/sb1250_dma.h> 82 83 84 /* ********************************************************************* 85 * Simple types 86 ********************************************************************* */ 87 88 89 typedef u_long sbmac_port_t; 90 typedef uint64_t sbmac_physaddr_t; 91 typedef uint64_t sbmac_enetaddr_t; 92 93 typedef enum { sbmac_speed_auto, sbmac_speed_10, 94 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; 95 96 typedef enum { sbmac_duplex_auto, sbmac_duplex_half, 97 sbmac_duplex_full } sbmac_duplex_t; 98 99 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, 100 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; 101 102 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, 103 sbmac_state_broken } sbmac_state_t; 104 105 106 /* ********************************************************************* 107 * Macros 108 ********************************************************************* */ 109 110 111 #define SBDMA_NEXTBUF(d, f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ 112 (d)->sbdma_dscrtable : (d)->f+1) 113 114 115 #define CACHELINESIZE 32 116 #define NUMCACHEBLKS(x) (((x)+CACHELINESIZE-1)/CACHELINESIZE) 117 #define KMALLOC(x) malloc((x), M_DEVBUF, M_DONTWAIT) 118 #define KVTOPHYS(x) kvtophys((vaddr_t)(x)) 119 120 #ifdef SBMACDEBUG 121 #define dprintf(x) printf x 122 #else 123 #define dprintf(x) 124 #endif 125 126 #define SBMAC_READCSR(t) mips3_ld((uint64_t *) (t)) 127 #define SBMAC_WRITECSR(t, v) mips3_sd((uint64_t *) (t), (v)) 128 129 #define PKSEG1(x) ((sbmac_port_t) MIPS_PHYS_TO_KSEG1(x)) 130 131 #define SBMAC_MAX_TXDESCR 64 132 #define SBMAC_MAX_RXDESCR 64 133 134 #define ETHER_ALIGN 2 135 136 /* ********************************************************************* 137 * DMA Descriptor structure 138 ********************************************************************* */ 139 140 typedef struct sbdmadscr_s { 141 uint64_t dscr_a; 142 uint64_t dscr_b; 143 } sbdmadscr_t; 144 145 /* ********************************************************************* 146 * DMA Controller structure 147 ********************************************************************* */ 148 149 typedef struct sbmacdma_s { 150 151 /* 152 * This stuff is used to identify the channel and the registers 153 * associated with it. 154 */ 155 156 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ 157 int sbdma_channel; /* channel number */ 158 int sbdma_txdir; /* direction (1=transmit) */ 159 int sbdma_maxdescr; /* total # of descriptors in ring */ 160 sbmac_port_t sbdma_config0; /* DMA config register 0 */ 161 sbmac_port_t sbdma_config1; /* DMA config register 1 */ 162 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */ 163 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */ 164 sbmac_port_t sbdma_curdscr; /* current descriptor address */ 165 166 /* 167 * This stuff is for maintenance of the ring 168 */ 169 170 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ 171 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ 172 173 struct mbuf **sbdma_ctxtable; /* context table, one per descr */ 174 175 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ 176 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ 177 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ 178 } sbmacdma_t; 179 180 181 /* ********************************************************************* 182 * Ethernet softc structure 183 ********************************************************************* */ 184 185 struct sbmac_softc { 186 187 /* 188 * NetBSD-specific things 189 */ 190 struct device sc_dev; /* base device (must be first) */ 191 struct ethercom sc_ethercom; /* Ethernet common part */ 192 struct mii_data sc_mii; 193 struct callout sc_tick_ch; 194 195 int sbm_if_flags; 196 void *sbm_intrhand; 197 198 /* 199 * Controller-specific things 200 */ 201 202 sbmac_port_t sbm_base; /* MAC's base address */ 203 sbmac_state_t sbm_state; /* current state */ 204 205 sbmac_port_t sbm_macenable; /* MAC Enable Register */ 206 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */ 207 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */ 208 sbmac_port_t sbm_framecfg; /* Frame configuration register */ 209 sbmac_port_t sbm_rxfilter; /* receive filter register */ 210 sbmac_port_t sbm_isr; /* Interrupt status register */ 211 sbmac_port_t sbm_imr; /* Interrupt mask register */ 212 213 sbmac_speed_t sbm_speed; /* current speed */ 214 sbmac_duplex_t sbm_duplex; /* current duplex */ 215 sbmac_fc_t sbm_fc; /* current flow control setting */ 216 int sbm_rxflags; /* received packet flags */ 217 218 u_char sbm_hwaddr[ETHER_ADDR_LEN]; 219 220 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ 221 sbmacdma_t sbm_rxdma; 222 }; 223 224 225 /* ********************************************************************* 226 * Externs 227 ********************************************************************* */ 228 229 extern paddr_t kvtophys(vaddr_t); 230 231 /* ********************************************************************* 232 * Prototypes 233 ********************************************************************* */ 234 235 static void sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, 236 int txrx, int maxdescr); 237 static void sbdma_channel_start(sbmacdma_t *d); 238 static int sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m); 239 static int sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m); 240 static void sbdma_emptyring(sbmacdma_t *d); 241 static void sbdma_fillring(sbmacdma_t *d); 242 static void sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d); 243 static void sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d); 244 static void sbmac_initctx(struct sbmac_softc *s); 245 static void sbmac_channel_start(struct sbmac_softc *s); 246 static void sbmac_channel_stop(struct sbmac_softc *s); 247 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *, 248 sbmac_state_t); 249 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); 250 static void sbmac_init_and_start(struct sbmac_softc *sc); 251 static uint64_t sbmac_addr2reg(u_char *ptr); 252 static void sbmac_intr(void *xsc, uint32_t status, uint32_t pc); 253 static void sbmac_start(struct ifnet *ifp); 254 static void sbmac_setmulti(struct sbmac_softc *sc); 255 static int sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 256 static int sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 257 static int sbmac_mediachange(struct ifnet *ifp); 258 static void sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 259 static void sbmac_watchdog(struct ifnet *ifp); 260 static int sbmac_match(struct device *parent, struct cfdata *match, void *aux); 261 static void sbmac_attach(struct device *parent, struct device *self, void *aux); 262 static int sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed); 263 static int sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, 264 sbmac_fc_t fc); 265 static void sbmac_tick(void *arg); 266 267 268 /* ********************************************************************* 269 * Globals 270 ********************************************************************* */ 271 272 const struct cfattach sbmac_ca = { 273 sizeof(struct sbmac_softc), sbmac_match, sbmac_attach, 274 }; 275 276 277 uint32_t sbmac_mii_bitbang_read(struct device *self); 278 void sbmac_mii_bitbang_write(struct device *self, uint32_t val); 279 280 static const struct mii_bitbang_ops sbmac_mii_bitbang_ops = { 281 sbmac_mii_bitbang_read, 282 sbmac_mii_bitbang_write, 283 { 284 (uint32_t)M_MAC_MDIO_OUT, /* MII_BIT_MDO */ 285 (uint32_t)M_MAC_MDIO_IN, /* MII_BIT_MDI */ 286 (uint32_t)M_MAC_MDC, /* MII_BIT_MDC */ 287 0, /* MII_BIT_DIR_HOST_PHY */ 288 (uint32_t)M_MAC_MDIO_DIR /* MII_BIT_DIR_PHY_HOST */ 289 } 290 }; 291 292 uint32_t 293 sbmac_mii_bitbang_read(struct device *self) 294 { 295 struct sbmac_softc *sc = (void *) self; 296 sbmac_port_t reg; 297 298 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 299 return (uint32_t) SBMAC_READCSR(reg); 300 } 301 302 void 303 sbmac_mii_bitbang_write(struct device *self, uint32_t val) 304 { 305 struct sbmac_softc *sc = (void *) self; 306 sbmac_port_t reg; 307 308 reg = PKSEG1(sc->sbm_base + R_MAC_MDIO); 309 310 SBMAC_WRITECSR(reg, (val & 311 (M_MAC_MDC|M_MAC_MDIO_DIR|M_MAC_MDIO_OUT|M_MAC_MDIO_IN))); 312 } 313 314 /* 315 * Read an PHY register through the MII. 316 */ 317 static int 318 sbmac_mii_readreg(struct device *self, int phy, int reg) 319 { 320 321 return (mii_bitbang_readreg(self, &sbmac_mii_bitbang_ops, phy, reg)); 322 } 323 324 /* 325 * Write to a PHY register through the MII. 326 */ 327 static void 328 sbmac_mii_writereg(struct device *self, int phy, int reg, int val) 329 { 330 331 mii_bitbang_writereg(self, &sbmac_mii_bitbang_ops, phy, reg, val); 332 } 333 334 static void 335 sbmac_mii_statchg(struct device *self) 336 { 337 struct sbmac_softc *sc = (struct sbmac_softc *)self; 338 sbmac_state_t oldstate; 339 340 /* Stop the MAC in preparation for changing all of the parameters. */ 341 oldstate = sbmac_set_channel_state(sc, sbmac_state_off); 342 343 switch (sc->sc_ethercom.ec_if.if_baudrate) { 344 default: /* if autonegotiation fails, assume 10Mbit */ 345 case IF_Mbps(10): 346 sbmac_set_speed(sc, sbmac_speed_10); 347 break; 348 349 case IF_Mbps(100): 350 sbmac_set_speed(sc, sbmac_speed_100); 351 break; 352 353 case IF_Mbps(1000): 354 sbmac_set_speed(sc, sbmac_speed_1000); 355 break; 356 } 357 358 if (sc->sc_mii.mii_media_active & IFM_FDX) { 359 /* Configure for full-duplex */ 360 /* XXX: is flow control right for 10, 100? */ 361 sbmac_set_duplex(sc, sbmac_duplex_full, sbmac_fc_frame); 362 } else { 363 /* Configure for half-duplex */ 364 /* XXX: is flow control right? */ 365 sbmac_set_duplex(sc, sbmac_duplex_half, sbmac_fc_disabled); 366 } 367 368 /* And put it back into its former state. */ 369 sbmac_set_channel_state(sc, oldstate); 370 } 371 372 /* ********************************************************************* 373 * SBDMA_INITCTX(d, s, chan, txrx, maxdescr) 374 * 375 * Initialize a DMA channel context. Since there are potentially 376 * eight DMA channels per MAC, it's nice to do this in a standard 377 * way. 378 * 379 * Input parameters: 380 * d - sbmacdma_t structure (DMA channel context) 381 * s - sbmac_softc structure (pointer to a MAC) 382 * chan - channel number (0..1 right now) 383 * txrx - Identifies DMA_TX or DMA_RX for channel direction 384 * maxdescr - number of descriptors 385 * 386 * Return value: 387 * nothing 388 ********************************************************************* */ 389 390 static void 391 sbdma_initctx(sbmacdma_t *d, struct sbmac_softc *s, int chan, int txrx, 392 int maxdescr) 393 { 394 /* 395 * Save away interesting stuff in the structure 396 */ 397 398 d->sbdma_eth = s; 399 d->sbdma_channel = chan; 400 d->sbdma_txdir = txrx; 401 402 /* 403 * initialize register pointers 404 */ 405 406 d->sbdma_config0 = PKSEG1(s->sbm_base + 407 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG0)); 408 d->sbdma_config1 = PKSEG1(s->sbm_base + 409 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CONFIG0)); 410 d->sbdma_dscrbase = PKSEG1(s->sbm_base + 411 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_BASE)); 412 d->sbdma_dscrcnt = PKSEG1(s->sbm_base + 413 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_DSCR_CNT)); 414 d->sbdma_curdscr = PKSEG1(s->sbm_base + 415 R_MAC_DMA_REGISTER(txrx, chan, R_MAC_DMA_CUR_DSCRADDR)); 416 417 /* 418 * Allocate memory for the ring 419 */ 420 421 d->sbdma_maxdescr = maxdescr; 422 423 d->sbdma_dscrtable = (sbdmadscr_t *) 424 KMALLOC(d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 425 426 bzero(d->sbdma_dscrtable, d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 427 428 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 429 430 d->sbdma_dscrtable_phys = KVTOPHYS(d->sbdma_dscrtable); 431 432 /* 433 * And context table 434 */ 435 436 d->sbdma_ctxtable = (struct mbuf **) 437 KMALLOC(d->sbdma_maxdescr*sizeof(struct mbuf *)); 438 439 bzero(d->sbdma_ctxtable, d->sbdma_maxdescr*sizeof(struct mbuf *)); 440 } 441 442 /* ********************************************************************* 443 * SBDMA_CHANNEL_START(d) 444 * 445 * Initialize the hardware registers for a DMA channel. 446 * 447 * Input parameters: 448 * d - DMA channel to init (context must be previously init'd 449 * 450 * Return value: 451 * nothing 452 ********************************************************************* */ 453 454 static void 455 sbdma_channel_start(sbmacdma_t *d) 456 { 457 /* 458 * Turn on the DMA channel 459 */ 460 461 SBMAC_WRITECSR(d->sbdma_config1, 0); 462 463 SBMAC_WRITECSR(d->sbdma_dscrbase, d->sbdma_dscrtable_phys); 464 465 SBMAC_WRITECSR(d->sbdma_config0, V_DMA_RINGSZ(d->sbdma_maxdescr) | 0); 466 467 /* 468 * Initialize ring pointers 469 */ 470 471 d->sbdma_addptr = d->sbdma_dscrtable; 472 d->sbdma_remptr = d->sbdma_dscrtable; 473 } 474 475 /* ********************************************************************* 476 * SBDMA_ADD_RCVBUFFER(d, m) 477 * 478 * Add a buffer to the specified DMA channel. For receive channels, 479 * this queues a buffer for inbound packets. 480 * 481 * Input parameters: 482 * d - DMA channel descriptor 483 * m - mbuf to add, or NULL if we should allocate one. 484 * 485 * Return value: 486 * 0 if buffer could not be added (ring is full) 487 * 1 if buffer added successfully 488 ********************************************************************* */ 489 490 491 static int 492 sbdma_add_rcvbuffer(sbmacdma_t *d, struct mbuf *m) 493 { 494 sbdmadscr_t *dsc; 495 sbdmadscr_t *nextdsc; 496 struct mbuf *m_new = NULL; 497 498 /* get pointer to our current place in the ring */ 499 500 dsc = d->sbdma_addptr; 501 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 502 503 /* 504 * figure out if the ring is full - if the next descriptor 505 * is the same as the one that we're going to remove from 506 * the ring, the ring is full 507 */ 508 509 if (nextdsc == d->sbdma_remptr) 510 return ENOSPC; 511 512 /* 513 * Allocate an mbuf if we don't already have one. 514 * If we do have an mbuf, reset it so that it's empty. 515 */ 516 517 if (m == NULL) { 518 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 519 if (m_new == NULL) { 520 printf("%s: mbuf allocation failed\n", 521 d->sbdma_eth->sc_dev.dv_xname); 522 return ENOBUFS; 523 } 524 525 MCLGET(m_new, M_DONTWAIT); 526 if (!(m_new->m_flags & M_EXT)) { 527 printf("%s: mbuf cluster allocation failed\n", 528 d->sbdma_eth->sc_dev.dv_xname); 529 m_freem(m_new); 530 return ENOBUFS; 531 } 532 533 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 534 m_adj(m_new, ETHER_ALIGN); 535 } else { 536 m_new = m; 537 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 538 m_new->m_data = m_new->m_ext.ext_buf; 539 m_adj(m_new, ETHER_ALIGN); 540 } 541 542 /* 543 * fill in the descriptor 544 */ 545 546 dsc->dscr_a = KVTOPHYS(mtod(m_new, caddr_t)) | 547 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(ETHER_ALIGN + m_new->m_len)) | 548 M_DMA_DSCRA_INTERRUPT; 549 550 /* receiving: no options */ 551 dsc->dscr_b = 0; 552 553 /* 554 * fill in the context 555 */ 556 557 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 558 559 /* 560 * point at next packet 561 */ 562 563 d->sbdma_addptr = nextdsc; 564 565 /* 566 * Give the buffer to the DMA engine. 567 */ 568 569 SBMAC_WRITECSR(d->sbdma_dscrcnt, 1); 570 571 return 0; /* we did it */ 572 } 573 574 /* ********************************************************************* 575 * SBDMA_ADD_TXBUFFER(d, m) 576 * 577 * Add a transmit buffer to the specified DMA channel, causing a 578 * transmit to start. 579 * 580 * Input parameters: 581 * d - DMA channel descriptor 582 * m - mbuf to add 583 * 584 * Return value: 585 * 0 transmit queued successfully 586 * otherwise error code 587 ********************************************************************* */ 588 589 590 static int 591 sbdma_add_txbuffer(sbmacdma_t *d, struct mbuf *m) 592 { 593 sbdmadscr_t *dsc; 594 sbdmadscr_t *nextdsc; 595 struct mbuf *m_new = NULL; 596 int length; 597 598 /* get pointer to our current place in the ring */ 599 600 dsc = d->sbdma_addptr; 601 nextdsc = SBDMA_NEXTBUF(d, sbdma_addptr); 602 603 /* 604 * figure out if the ring is full - if the next descriptor 605 * is the same as the one that we're going to remove from 606 * the ring, the ring is full 607 */ 608 609 if (nextdsc == d->sbdma_remptr) 610 return ENOSPC; 611 612 #if 0 613 do { 614 struct mbuf *m0; 615 616 printf("mbuf chain: "); 617 for (m0 = m; m0 != 0; m0 = m0->m_next) { 618 printf("%d%c/%X ", m0->m_len, 619 m0->m_flags & M_EXT ? 'X' : 'N', 620 mtod(m0, u_int)); 621 } 622 printf("\n"); 623 } while (0); 624 #endif 625 626 /* 627 * [BEGIN XXX] 628 * XXX Copy/coalesce the mbufs into a single mbuf cluster (we assume 629 * it will fit). This is a temporary hack to get us going. 630 */ 631 632 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 633 if (m_new == NULL) { 634 printf("%s: mbuf allocation failed\n", 635 d->sbdma_eth->sc_dev.dv_xname); 636 return ENOBUFS; 637 } 638 639 MCLGET(m_new, M_DONTWAIT); 640 if (!(m_new->m_flags & M_EXT)) { 641 printf("%s: mbuf cluster allocation failed\n", 642 d->sbdma_eth->sc_dev.dv_xname); 643 m_freem(m_new); 644 return ENOBUFS; 645 } 646 647 m_new->m_len = m_new->m_pkthdr.len= MCLBYTES; 648 /*m_adj(m_new, ETHER_ALIGN);*/ 649 650 /* 651 * XXX Don't forget to include the offset portion in the 652 * XXX cache block calculation when this code is rewritten! 653 */ 654 655 /* 656 * Copy data 657 */ 658 659 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 660 m_new->m_len = m_new->m_pkthdr.len = m->m_pkthdr.len; 661 662 /* Free old mbuf 'm', actual mbuf is now 'm_new' */ 663 664 // XXX: CALLERS WILL FREE, they might have to bpf_mtap() if this 665 // XXX: function succeeds. 666 // m_freem(m); 667 length = m_new->m_len; 668 669 /* [END XXX] */ 670 671 /* 672 * fill in the descriptor 673 */ 674 675 dsc->dscr_a = KVTOPHYS(mtod(m_new, caddr_t)) | 676 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(m_new->m_len)) | 677 M_DMA_DSCRA_INTERRUPT | 678 M_DMA_ETHTX_SOP; 679 680 /* transmitting: set outbound options and length */ 681 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 682 V_DMA_DSCRB_PKT_SIZE(length); 683 684 /* 685 * fill in the context 686 */ 687 688 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = m_new; 689 690 /* 691 * point at next packet 692 */ 693 694 d->sbdma_addptr = nextdsc; 695 696 /* 697 * Give the buffer to the DMA engine. 698 */ 699 700 SBMAC_WRITECSR(d->sbdma_dscrcnt, 1); 701 702 return 0; /* we did it */ 703 } 704 705 /* ********************************************************************* 706 * SBDMA_EMPTYRING(d) 707 * 708 * Free all allocated mbufs on the specified DMA channel; 709 * 710 * Input parameters: 711 * d - DMA channel 712 * 713 * Return value: 714 * nothing 715 ********************************************************************* */ 716 717 static void 718 sbdma_emptyring(sbmacdma_t *d) 719 { 720 int idx; 721 struct mbuf *m; 722 723 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 724 m = d->sbdma_ctxtable[idx]; 725 if (m) { 726 m_freem(m); 727 d->sbdma_ctxtable[idx] = NULL; 728 } 729 } 730 } 731 732 /* ********************************************************************* 733 * SBDMA_FILLRING(d) 734 * 735 * Fill the specified DMA channel (must be receive channel) 736 * with mbufs 737 * 738 * Input parameters: 739 * d - DMA channel 740 * 741 * Return value: 742 * nothing 743 ********************************************************************* */ 744 745 static void 746 sbdma_fillring(sbmacdma_t *d) 747 { 748 int idx; 749 750 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) 751 if (sbdma_add_rcvbuffer(d, NULL) != 0) 752 break; 753 } 754 755 /* ********************************************************************* 756 * SBDMA_RX_PROCESS(sc, d) 757 * 758 * Process "completed" receive buffers on the specified DMA channel. 759 * Note that this isn't really ideal for priority channels, since 760 * it processes all of the packets on a given channel before 761 * returning. 762 * 763 * Input parameters: 764 * sc - softc structure 765 * d - DMA channel context 766 * 767 * Return value: 768 * nothing 769 ********************************************************************* */ 770 771 static void 772 sbdma_rx_process(struct sbmac_softc *sc, sbmacdma_t *d) 773 { 774 int curidx; 775 int hwidx; 776 sbdmadscr_t *dsc; 777 struct mbuf *m; 778 struct ether_header *eh; 779 int len; 780 781 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 782 783 for (;;) { 784 /* 785 * figure out where we are (as an index) and where 786 * the hardware is (also as an index) 787 * 788 * This could be done faster if (for example) the 789 * descriptor table was page-aligned and contiguous in 790 * both virtual and physical memory -- you could then 791 * just compare the low-order bits of the virtual address 792 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 793 */ 794 795 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 796 hwidx = (int) 797 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 798 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 799 800 /* 801 * If they're the same, that means we've processed all 802 * of the descriptors up to (but not including) the one that 803 * the hardware is working on right now. 804 */ 805 806 if (curidx == hwidx) 807 break; 808 809 /* 810 * Otherwise, get the packet's mbuf ptr back 811 */ 812 813 dsc = &(d->sbdma_dscrtable[curidx]); 814 m = d->sbdma_ctxtable[curidx]; 815 d->sbdma_ctxtable[curidx] = NULL; 816 817 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 818 819 /* 820 * Check packet status. If good, process it. 821 * If not, silently drop it and put it back on the 822 * receive ring. 823 */ 824 825 if (! (dsc->dscr_a & M_DMA_ETHRX_BAD)) { 826 827 /* 828 * Set length into the packet 829 * XXX do we remove the CRC here? 830 */ 831 m->m_pkthdr.len = m->m_len = len; 832 833 ifp->if_ipackets++; 834 eh = mtod(m, struct ether_header *); 835 m->m_pkthdr.rcvif = ifp; 836 837 838 /* 839 * Add a new buffer to replace the old one. 840 */ 841 sbdma_add_rcvbuffer(d, NULL); 842 843 #if (NBPFILTER > 0) 844 /* 845 * Handle BPF listeners. Let the BPF user see the 846 * packet, but don't pass it up to the ether_input() 847 * layer unless it's a broadcast packet, multicast 848 * packet, matches our ethernet address or the 849 * interface is in promiscuous mode. 850 */ 851 852 if (ifp->if_bpf) 853 bpf_mtap(ifp->if_bpf, m); 854 #endif 855 /* 856 * Pass the buffer to the kernel 857 */ 858 (*ifp->if_input)(ifp, m); 859 } else { 860 /* 861 * Packet was mangled somehow. Just drop it and 862 * put it back on the receive ring. 863 */ 864 sbdma_add_rcvbuffer(d, m); 865 } 866 867 /* 868 * .. and advance to the next buffer. 869 */ 870 871 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 872 } 873 } 874 875 /* ********************************************************************* 876 * SBDMA_TX_PROCESS(sc, d) 877 * 878 * Process "completed" transmit buffers on the specified DMA channel. 879 * This is normally called within the interrupt service routine. 880 * Note that this isn't really ideal for priority channels, since 881 * it processes all of the packets on a given channel before 882 * returning. 883 * 884 * Input parameters: 885 * sc - softc structure 886 * d - DMA channel context 887 * 888 * Return value: 889 * nothing 890 ********************************************************************* */ 891 892 static void 893 sbdma_tx_process(struct sbmac_softc *sc, sbmacdma_t *d) 894 { 895 int curidx; 896 int hwidx; 897 sbdmadscr_t *dsc; 898 struct mbuf *m; 899 900 struct ifnet *ifp = &(sc->sc_ethercom.ec_if); 901 902 for (;;) { 903 /* 904 * figure out where we are (as an index) and where 905 * the hardware is (also as an index) 906 * 907 * This could be done faster if (for example) the 908 * descriptor table was page-aligned and contiguous in 909 * both virtual and physical memory -- you could then 910 * just compare the low-order bits of the virtual address 911 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 912 */ 913 914 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 915 hwidx = (int) 916 (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 917 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 918 919 /* 920 * If they're the same, that means we've processed all 921 * of the descriptors up to (but not including) the one that 922 * the hardware is working on right now. 923 */ 924 925 if (curidx == hwidx) 926 break; 927 928 /* 929 * Otherwise, get the packet's mbuf ptr back 930 */ 931 932 dsc = &(d->sbdma_dscrtable[curidx]); 933 m = d->sbdma_ctxtable[curidx]; 934 d->sbdma_ctxtable[curidx] = NULL; 935 936 /* 937 * for transmits, we just free buffers. 938 */ 939 940 m_freem(m); 941 942 /* 943 * .. and advance to the next buffer. 944 */ 945 946 d->sbdma_remptr = SBDMA_NEXTBUF(d, sbdma_remptr); 947 } 948 949 /* 950 * Decide what to set the IFF_OACTIVE bit in the interface to. 951 * It's supposed to reflect if the interface is actively 952 * transmitting, but that's really hard to do quickly. 953 */ 954 955 ifp->if_flags &= ~IFF_OACTIVE; 956 } 957 958 959 960 /* ********************************************************************* 961 * SBMAC_INITCTX(s) 962 * 963 * Initialize an Ethernet context structure - this is called 964 * once per MAC on the 1250. Memory is allocated here, so don't 965 * call it again from inside the ioctl routines that bring the 966 * interface up/down 967 * 968 * Input parameters: 969 * s - sbmac context structure 970 * 971 * Return value: 972 * 0 973 ********************************************************************* */ 974 975 static void 976 sbmac_initctx(struct sbmac_softc *s) 977 { 978 979 /* 980 * figure out the addresses of some ports 981 */ 982 983 s->sbm_macenable = PKSEG1(s->sbm_base + R_MAC_ENABLE); 984 s->sbm_maccfg = PKSEG1(s->sbm_base + R_MAC_CFG); 985 s->sbm_fifocfg = PKSEG1(s->sbm_base + R_MAC_THRSH_CFG); 986 s->sbm_framecfg = PKSEG1(s->sbm_base + R_MAC_FRAMECFG); 987 s->sbm_rxfilter = PKSEG1(s->sbm_base + R_MAC_ADFILTER_CFG); 988 s->sbm_isr = PKSEG1(s->sbm_base + R_MAC_STATUS); 989 s->sbm_imr = PKSEG1(s->sbm_base + R_MAC_INT_MASK); 990 991 /* 992 * Initialize the DMA channels. Right now, only one per MAC is used 993 * Note: Only do this _once_, as it allocates memory from the kernel! 994 */ 995 996 sbdma_initctx(&(s->sbm_txdma), s, 0, DMA_TX, SBMAC_MAX_TXDESCR); 997 sbdma_initctx(&(s->sbm_rxdma), s, 0, DMA_RX, SBMAC_MAX_RXDESCR); 998 999 /* 1000 * initial state is OFF 1001 */ 1002 1003 s->sbm_state = sbmac_state_off; 1004 1005 /* 1006 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC 1007 */ 1008 1009 s->sbm_speed = sbmac_speed_10; 1010 s->sbm_duplex = sbmac_duplex_half; 1011 s->sbm_fc = sbmac_fc_disabled; 1012 } 1013 1014 1015 /* ********************************************************************* 1016 * SBMAC_CHANNEL_START(s) 1017 * 1018 * Start packet processing on this MAC. 1019 * 1020 * Input parameters: 1021 * s - sbmac structure 1022 * 1023 * Return value: 1024 * nothing 1025 ********************************************************************* */ 1026 1027 static void 1028 sbmac_channel_start(struct sbmac_softc *s) 1029 { 1030 uint64_t reg; 1031 sbmac_port_t port; 1032 uint64_t cfg, fifo, framecfg; 1033 int idx; 1034 1035 /* 1036 * Don't do this if running 1037 */ 1038 1039 if (s->sbm_state == sbmac_state_on) 1040 return; 1041 1042 /* 1043 * Bring the controller out of reset, but leave it off. 1044 */ 1045 1046 SBMAC_WRITECSR(s->sbm_macenable, 0); 1047 1048 /* 1049 * Ignore all received packets 1050 */ 1051 1052 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1053 1054 /* 1055 * Calculate values for various control registers. 1056 */ 1057 1058 cfg = M_MAC_RETRY_EN | 1059 M_MAC_TX_HOLD_SOP_EN | 1060 V_MAC_TX_PAUSE_CNT_16K | 1061 M_MAC_AP_STAT_EN | 1062 M_MAC_SS_EN | 1063 0; 1064 1065 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1066 V_MAC_TX_RD_THRSH(4) | 1067 V_MAC_TX_RL_THRSH(4) | 1068 V_MAC_RX_PL_THRSH(4) | 1069 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ 1070 V_MAC_RX_PL_THRSH(4) | 1071 V_MAC_RX_RL_THRSH(8) | 1072 0; 1073 1074 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | 1075 V_MAC_MAX_FRAMESZ_DEFAULT | 1076 V_MAC_BACKOFF_SEL(1); 1077 1078 /* 1079 * Clear out the hash address map 1080 */ 1081 1082 port = PKSEG1(s->sbm_base + R_MAC_HASH_BASE); 1083 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1084 SBMAC_WRITECSR(port, 0); 1085 port += sizeof(uint64_t); 1086 } 1087 1088 /* 1089 * Clear out the exact-match table 1090 */ 1091 1092 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1093 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1094 SBMAC_WRITECSR(port, 0); 1095 port += sizeof(uint64_t); 1096 } 1097 1098 /* 1099 * Clear out the DMA Channel mapping table registers 1100 */ 1101 1102 port = PKSEG1(s->sbm_base + R_MAC_CHUP0_BASE); 1103 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1104 SBMAC_WRITECSR(port, 0); 1105 port += sizeof(uint64_t); 1106 } 1107 1108 port = PKSEG1(s->sbm_base + R_MAC_CHLO0_BASE); 1109 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1110 SBMAC_WRITECSR(port, 0); 1111 port += sizeof(uint64_t); 1112 } 1113 1114 /* 1115 * Program the hardware address. It goes into the hardware-address 1116 * register as well as the first filter register. 1117 */ 1118 1119 reg = sbmac_addr2reg(s->sbm_hwaddr); 1120 1121 port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); 1122 SBMAC_WRITECSR(port, reg); 1123 port = PKSEG1(s->sbm_base + R_MAC_ETHERNET_ADDR); 1124 SBMAC_WRITECSR(port, 0); // pass1 workaround 1125 1126 /* 1127 * Set the receive filter for no packets, and write values 1128 * to the various config registers 1129 */ 1130 1131 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1132 SBMAC_WRITECSR(s->sbm_imr, 0); 1133 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1134 SBMAC_WRITECSR(s->sbm_fifocfg, fifo); 1135 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1136 1137 /* 1138 * Initialize DMA channels (rings should be ok now) 1139 */ 1140 1141 sbdma_channel_start(&(s->sbm_rxdma)); 1142 sbdma_channel_start(&(s->sbm_txdma)); 1143 1144 /* 1145 * Configure the speed, duplex, and flow control 1146 */ 1147 1148 sbmac_set_speed(s, s->sbm_speed); 1149 sbmac_set_duplex(s, s->sbm_duplex, s->sbm_fc); 1150 1151 /* 1152 * Fill the receive ring 1153 */ 1154 1155 sbdma_fillring(&(s->sbm_rxdma)); 1156 1157 /* 1158 * Turn on the rest of the bits in the enable register 1159 */ 1160 1161 SBMAC_WRITECSR(s->sbm_macenable, M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0 | 1162 M_MAC_RX_ENABLE | M_MAC_TX_ENABLE); 1163 1164 1165 /* 1166 * Accept any kind of interrupt on TX and RX DMA channel 0 1167 */ 1168 SBMAC_WRITECSR(s->sbm_imr, 1169 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1170 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)); 1171 1172 /* 1173 * Enable receiving unicasts and broadcasts 1174 */ 1175 1176 SBMAC_WRITECSR(s->sbm_rxfilter, M_MAC_UCAST_EN | M_MAC_BCAST_EN); 1177 1178 /* 1179 * we're running now. 1180 */ 1181 1182 s->sbm_state = sbmac_state_on; 1183 s->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1184 1185 /* 1186 * Program multicast addresses 1187 */ 1188 1189 sbmac_setmulti(s); 1190 1191 /* 1192 * If channel was in promiscuous mode before, turn that on 1193 */ 1194 1195 if (s->sc_ethercom.ec_if.if_flags & IFF_PROMISC) 1196 sbmac_promiscuous_mode(s, 1); 1197 1198 /* 1199 * Turn on the once-per-second timer 1200 */ 1201 1202 callout_reset(&(s->sc_tick_ch), hz, sbmac_tick, s); 1203 } 1204 1205 1206 /* ********************************************************************* 1207 * SBMAC_CHANNEL_STOP(s) 1208 * 1209 * Stop packet processing on this MAC. 1210 * 1211 * Input parameters: 1212 * s - sbmac structure 1213 * 1214 * Return value: 1215 * nothing 1216 ********************************************************************* */ 1217 1218 static void sbmac_channel_stop(struct sbmac_softc *s) 1219 { 1220 uint64_t ctl; 1221 1222 /* don't do this if already stopped */ 1223 1224 if (s->sbm_state == sbmac_state_off) return; 1225 1226 /* don't accept any packets, disable all interrupts */ 1227 1228 SBMAC_WRITECSR(s->sbm_rxfilter, 0); 1229 SBMAC_WRITECSR(s->sbm_imr, 0); 1230 1231 /* Turn off ticker */ 1232 1233 callout_stop(&(s->sc_tick_ch)); 1234 1235 /* turn off receiver and transmitter */ 1236 1237 ctl = SBMAC_READCSR(s->sbm_macenable); 1238 ctl &= ~(M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0); 1239 SBMAC_WRITECSR(s->sbm_macenable, ctl); 1240 1241 /* We're stopped now. */ 1242 1243 s->sbm_state = sbmac_state_off; 1244 s->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1245 1246 /* Empty the receive and transmit rings */ 1247 1248 sbdma_emptyring(&(s->sbm_rxdma)); 1249 sbdma_emptyring(&(s->sbm_txdma)); 1250 1251 } 1252 1253 /* ********************************************************************* 1254 * SBMAC_SET_CHANNEL_STATE(state) 1255 * 1256 * Set the channel's state ON or OFF 1257 * 1258 * Input parameters: 1259 * state - new state 1260 * 1261 * Return value: 1262 * old state 1263 ********************************************************************* */ 1264 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc, 1265 sbmac_state_t state) 1266 { 1267 sbmac_state_t oldstate = sc->sbm_state; 1268 1269 /* 1270 * If same as previous state, return 1271 */ 1272 1273 if (state == oldstate) { 1274 return oldstate; 1275 } 1276 1277 /* 1278 * If new state is ON, turn channel on 1279 */ 1280 1281 if (state == sbmac_state_on) { 1282 sbmac_channel_start(sc); 1283 } 1284 else { 1285 sbmac_channel_stop(sc); 1286 } 1287 1288 /* 1289 * Return previous state 1290 */ 1291 1292 return oldstate; 1293 } 1294 1295 1296 /* ********************************************************************* 1297 * SBMAC_PROMISCUOUS_MODE(sc, onoff) 1298 * 1299 * Turn on or off promiscuous mode 1300 * 1301 * Input parameters: 1302 * sc - softc 1303 * onoff - 1 to turn on, 0 to turn off 1304 * 1305 * Return value: 1306 * nothing 1307 ********************************************************************* */ 1308 1309 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff) 1310 { 1311 uint64_t reg; 1312 1313 if (sc->sbm_state != sbmac_state_on) return; 1314 1315 if (onoff) { 1316 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1317 reg |= M_MAC_ALLPKT_EN; 1318 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1319 } 1320 else { 1321 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1322 reg &= ~M_MAC_ALLPKT_EN; 1323 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1324 } 1325 } 1326 1327 1328 1329 /* ********************************************************************* 1330 * SBMAC_INIT_AND_START(sc) 1331 * 1332 * Stop the channel and restart it. This is generally used 1333 * when we have to do something to the channel that requires 1334 * a swift kick. 1335 * 1336 * Input parameters: 1337 * sc - softc 1338 ********************************************************************* */ 1339 1340 static void sbmac_init_and_start(struct sbmac_softc *sc) 1341 { 1342 int s; 1343 1344 s = splnet(); 1345 1346 mii_pollstat(&sc->sc_mii); /* poll phy for current speed */ 1347 sbmac_mii_statchg((struct device *) sc); /* set state to new speed */ 1348 sbmac_set_channel_state(sc, sbmac_state_on); 1349 1350 splx(s); 1351 } 1352 1353 /* ********************************************************************* 1354 * SBMAC_ADDR2REG(ptr) 1355 * 1356 * Convert six bytes into the 64-bit register value that 1357 * we typically write into the SBMAC's address/mcast registers 1358 * 1359 * Input parameters: 1360 * ptr - pointer to 6 bytes 1361 * 1362 * Return value: 1363 * register value 1364 ********************************************************************* */ 1365 1366 static uint64_t sbmac_addr2reg(u_char *ptr) 1367 { 1368 uint64_t reg = 0; 1369 1370 ptr += 6; 1371 1372 reg |= (uint64_t) *(--ptr); 1373 reg <<= 8; 1374 reg |= (uint64_t) *(--ptr); 1375 reg <<= 8; 1376 reg |= (uint64_t) *(--ptr); 1377 reg <<= 8; 1378 reg |= (uint64_t) *(--ptr); 1379 reg <<= 8; 1380 reg |= (uint64_t) *(--ptr); 1381 reg <<= 8; 1382 reg |= (uint64_t) *(--ptr); 1383 1384 return reg; 1385 } 1386 1387 1388 /* ********************************************************************* 1389 * SBMAC_SET_SPEED(s, speed) 1390 * 1391 * Configure LAN speed for the specified MAC. 1392 * Warning: must be called when MAC is off! 1393 * 1394 * Input parameters: 1395 * s - sbmac structure 1396 * speed - speed to set MAC to (see sbmac_speed_t enum) 1397 * 1398 * Return value: 1399 * 1 if successful 1400 * 0 indicates invalid parameters 1401 ********************************************************************* */ 1402 1403 static int sbmac_set_speed(struct sbmac_softc *s, sbmac_speed_t speed) 1404 { 1405 uint64_t cfg; 1406 uint64_t framecfg; 1407 1408 /* 1409 * Save new current values 1410 */ 1411 1412 s->sbm_speed = speed; 1413 1414 if (s->sbm_state != sbmac_state_off) 1415 panic("sbmac_set_speed while MAC not off"); 1416 1417 /* 1418 * Read current register values 1419 */ 1420 1421 cfg = SBMAC_READCSR(s->sbm_maccfg); 1422 framecfg = SBMAC_READCSR(s->sbm_framecfg); 1423 1424 /* 1425 * Mask out the stuff we want to change 1426 */ 1427 1428 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1429 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1430 M_MAC_SLOT_SIZE); 1431 1432 /* 1433 * Now add in the new bits 1434 */ 1435 1436 switch (speed) { 1437 case sbmac_speed_10: 1438 framecfg |= V_MAC_IFG_RX_10 | 1439 V_MAC_IFG_TX_10 | 1440 K_MAC_IFG_THRSH_10 | 1441 V_MAC_SLOT_SIZE_10; 1442 cfg |= V_MAC_SPEED_SEL_10MBPS; 1443 break; 1444 1445 case sbmac_speed_100: 1446 framecfg |= V_MAC_IFG_RX_100 | 1447 V_MAC_IFG_TX_100 | 1448 V_MAC_IFG_THRSH_100 | 1449 V_MAC_SLOT_SIZE_100; 1450 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1451 break; 1452 1453 case sbmac_speed_1000: 1454 framecfg |= V_MAC_IFG_RX_1000 | 1455 V_MAC_IFG_TX_1000 | 1456 V_MAC_IFG_THRSH_1000 | 1457 V_MAC_SLOT_SIZE_1000; 1458 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1459 break; 1460 1461 case sbmac_speed_auto: /* XXX not implemented */ 1462 /* fall through */ 1463 default: 1464 return 0; 1465 } 1466 1467 /* 1468 * Send the bits back to the hardware 1469 */ 1470 1471 SBMAC_WRITECSR(s->sbm_framecfg, framecfg); 1472 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1473 1474 return 1; 1475 1476 } 1477 1478 /* ********************************************************************* 1479 * SBMAC_SET_DUPLEX(s, duplex, fc) 1480 * 1481 * Set Ethernet duplex and flow control options for this MAC 1482 * Warning: must be called when MAC is off! 1483 * 1484 * Input parameters: 1485 * s - sbmac structure 1486 * duplex - duplex setting (see sbmac_duplex_t) 1487 * fc - flow control setting (see sbmac_fc_t) 1488 * 1489 * Return value: 1490 * 1 if ok 1491 * 0 if an invalid parameter combination was specified 1492 ********************************************************************* */ 1493 1494 static int sbmac_set_duplex(struct sbmac_softc *s, sbmac_duplex_t duplex, sbmac_fc_t fc) 1495 { 1496 uint64_t cfg; 1497 1498 /* 1499 * Save new current values 1500 */ 1501 1502 s->sbm_duplex = duplex; 1503 s->sbm_fc = fc; 1504 1505 if (s->sbm_state != sbmac_state_off) 1506 panic("sbmac_set_duplex while MAC not off"); 1507 1508 /* 1509 * Read current register values 1510 */ 1511 1512 cfg = SBMAC_READCSR(s->sbm_maccfg); 1513 1514 /* 1515 * Mask off the stuff we're about to change 1516 */ 1517 1518 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1519 1520 1521 switch (duplex) { 1522 case sbmac_duplex_half: 1523 switch (fc) { 1524 case sbmac_fc_disabled: 1525 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1526 break; 1527 1528 case sbmac_fc_collision: 1529 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1530 break; 1531 1532 case sbmac_fc_carrier: 1533 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1534 break; 1535 1536 case sbmac_fc_auto: /* XXX not implemented */ 1537 /* fall through */ 1538 case sbmac_fc_frame: /* not valid in half duplex */ 1539 default: /* invalid selection */ 1540 panic("%s: invalid half duplex fc selection %d\n", 1541 s->sc_dev.dv_xname, fc); 1542 return 0; 1543 } 1544 break; 1545 1546 case sbmac_duplex_full: 1547 switch (fc) { 1548 case sbmac_fc_disabled: 1549 cfg |= V_MAC_FC_CMD_DISABLED; 1550 break; 1551 1552 case sbmac_fc_frame: 1553 cfg |= V_MAC_FC_CMD_ENABLED; 1554 break; 1555 1556 case sbmac_fc_collision: /* not valid in full duplex */ 1557 case sbmac_fc_carrier: /* not valid in full duplex */ 1558 case sbmac_fc_auto: /* XXX not implemented */ 1559 /* fall through */ 1560 default: 1561 panic("%s: invalid full duplex fc selection %d\n", 1562 s->sc_dev.dv_xname, fc); 1563 return 0; 1564 } 1565 break; 1566 1567 default: 1568 /* fall through */ 1569 case sbmac_duplex_auto: 1570 panic("%s: bad duplex %d\n", s->sc_dev.dv_xname, duplex); 1571 /* XXX not implemented */ 1572 break; 1573 } 1574 1575 /* 1576 * Send the bits back to the hardware 1577 */ 1578 1579 SBMAC_WRITECSR(s->sbm_maccfg, cfg); 1580 1581 return 1; 1582 } 1583 1584 1585 1586 1587 /* ********************************************************************* 1588 * SBMAC_INTR() 1589 * 1590 * Interrupt handler for MAC interrupts 1591 * 1592 * Input parameters: 1593 * MAC structure 1594 * 1595 * Return value: 1596 * nothing 1597 ********************************************************************* */ 1598 /* ARGSUSED */ 1599 static void 1600 sbmac_intr(void *xsc, uint32_t status, uint32_t pc) 1601 { 1602 struct sbmac_softc *sc = (struct sbmac_softc *) xsc; 1603 uint64_t isr; 1604 1605 for (;;) { 1606 1607 /* 1608 * Read the ISR (this clears the bits in the real register) 1609 */ 1610 1611 isr = SBMAC_READCSR(sc->sbm_isr); 1612 1613 if (isr == 0) 1614 break; 1615 1616 /* 1617 * Transmits on channel 0 1618 */ 1619 1620 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) 1621 sbdma_tx_process(sc, &(sc->sbm_txdma)); 1622 1623 /* 1624 * Receives on channel 0 1625 */ 1626 1627 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) 1628 sbdma_rx_process(sc, &(sc->sbm_rxdma)); 1629 } 1630 } 1631 1632 1633 /* ********************************************************************* 1634 * SBMAC_START(ifp) 1635 * 1636 * Start output on the specified interface. Basically, we 1637 * queue as many buffers as we can until the ring fills up, or 1638 * we run off the end of the queue, whichever comes first. 1639 * 1640 * Input parameters: 1641 * ifp - interface 1642 * 1643 * Return value: 1644 * nothing 1645 ********************************************************************* */ 1646 static void sbmac_start(struct ifnet *ifp) 1647 { 1648 struct sbmac_softc *sc; 1649 struct mbuf *m_head = NULL; 1650 int rv; 1651 1652 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1653 return; 1654 1655 sc = ifp->if_softc; 1656 1657 for (;;) { 1658 1659 IF_DEQUEUE(&ifp->if_snd, m_head); 1660 if (m_head == NULL) break; 1661 1662 /* 1663 * Put the buffer on the transmit ring. If we 1664 * don't have room, set the OACTIVE flag and wait 1665 * for the NIC to drain the ring. 1666 */ 1667 1668 rv = sbdma_add_txbuffer(&(sc->sbm_txdma), m_head); 1669 1670 if (rv == 0) { 1671 /* 1672 * If there's a BPF listener, bounce a copy of this frame 1673 * to it. 1674 */ 1675 #if (NBPFILTER > 0) 1676 if (ifp->if_bpf) { 1677 bpf_mtap(ifp->if_bpf, m_head); 1678 } 1679 #endif 1680 m_freem(m_head); 1681 } else { 1682 IF_PREPEND(&ifp->if_snd, m_head); 1683 ifp->if_flags |= IFF_OACTIVE; 1684 break; 1685 } 1686 } 1687 } 1688 1689 /* ********************************************************************* 1690 * SBMAC_SETMULTI(sc) 1691 * 1692 * Reprogram the multicast table into the hardware, given 1693 * the list of multicasts associated with the interface 1694 * structure. 1695 * 1696 * Input parameters: 1697 * sc - softc 1698 * 1699 * Return value: 1700 * nothing 1701 ********************************************************************* */ 1702 1703 static void sbmac_setmulti(struct sbmac_softc *sc) 1704 { 1705 struct ifnet *ifp; 1706 uint64_t reg; 1707 sbmac_port_t port; 1708 int idx; 1709 struct ether_multi *enm; 1710 struct ether_multistep step; 1711 1712 ifp = &sc->sc_ethercom.ec_if; 1713 1714 /* 1715 * Clear out entire multicast table. We do this by nuking 1716 * the entire hash table and all the direct matches except 1717 * the first one, which is used for our station address 1718 */ 1719 1720 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 1721 port = PKSEG1(sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1722 SBMAC_WRITECSR(port, 0); 1723 } 1724 1725 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1726 port = PKSEG1(sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t))); 1727 SBMAC_WRITECSR(port, 0); 1728 } 1729 1730 /* 1731 * Clear the filter to say we don't want any multicasts. 1732 */ 1733 1734 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1735 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1736 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1737 1738 if (ifp->if_flags & IFF_ALLMULTI) { 1739 /* 1740 * Enable ALL multicasts. Do this by inverting the 1741 * multicast enable bit. 1742 */ 1743 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1744 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 1745 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1746 return; 1747 } 1748 1749 /* 1750 * Progam new multicast entries. For now, only use the 1751 * perfect filter. In the future we'll need to use the 1752 * hash filter if the perfect filter overflows 1753 */ 1754 1755 /* XXX only using perfect filter for now, need to use hash 1756 * XXX if the table overflows */ 1757 1758 idx = 1; /* skip station address */ 1759 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1760 while ((enm != NULL) && (idx < MAC_ADDR_COUNT)) { 1761 reg = sbmac_addr2reg(enm->enm_addrlo); 1762 port = PKSEG1(sc->sbm_base + 1763 R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); 1764 SBMAC_WRITECSR(port, reg); 1765 idx++; 1766 ETHER_NEXT_MULTI(step, enm); 1767 } 1768 1769 /* 1770 * Enable the "accept multicast bits" if we programmed at least one 1771 * multicast. 1772 */ 1773 1774 if (idx > 1) { 1775 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1776 reg |= M_MAC_MCAST_EN; 1777 SBMAC_WRITECSR(sc->sbm_rxfilter, reg); 1778 } 1779 } 1780 1781 1782 /* ********************************************************************* 1783 * SBMAC_ETHER_IOCTL(ifp, cmd, data) 1784 * 1785 * Generic IOCTL requests for this interface. The basic 1786 * stuff is handled here for bringing the interface up, 1787 * handling multicasts, etc. 1788 * 1789 * Input parameters: 1790 * ifp - interface structure 1791 * cmd - command code 1792 * data - pointer to data 1793 * 1794 * Return value: 1795 * return value (0 is success) 1796 ********************************************************************* */ 1797 1798 static int sbmac_ether_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1799 { 1800 struct ifaddr *ifa = (struct ifaddr *) data; 1801 struct sbmac_softc *sc = ifp->if_softc; 1802 1803 switch (cmd) { 1804 case SIOCSIFADDR: 1805 ifp->if_flags |= IFF_UP; 1806 1807 switch (ifa->ifa_addr->sa_family) { 1808 #ifdef INET 1809 case AF_INET: 1810 sbmac_init_and_start(sc); 1811 arp_ifinit(ifp, ifa); 1812 break; 1813 #endif 1814 #ifdef NS 1815 case AF_NS: 1816 { 1817 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1818 1819 if (ns_nullhost(*ina)) 1820 ina->x_host = *(union ns_host *) 1821 LLADDR(ifp->if_sadl); 1822 else 1823 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1824 ifp->if_addrlen); 1825 /* Set new address. */ 1826 sbmac_init_and_start(sc); 1827 break; 1828 } 1829 #endif 1830 default: 1831 sbmac_init_and_start(sc); 1832 break; 1833 } 1834 break; 1835 1836 default: 1837 return (EINVAL); 1838 } 1839 1840 return (0); 1841 } 1842 1843 1844 /* ********************************************************************* 1845 * SBMAC_IOCTL(ifp, command, data) 1846 * 1847 * Main IOCTL handler - dispatches to other IOCTLs for various 1848 * types of requests. 1849 * 1850 * Input parameters: 1851 * ifp - interface pointer 1852 * command - command code 1853 * data - pointer to argument data 1854 * 1855 * Return value: 1856 * 0 if ok 1857 * else error code 1858 ********************************************************************* */ 1859 1860 static int sbmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1861 { 1862 struct sbmac_softc *sc = ifp->if_softc; 1863 struct ifreq *ifr = (struct ifreq *) data; 1864 int s, error = 0; 1865 1866 s = splnet(); 1867 1868 switch(command) { 1869 case SIOCSIFADDR: 1870 case SIOCGIFADDR: 1871 error = sbmac_ether_ioctl(ifp, command, data); 1872 break; 1873 case SIOCSIFMTU: 1874 if (ifr->ifr_mtu > 1518) /* XXX */ 1875 error = EINVAL; 1876 else { 1877 ifp->if_mtu = ifr->ifr_mtu; 1878 /* XXX Program new MTU here */ 1879 } 1880 break; 1881 case SIOCSIFFLAGS: 1882 if (ifp->if_flags & IFF_UP) { 1883 /* 1884 * If only the state of the PROMISC flag changed, 1885 * just tweak the hardware registers. 1886 */ 1887 if ((ifp->if_flags & IFF_RUNNING) && 1888 (ifp->if_flags & IFF_PROMISC)) { 1889 /* turn on promiscuous mode */ 1890 sbmac_promiscuous_mode(sc, 1); 1891 } 1892 else if (ifp->if_flags & IFF_RUNNING && 1893 !(ifp->if_flags & IFF_PROMISC)) { 1894 /* turn off promiscuous mode */ 1895 sbmac_promiscuous_mode(sc, 0); 1896 } 1897 else { 1898 sbmac_set_channel_state(sc, sbmac_state_on); 1899 } 1900 } 1901 else { 1902 if (ifp->if_flags & IFF_RUNNING) { 1903 sbmac_set_channel_state(sc, sbmac_state_off); 1904 } 1905 } 1906 1907 sc->sbm_if_flags = ifp->if_flags; 1908 error = 0; 1909 break; 1910 1911 case SIOCADDMULTI: 1912 case SIOCDELMULTI: 1913 if (ifp->if_flags & IFF_RUNNING) { 1914 sbmac_setmulti(sc); 1915 error = 0; 1916 } 1917 break; 1918 case SIOCSIFMEDIA: 1919 case SIOCGIFMEDIA: 1920 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1921 break; 1922 default: 1923 error = EINVAL; 1924 break; 1925 } 1926 1927 (void)splx(s); 1928 1929 return(error); 1930 } 1931 1932 1933 /* ********************************************************************* 1934 * SBMAC_IFMEDIA_UPD(ifp) 1935 * 1936 * Configure an appropriate media type for this interface, 1937 * given the data in the interface structure 1938 * 1939 * Input parameters: 1940 * ifp - interface 1941 * 1942 * Return value: 1943 * 0 if ok 1944 * else error code 1945 ********************************************************************* */ 1946 1947 static int sbmac_mediachange(struct ifnet *ifp) 1948 { 1949 struct sbmac_softc *sc = ifp->if_softc; 1950 1951 if (ifp->if_flags & IFF_UP) 1952 mii_mediachg(&sc->sc_mii); 1953 return(0); 1954 } 1955 1956 /* ********************************************************************* 1957 * SBMAC_IFMEDIA_STS(ifp, ifmr) 1958 * 1959 * Report current media status (used by ifconfig, for example) 1960 * 1961 * Input parameters: 1962 * ifp - interface structure 1963 * ifmr - media request structure 1964 * 1965 * Return value: 1966 * nothing 1967 ********************************************************************* */ 1968 1969 static void sbmac_mediastatus(struct ifnet *ifp, struct ifmediareq *req) 1970 { 1971 struct sbmac_softc *sc = ifp->if_softc; 1972 1973 mii_pollstat(&sc->sc_mii); 1974 req->ifm_status = sc->sc_mii.mii_media_status; 1975 req->ifm_active = sc->sc_mii.mii_media_active; 1976 } 1977 1978 1979 /* ********************************************************************* 1980 * SBMAC_WATCHDOG(ifp) 1981 * 1982 * Called periodically to make sure we're still happy. 1983 * 1984 * Input parameters: 1985 * ifp - interface structure 1986 * 1987 * Return value: 1988 * nothing 1989 ********************************************************************* */ 1990 1991 static void sbmac_watchdog(struct ifnet *ifp) 1992 { 1993 /* XXX do something */ 1994 } 1995 1996 /* 1997 * One second timer, used to tick MII. 1998 */ 1999 static void sbmac_tick(void *arg) 2000 { 2001 struct sbmac_softc *sc = arg; 2002 int s; 2003 2004 s = splnet(); 2005 mii_tick(&sc->sc_mii); 2006 splx(s); 2007 2008 callout_reset(&sc->sc_tick_ch, hz, sbmac_tick, sc); 2009 } 2010 2011 2012 /* ********************************************************************* 2013 * SBMAC_MATCH(parent, match, aux) 2014 * 2015 * Part of the config process - see if this device matches the 2016 * info about what we expect to find on the bus. 2017 * 2018 * Input parameters: 2019 * parent - parent bus structure 2020 * match - 2021 * aux - bus-specific args 2022 * 2023 * Return value: 2024 * 1 if we match 2025 * 0 if we don't match 2026 ********************************************************************* */ 2027 2028 static int sbmac_match(struct device *parent, struct cfdata *match, void *aux) 2029 { 2030 struct sbobio_attach_args *sap = aux; 2031 2032 /* 2033 * Make sure it's a MAC 2034 */ 2035 2036 if (sap->sa_locs.sa_type != SBOBIO_DEVTYPE_MAC) { 2037 return 0; 2038 } 2039 2040 /* 2041 * Yup, it is. 2042 */ 2043 2044 return 1; 2045 } 2046 2047 2048 /* ********************************************************************* 2049 * SBMAC_PARSE_XDIGIT(str) 2050 * 2051 * Parse a hex digit, returning its value 2052 * 2053 * Input parameters: 2054 * str - character 2055 * 2056 * Return value: 2057 * hex value, or -1 if invalid 2058 ********************************************************************* */ 2059 2060 static int sbmac_parse_xdigit(char str) 2061 { 2062 int digit; 2063 2064 if ((str >= '0') && (str <= '9')) digit = str - '0'; 2065 else if ((str >= 'a') && (str <= 'f')) digit = str - 'a' + 10; 2066 else if ((str >= 'A') && (str <= 'F')) digit = str - 'A' + 10; 2067 else return -1; 2068 2069 return digit; 2070 } 2071 2072 /* ********************************************************************* 2073 * SBMAC_PARSE_HWADDR(str, hwaddr) 2074 * 2075 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte 2076 * Ethernet address. 2077 * 2078 * Input parameters: 2079 * str - string 2080 * hwaddr - pointer to hardware address 2081 * 2082 * Return value: 2083 * 0 if ok, else -1 2084 ********************************************************************* */ 2085 2086 static int sbmac_parse_hwaddr(char *str, u_char *hwaddr) 2087 { 2088 int digit1, digit2; 2089 int idx = 6; 2090 2091 while (*str && (idx > 0)) { 2092 digit1 = sbmac_parse_xdigit(*str); 2093 if (digit1 < 0) return -1; 2094 str++; 2095 if (!*str) return -1; 2096 2097 if ((*str == ':') || (*str == '-')) { 2098 digit2 = digit1; 2099 digit1 = 0; 2100 } 2101 else { 2102 digit2 = sbmac_parse_xdigit(*str); 2103 if (digit2 < 0) return -1; 2104 str++; 2105 } 2106 2107 *hwaddr++ = (digit1 << 4) | digit2; 2108 idx--; 2109 2110 if (*str == '-') str++; 2111 if (*str == ':') str++; 2112 } 2113 return 0; 2114 } 2115 2116 /* ********************************************************************* 2117 * SBMAC_ATTACH(parent, self, aux) 2118 * 2119 * Attach routine - init hardware and hook ourselves into NetBSD. 2120 * 2121 * Input parameters: 2122 * parent - parent bus device 2123 * self - our softc 2124 * aux - attach data 2125 * 2126 * Return value: 2127 * nothing 2128 ********************************************************************* */ 2129 2130 static void sbmac_attach(struct device *parent, struct device *self, void *aux) 2131 { 2132 struct ifnet *ifp; 2133 struct sbmac_softc *sc; 2134 struct sbobio_attach_args *sap = aux; 2135 u_char *eaddr; 2136 static int unit = 0; /* XXX */ 2137 uint64_t ea_reg; 2138 int idx; 2139 2140 sc = (struct sbmac_softc *)self; 2141 2142 /* Determine controller base address */ 2143 2144 sc->sbm_base = (sbmac_port_t) sap->sa_base + sap->sa_locs.sa_offset; 2145 2146 eaddr = sc->sbm_hwaddr; 2147 2148 /* 2149 * Initialize context (get pointers to registers and stuff), then 2150 * allocate the memory for the descriptor tables. 2151 */ 2152 2153 sbmac_initctx(sc); 2154 2155 callout_init(&(sc->sc_tick_ch)); 2156 2157 /* 2158 * Read the ethernet address. The firwmare left this programmed 2159 * for us in the ethernet address register for each mac. 2160 */ 2161 2162 ea_reg = SBMAC_READCSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR)); 2163 for (idx = 0; idx < 6; idx++) { 2164 eaddr[idx] = (uint8_t) (ea_reg & 0xFF); 2165 ea_reg >>= 8; 2166 } 2167 2168 #define SBMAC_DEFAULT_HWADDR "40:00:00:00:01:00" 2169 if (eaddr[0] == 0 && eaddr[1] == 0 && eaddr[2] == 0 && 2170 eaddr[3] == 0 && eaddr[4] == 0 && eaddr[5] == 0) { 2171 sbmac_parse_hwaddr(SBMAC_DEFAULT_HWADDR, eaddr); 2172 eaddr[5] = unit; 2173 } 2174 2175 #ifdef SBMAC_ETH0_HWADDR 2176 if (unit == 0) sbmac_parse_hwaddr(SBMAC_ETH0_HWADDR, eaddr); 2177 #endif 2178 #ifdef SBMAC_ETH1_HWADDR 2179 if (unit == 1) sbmac_parse_hwaddr(SBMAC_ETH1_HWADDR, eaddr); 2180 #endif 2181 #ifdef SBMAC_ETH2_HWADDR 2182 if (unit == 2) sbmac_parse_hwaddr(SBMAC_ETH2_HWADDR, eaddr); 2183 #endif 2184 unit++; 2185 2186 /* 2187 * Display Ethernet address (this is called during the config process 2188 * so we need to finish off the config message that was being displayed) 2189 */ 2190 printf(": Ethernet\n%s: Ethernet address: %s\n", self->dv_xname, 2191 ether_sprintf(eaddr)); 2192 2193 2194 /* 2195 * Set up ifnet structure 2196 */ 2197 2198 ifp = &sc->sc_ethercom.ec_if; 2199 ifp->if_softc = sc; 2200 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 2201 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | IFF_NOTRAILERS; 2202 ifp->if_ioctl = sbmac_ioctl; 2203 ifp->if_start = sbmac_start; 2204 ifp->if_watchdog = sbmac_watchdog; 2205 ifp->if_snd.ifq_maxlen = SBMAC_MAX_TXDESCR - 1; 2206 2207 /* 2208 * Set up ifmedia support. 2209 */ 2210 2211 /* 2212 * Initialize MII/media info. 2213 */ 2214 sc->sc_mii.mii_ifp = ifp; 2215 sc->sc_mii.mii_readreg = sbmac_mii_readreg; 2216 sc->sc_mii.mii_writereg = sbmac_mii_writereg; 2217 sc->sc_mii.mii_statchg = sbmac_mii_statchg; 2218 ifmedia_init(&sc->sc_mii.mii_media, 0, sbmac_mediachange, 2219 sbmac_mediastatus); 2220 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2221 MII_OFFSET_ANY, 0); 2222 2223 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2224 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2225 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2226 } 2227 else { 2228 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2229 } 2230 2231 2232 /* 2233 * map/route interrupt 2234 */ 2235 2236 sc->sbm_intrhand = cpu_intr_establish(sap->sa_locs.sa_intr[0], 2237 IPL_NET, sbmac_intr, sc); 2238 2239 /* 2240 * Call MI attach routines. 2241 */ 2242 if_attach(ifp); 2243 ether_ifattach(ifp, eaddr); 2244 } 2245