1 /* $NetBSD: sbtimer.c,v 1.17 2011/02/01 06:13:08 matt Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. The "Broadcom Corporation" name may not be 19 * used to endorse or promote products derived from this software 20 * without the prior written permission of Broadcom Corporation. 21 * 22 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 25 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 26 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 27 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 32 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sbtimer.c,v 1.17 2011/02/01 06:13:08 matt Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/device.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 43 #include <mips/locore.h> 44 45 #include <mips/sibyte/include/sb1250_regs.h> 46 #include <mips/sibyte/include/sb1250_scd.h> 47 #include <mips/sibyte/dev/sbscdvar.h> 48 49 struct sbtimer_softc { 50 device_t sc_dev; 51 void *sc_intrhand; 52 int sc_flags; 53 void *sc_addr_icnt, *sc_addr_cnt, *sc_addr_cfg; 54 }; 55 #define SBTIMER_CLOCK 1 56 #define SBTIMER_STATCLOCK 2 57 58 #define READ_REG(rp) (mips3_ld((volatile uint64_t *)(rp))) 59 #define WRITE_REG(rp, val) (mips3_sd((volatile uint64_t *)(rp), (val))) 60 61 static int sbtimer_match(device_t, cfdata_t, void *); 62 static void sbtimer_attach(device_t, device_t, void *); 63 64 CFATTACH_DECL_NEW(sbtimer, sizeof(struct sbtimer_softc), 65 sbtimer_match, sbtimer_attach, NULL, NULL); 66 67 static void sbtimer_clockintr(void *arg, uint32_t status, vaddr_t pc); 68 static void sbtimer_statclockintr(void *arg, uint32_t status, vaddr_t pc); 69 static void sbtimer_miscintr(void *arg, uint32_t status, vaddr_t pc); 70 71 static void sbtimer_clock_init(void *arg); 72 73 static int 74 sbtimer_match(device_t parent, cfdata_t match, void *aux) 75 { 76 struct sbscd_attach_args *sap = aux; 77 78 if (sap->sa_locs.sa_type != SBSCD_DEVTYPE_TIMER) 79 return (0); 80 81 return 1; 82 } 83 84 static void 85 sbtimer_attach(device_t parent, device_t self, void *aux) 86 { 87 struct sbscd_attach_args *sa = aux; 88 struct sbtimer_softc *sc = device_private(self); 89 void (*fun)(void *, uint32_t, vaddr_t); 90 int ipl; 91 const char *comment = ""; 92 93 sc->sc_dev = self; 94 95 sc->sc_flags = device_cfdata(sc->sc_dev)->cf_flags; 96 sc->sc_addr_icnt = (uint64_t *)MIPS_PHYS_TO_KSEG1(sa->sa_locs.sa_addr + 97 R_SCD_TIMER_INIT); 98 sc->sc_addr_cnt = (uint64_t *)MIPS_PHYS_TO_KSEG1(sa->sa_locs.sa_addr + 99 R_SCD_TIMER_CNT); 100 sc->sc_addr_cfg = (uint64_t *)MIPS_PHYS_TO_KSEG1(sa->sa_locs.sa_addr + 101 R_SCD_TIMER_CFG); 102 103 aprint_normal(": "); 104 if ((sc->sc_flags & SBTIMER_CLOCK) != 0) { 105 ipl = IPL_CLOCK; 106 fun = sbtimer_clockintr; 107 108 if (system_set_clockfns(sc, sbtimer_clock_init)) { 109 /* not really the clock */ 110 sc->sc_flags &= ~SBTIMER_CLOCK; 111 comment = " (not system timer)"; 112 goto not_really; 113 } 114 aprint_normal("system timer"); 115 } else if ((sc->sc_flags & SBTIMER_STATCLOCK) != 0) { 116 ipl = IPL_HIGH; 117 fun = sbtimer_statclockintr; 118 119 /* XXX make sure it's the statclock */ 120 if (1) { 121 /* not really the statclock */ 122 sc->sc_flags &= ~SBTIMER_STATCLOCK; 123 comment = " (not system statistics timer)"; 124 goto not_really; 125 } 126 aprint_normal("system statistics timer"); 127 } else { 128 not_really: 129 ipl = IPL_BIO; /* XXX -- pretty low */ 130 fun = sbtimer_miscintr; 131 aprint_normal("general-purpose timer%s", comment); 132 } 133 aprint_normal("\n"); 134 135 /* clear intr & disable timer. */ 136 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */ 137 138 sc->sc_intrhand = cpu_intr_establish(sa->sa_locs.sa_intr[0], ipl, 139 fun, sc); 140 } 141 142 static void 143 sbtimer_clock_init(void *arg) 144 { 145 struct sbtimer_softc *sc = arg; 146 147 if ((1000000 % hz) == 0) { 148 aprint_normal_dev(sc->sc_dev, "%dHz system timer\n", hz); 149 } else { 150 aprint_error_dev(sc->sc_dev, 151 "cannot get %dHz clock; using 1000Hz\n", hz); 152 hz = 1000; 153 tick = 1000000 / hz; 154 } 155 156 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */ 157 if (G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG))) == 0) { 158 aprint_debug_dev(sc->sc_dev, 159 "PLL_DIV == 0; speeding up clock ticks for simulator\n"); 160 WRITE_REG(sc->sc_addr_icnt, (tick/100) - 1); /* XXX */ 161 } else { 162 WRITE_REG(sc->sc_addr_icnt, tick - 1); /* XXX */ 163 } 164 WRITE_REG(sc->sc_addr_cfg, 0x03); /* XXX */ 165 } 166 167 static void 168 sbtimer_clockintr(void *arg, uint32_t status, vaddr_t pc) 169 { 170 struct sbtimer_softc *sc = arg; 171 struct clockframe cf; 172 173 /* clear interrupt, but leave timer enabled and in repeating mode */ 174 WRITE_REG(sc->sc_addr_cfg, 0x03); /* XXX */ 175 176 cf.pc = pc; 177 cf.sr = status; 178 179 hardclock(&cf); 180 181 /* 182 * We never want a CPU core clock interrupt, so adjust the CP0 183 * compare register to just before the CP0 clock register's value 184 * each time. 185 */ 186 mips3_cp0_compare_write(mips3_cp0_count_read() - 1); 187 } 188 189 static void 190 sbtimer_statclockintr(void *arg, uint32_t status, vaddr_t pc) 191 { 192 struct sbtimer_softc *sc = arg; 193 struct clockframe cf; 194 195 /* clear intr & disable timer, reset initial count, re-enable timer */ 196 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */ 197 /* XXX more to do */ 198 199 cf.pc = pc; 200 cf.sr = status; 201 202 statclock(&cf); 203 } 204 205 static void 206 sbtimer_miscintr(void *arg, uint32_t status, vaddr_t pc) 207 { 208 struct sbtimer_softc *sc = arg; 209 210 /* disable timer */ 211 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */ 212 213 /* XXX more to do */ 214 } 215