1 /* ********************************************************************* 2 * BCM1280/BCM1480 Board Support Package 3 * 4 * High-Speed Port Block constants File: bcm1480_hsp.h 5 * 6 * This module contains constants and macros useful for 7 * programming the high-speed (HT/SPI-4) ports. 8 * 9 * BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 #ifndef _BCM1480_HSP_H 49 #define _BCM1480_HSP_H 50 51 #include "sb1250_defs.h" 52 53 54 #define BCM1480_HSP_NUM_PORTS 3 55 56 57 /* 58 * RX SPI-4 Configuration 0 Register (Table 334) 59 */ 60 61 #define M_BCM1480_HSP_RX_PORT_RESET _SB_MAKEMASK1(0) 62 #define M_BCM1480_HSP_RX_PLL_DIV_4 _SB_MAKEMASK1(2) 63 64 #define S_BCM1480_HSP_RX_PLL_MULTIPLIER 3 65 #define M_BCM1480_HSP_RX_PLL_MULTIPLIER _SB_MAKEMASK(5,S_BCM1480_HSP_RX_PLL_MULTIPLIER) 66 #define V_BCM1480_HSP_RX_PLL_MULTIPLIER(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PLL_MULTIPLIER) 67 #define G_BCM1480_HSP_RX_PLL_MULTIPLIER(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PLL_MULTIPLIER,M_BCM1480_HSP_RX_PLL_MULTIPLIER) 68 69 #define S_BCM1480_HSP_TRAIN_CYCLE_COUNT 8 70 #define M_BCM1480_HSP_TRAIN_CYCLE_COUNT _SB_MAKEMASK(8,S_BCM1480_HSP_TRAIN_CYCLE_COUNT) 71 #define V_BCM1480_HSP_TRAIN_CYCLE_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TRAIN_CYCLE_COUNT) 72 #define G_BCM1480_HSP_TRAIN_CYCLE_COUNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TRAIN_CYCLE_COUNT,M_BCM1480_HSP_TRAIN_CYCLE_COUNT) 73 74 #define S_BCM1480_HSP_DIP4_ERR_CLEAR 16 75 #define M_BCM1480_HSP_DIP4_ERR_CLEAR _SB_MAKEMASK(4,S_BCM1480_HSP_DIP4_ERR_CLEAR) 76 #define V_BCM1480_HSP_DIP4_ERR_CLEAR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_DIP4_ERR_CLEAR) 77 #define G_BCM1480_HSP_DIP4_ERR_CLEAR(x) _SB_GETVALUE(x,S_BCM1480_HSP_DIP4_ERR_CLEAR,M_BCM1480_HSP_DIP4_ERR_CLEAR) 78 79 #define S_BCM1480_DIP4_ERR_LIMIT 20 80 #define M_BCM1480_DIP4_ERR_LIMIT _SB_MAKEMASK(4,S_BCM1480_DIP4_ERR_LIMIT) 81 #define V_BCM1480_DIP4_ERR_LIMIT(x) _SB_MAKEVALUE(x,S_BCM1480_DIP4_ERR_LIMIT) 82 #define G_BCM1480_DIP4_ERR_LIMIT(x) _SB_GETVALUE(x,S_BCM1480_DIP4_ERR_LIMIT,M_BCM1480_DIP4_ERR_LIMIT) 83 84 #define M_BCM1480_HSP_RSTAT_POLARITY _SB_MAKEMASK1(24) 85 86 #define S_BCM1480_HSP_LINK_MODE 62 87 #define M_BCM1480_HSP_LINK_MODE _SB_MAKEMASK(2,S_BCM1480_HSP_LINK_MODE) 88 #define V_BCM1480_HSP_LINK_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_LINK_MODE) 89 #define G_BCM1480_HSP_LINK_MODE(x) _SB_GETVALUE(x,S_BCM1480_HSP_LINK_MODE,M_BCM1480_HSP_LINK_MODE) 90 91 92 #define K_BCM1480_HSP_LINK_MODE_HT 0 93 #define K_BCM1480_HSP_LINK_MODE_NOTCONN 1 94 #define K_BCM1480_HSP_LINK_MODE_SPI4 3 95 96 /* 97 * RX SPI-4 De-Skew Override Configuration Register (Table 335) 98 */ 99 100 /* 101 * Note: these macros don't follow the usual convention, since the entire 102 * thing is basically an array of 4-bit fields, we add the "bit" parameter to each. 103 */ 104 #define M_BCM1480_HSP_RX_DESKEW_BIT(b) _SB_MAKEMASK(2,S_BCM1480_HSP_RX_DESKEW_BIT(b)) 105 #define V_BCM1480_HSP_RX_DESKEW_BIT(b,x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DESKEW_BIT(b)) 106 #define G_BCM1480_HSP_RX_DESKEW_BIT(b,x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_DESKEW_BIT(b),M_BCM1480_HSP_RX_DESKEW_BIT(b)) 107 108 109 /* 110 * RX SPI-4 Data Path and Deskew Configuration Register (Table 336) 111 */ 112 113 #define S_BCM1480_HSP_RX_DESKEW_PER_BIT 0 114 #define M_BCM1480_HSP_RX_DESKEW_PER_BIT _SB_MAKEMASK(4,S_BCM1480_HSP_RX_DESKEW_PER_BIT) 115 #define V_BCM1480_HSP_RX_DESKEW_PER_BIT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DESKEW_PER_BIT) 116 #define G_BCM1480_HSP_RX_DESKEW_PER_BIT(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_DESKEW_PER_BIT,M_BCM1480_HSP_RX_DESKEW_PER_BIT) 117 118 #define M_BCM1480_HSP_RX_STATIC_DESKEW_EN _SB_MAKEMASK1(4) 119 #define M_BCM1480_HSP_RX_DESKEW_DISA _SB_MAKEMASK1(5) 120 #define M_BCM1480_HSP_RX_RETRAIN_EN _SB_MAKEMASK1(8) 121 122 123 /* 124 * TX SPI-4 Configuration 0 Register (Table 337) 125 */ 126 127 #define M_BCM1480_HSP_TX_PORT_RESET _SB_MAKEMASK1(0) 128 129 #define S_BCM1480_HSP_TX_PLL_MULTIPLIER 1 130 #define M_BCM1480_HSP_TX_PLL_MULTIPLIER _SB_MAKEMASK(5,S_BCM1480_HSP_TX_PLL_MULTIPLIER) 131 #define V_BCM1480_HSP_TX_PLL_MULTIPLIER(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PLL_MULTIPLIER) 132 #define G_BCM1480_HSP_TX_PLL_MULTIPLIER(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PLL_MULTIPLIER,M_BCM1480_HSP_TX_PLL_MULTIPLIER) 133 134 #define S_BCM1480_HSP_TX_RST_TRAINCNT 8 135 #define M_BCM1480_HSP_TX_RST_TRAINCNT _SB_MAKEMASK(16,S_BCM1480_HSP_TX_RST_TRAINCNT) 136 #define V_BCM1480_HSP_TX_RST_TRAINCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RST_TRAINCNT) 137 #define G_BCM1480_HSP_TX_RST_TRAINCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_RST_TRAINCNT,M_BCM1480_HSP_TX_RST_TRAINCNT) 138 139 #define S_BCM1480_HSP_TX_RST_STATCNT 24 140 #define M_BCM1480_HSP_TX_RST_STATCNT _SB_MAKEMASK(4,S_BCM1480_HSP_TX_RST_STATCNT) 141 #define V_BCM1480_HSP_TX_RST_STATCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RST_STATCNT) 142 #define G_BCM1480_HSP_TX_RST_STATCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_RST_STATCNT,M_BCM1480_HSP_TX_RST_STATCNT) 143 144 #define M_BCM1480_HSP_TX_FORCE_ERR _SB_MAKEMASK1(32) 145 #define M_BCM1480_HSP_TX_TSTAT_SLOW_MODE _SB_MAKEMASK1(33) 146 #define M_BCM1480_HSP_TX_TX_PLL_DIV_4 _SB_MAKEMASK1(34) 147 148 #define S_BCM1480_HSP_TX_DIP2_ERRLIMIT 36 149 #define M_BCM1480_HSP_TX_DIP2_ERRLIMIT _SB_MAKEMASK(4,S_BCM1480_HSP_TX_DIP2_ERRLIMIT) 150 #define V_BCM1480_HSP_TX_DIP2_ERRLIMIT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_DIP2_ERRLIMIT) 151 #define G_BCM1480_HSP_TX_DIP2_ERRLIMIT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_DIP2_ERRLIMIT,M_BCM1480_HSP_TX_DIP2_ERRLIMIT) 152 153 #define M_BCM1480_HSP_TX_TSTAT_POLARITY _SB_MAKEMASK1(40) 154 #define M_BCM1480_HSP_TX_TX_OFF _SB_MAKEMASK1(41) 155 156 157 /* 158 * TX SPI-4 Training and Packet Configuration Register (Table 338) 159 */ 160 161 #define S_BCM1480_HSP_TX_DATA_MAX_T 0 162 #define M_BCM1480_HSP_TX_DATA_MAX_T _SB_MAKEMASK(16,S_BCM1480_HSP_TX_DATA_MAX_T) 163 #define V_BCM1480_HSP_TX_DATA_MAX_T(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_DATA_MAX_T) 164 #define G_BCM1480_HSP_TX_DATA_MAX_T(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_DATA_MAX_T,M_BCM1480_HSP_TX_DATA_MAX_T) 165 166 #define S_BCM1480_HSP_TX_TXPREFBURSTSZ 32 167 #define M_BCM1480_HSP_TX_TXPREFBURSTSZ _SB_MAKEMASK(8,S_BCM1480_HSP_TX_TXPREFBURSTSZ) 168 #define V_BCM1480_HSP_TX_TXPREFBURSTSZ(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_TXPREFBURSTSZ) 169 #define G_BCM1480_HSP_TX_TXPREFBURSTSZ(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_TXPREFBURSTSZ,M_BCM1480_HSP_TX_TXPREFBURSTSZ) 170 171 #define S_BCM1480_HSP_TX_TXMAXBURSTSZ 40 172 #define M_BCM1480_HSP_TX_TXMAXBURSTSZ _SB_MAKEMASK(8,S_BCM1480_HSP_TX_TXMAXBURSTSZ) 173 #define V_BCM1480_HSP_TX_TXMAXBURSTSZ(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_TXMAXBURSTSZ) 174 #define G_BCM1480_HSP_TX_TXMAXBURSTSZ(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_TXMAXBURSTSZ,M_BCM1480_HSP_TX_TXMAXBURSTSZ) 175 176 #define M_BCM1480_HSP_TX_NO_INTERLEAVE_MODE _SB_MAKEMASK1(48) 177 178 179 /* ********************************************************************* 180 * Interrupts and Diagnostics 181 ********************************************************************* */ 182 183 /* 184 * RX SPI4 Interrupt enable and Interrupt Status (tables 339, 340) 185 */ 186 187 #define M_BCM1480_HSP_RX_INT_PERVCERR _SB_MAKEMASK1(0) 188 #define M_BCM1480_HSP_RX_INT_EOPABORT _SB_MAKEMASK1(1) 189 #define M_BCM1480_HSP_RX_INT_SPI4PROTOERR _SB_MAKEMASK1(2) 190 #define M_BCM1480_HSP_RX_INT_ESTOREOVERFLOW _SB_MAKEMASK1(3) 191 #define M_BCM1480_HSP_RX_INT_ALPHATRAINERR _SB_MAKEMASK1(4) 192 #define M_BCM1480_HSP_RX_INT_DIP4ERROR _SB_MAKEMASK1(5) 193 #define M_BCM1480_HSP_RX_INT_HRERROR _SB_MAKEMASK1(6) 194 #define M_BCM1480_HSP_RX_INT_INTOVERFLOW _SB_MAKEMASK1(7) 195 196 197 198 /* 199 * RX HT Diagnostic CRC Error (tables 341, 342) 200 */ 201 202 203 #define S_BCM1480_HSP_RX_BAD_CRC_LANE 0 204 #define M_BCM1480_HSP_RX_BAD_CRC_LANE _SB_MAKEMASK(32,S_BCM1480_HSP_RX_BAD_CRC_LANE) 205 #define V_BCM1480_HSP_RX_BAD_CRC_LANE(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_BAD_CRC_LANE) 206 #define G_BCM1480_HSP_RX_BAD_CRC_LANE(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_BAD_CRC_LANE,M_BCM1480_HSP_RX_BAD_CRC_LANE) 207 208 #define S_BCM1480_HSP_RX_EXPECTED_CRC_LANE 32 209 #define M_BCM1480_HSP_RX_EXPECTED_CRC_LANE _SB_MAKEMASK(32,S_BCM1480_HSP_RX_EXPECTED_CRC_LANE) 210 #define V_BCM1480_HSP_RX_EXPECTED_CRC_LANE(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_EXPECTED_CRC_LANE) 211 #define G_BCM1480_HSP_RX_EXPECTED_CRC_LANE(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_EXPECTED_CRC_LANE,M_BCM1480_HSP_RX_EXPECTED_CRC_LANE) 212 213 /* 214 * RX Diagnostic HT Command (Table 343) 215 */ 216 217 /* No fields */ 218 219 /* 220 * RX Diagnsostic Packet Protocol (Table 344) 221 */ 222 223 #define S_BCM1480_HSP_RX_DIAG_VC 0 224 #define M_BCM1480_HSP_RX_DIAG_VC _SB_MAKEMASK(8,S_BCM1480_HSP_RX_DIAG_VC) 225 #define V_BCM1480_HSP_RX_DIAG_VC(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAG_VC) 226 #define G_BCM1480_HSP_RX_DIAG_VC(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAG_VC,M_BCM1480_HSP_RX_DIAG_VC) 227 228 #define M_BCM1480_HSP_RX_DIAG_EOP _SB_MAKEMASK1(8) 229 #define M_BCM1480_HSP_RX_DIAG_SOP _SB_MAKEMASK1(9) 230 231 #define S_BCM1480_HSP_RX_DIAG_CONTROL 10 232 #define M_BCM1480_HSP_RX_DIAG_CONTROL _SB_MAKEMASK(4,S_BCM1480_HSP_RX_DIAG_CONTROL) 233 #define V_BCM1480_HSP_RX_DIAG_CONTROL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAG_CONTROL) 234 #define G_BCM1480_HSP_RX_DIAG_CONTROL(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAG_CONTROL,M_BCM1480_HSP_RX_DIAG_CONTROL) 235 236 #define M_BCM1480_HSP_RX_STRADDLING_CMD _SB_MAKEMASK1(14) 237 238 #define S_BCM1480_HSP_RX_DIAG_ERR_CODE_1 16 239 #define M_BCM1480_HSP_RX_DIAG_ERR_CODE_1 _SB_MAKEMASK(4,S_BCM1480_HSP_RX_DIAG_ERR_CODE_1) 240 #define V_BCM1480_HSP_RX_DIAG_ERR_CODE_1(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAG_ERR_CODE_1) 241 #define G_BCM1480_HSP_RX_DIAG_ERR_CODE_1(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAG_ERR_CODE_1,M_BCM1480_HSP_RX_DIAG_ERR_CODE_1) 242 243 #define S_BCM1480_HSP_RX_DIAG_ERR_CODE_2 20 244 #define M_BCM1480_HSP_RX_DIAG_ERR_CODE_2 _SB_MAKEMASK(4,S_BCM1480_HSP_RX_DIAG_ERR_CODE_2) 245 #define V_BCM1480_HSP_RX_DIAG_ERR_CODE_2(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAG_ERR_CODE_2) 246 #define G_BCM1480_HSP_RX_DIAG_ERR_CODE_2(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAG_ERR_CODE_2,M_BCM1480_HSP_RX_DIAG_ERR_CODE_2) 247 248 249 /* 250 * RX Diagnostic Detail (Table 345) 251 */ 252 253 #define M_BCM1480_HSP_RX_DIAGDET_PERVCERR _SB_MAKEMASK1(0) 254 #define M_BCM1480_HSP_RX_DIAGDET_ALPHATRAINERR _SB_MAKEMASK1(2) 255 #define M_BCM1480_HSP_RX_DIAGDET_SPI4PROTOERR _SB_MAKEMASK1(4) 256 #define M_BCM1480_HSP_RX_DIAGDET_DIP4ERROR _SB_MAKEMASK1(6) 257 #define M_BCM1480_HSP_RX_DIAGDET_ESTOREOVERFLOW _SB_MAKEMASK1(7) 258 259 260 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_DATANOSOP _SB_MAKEMASK1(32) 261 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_SOPAFTERSOP _SB_MAKEMASK1(33) 262 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_EOPNOSOP _SB_MAKEMASK1(34) 263 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_EOPABORT _SB_MAKEMASK1(35) 264 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_BADDATA _SB_MAKEMASK1(36) 265 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_RESCMD _SB_MAKEMASK1(37) 266 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_BADSOP _SB_MAKEMASK1(38) 267 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_BADEOP _SB_MAKEMASK1(39) 268 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_BADCTL _SB_MAKEMASK1(40) 269 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_BADIDLE _SB_MAKEMASK1(41) 270 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_BADTRAINING _SB_MAKEMASK1(42) 271 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_ALPHATRAINING _SB_MAKEMASK1(43) 272 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_DIP4IDLE _SB_MAKEMASK1(44) 273 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_DIP4EOP _SB_MAKEMASK1(45) 274 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_DIP4DEAD _SB_MAKEMASK1(46) 275 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_HRNOMATCH _SB_MAKEMASK1(47) 276 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_HRMULTMATCH _SB_MAKEMASK1(48) 277 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_ESTOREOVR _SB_MAKEMASK1(49) 278 #define M_BCM1480_HSP_RX_DIAGDET_SPI4_INTOVR _SB_MAKEMASK1(51) 279 280 281 #define S_BCM1480_HSP_RX_DIAGDET_STATUS 32 282 #define M_BCM1480_HSP_RX_DIAGDET_STATUS _SB_MAKEMASK(20,S_BCM1480_HSP_RX_DIAGDET_STATUS) 283 #define V_BCM1480_HSP_RX_DIAGDET_STATUS(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAGDET_STATUS) 284 #define G_BCM1480_HSP_RX_DIAGDET_STATUS(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAGDET_STATUS,M_BCM1480_HSP_RX_DIAGDET_STATUS) 285 286 #define S_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE 56 287 #define M_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE _SB_MAKEMASK(4,S_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE) 288 #define V_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE) 289 #define G_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE,M_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE) 290 291 #define S_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE 60 292 #define M_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE _SB_MAKEMASK(4,S_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE) 293 #define V_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE) 294 #define G_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE,M_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE) 295 296 /* 297 * TX SPI4 Interrupt Enable and Interrupt Status (Table 346, 347) 298 */ 299 300 #define M_BCM1480_HSP_TX_INT_TSTATTIMEOUT _SB_MAKEMASK1(0) 301 #define M_BCM1480_HSP_TX_INT_DIP2RXERR _SB_MAKEMASK1(1) 302 #define M_BCM1480_HSP_TX_INT_SPI4RESET _SB_MAKEMASK1(2) 303 304 /* 305 * RX Packet Buffer Allocation Registers (Table 349) 306 */ 307 308 /* 309 * XXX Depending on the revision of the manual, the fields may look 310 * incorrect here. Check the errata for the correct layout 311 * of this register. 312 */ 313 314 #define S_BCM1480_HSP_RX_RAMCEILING_0 0 315 #define M_BCM1480_HSP_RX_RAMCEILING_0 _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RAMCEILING_0) 316 #define V_BCM1480_HSP_RX_RAMCEILING_0(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RAMCEILING_0) 317 #define G_BCM1480_HSP_RX_RAMCEILING_0(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_RAMCEILING_0,M_BCM1480_HSP_RX_RAMCEILING_0) 318 319 #define S_BCM1480_HSP_RX_RAMFLOOR_0 16 320 #define M_BCM1480_HSP_RX_RAMFLOOR_0 _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RAMFLOOR_0) 321 #define V_BCM1480_HSP_RX_RAMFLOOR_0(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RAMFLOOR_0) 322 #define G_BCM1480_HSP_RX_RAMFLOOR_0(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_RAMFLOOR_0,M_BCM1480_HSP_RX_RAMFLOOR_0) 323 324 #define S_BCM1480_HSP_RX_RAMCEILING_1 32 325 #define M_BCM1480_HSP_RX_RAMCEILING_1 _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RAMCEILING_1) 326 #define V_BCM1480_HSP_RX_RAMCEILING_1(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RAMCEILING_1) 327 #define G_BCM1480_HSP_RX_RAMCEILING_1(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_RAMCEILING_1,M_BCM1480_HSP_RX_RAMCEILING_1) 328 329 #define S_BCM1480_HSP_RX_RAMFLOOR_1 48 330 #define M_BCM1480_HSP_RX_RAMFLOOR_1 _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RAMFLOOR_1) 331 #define V_BCM1480_HSP_RX_RAMFLOOR_1(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RAMFLOOR_1) 332 #define G_BCM1480_HSP_RX_RAMFLOOR_1(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_RAMFLOOR_1,M_BCM1480_HSP_RX_RAMFLOOR_1) 333 334 /* 335 * RX HT RAM Allocation Register 0 (Table 350 + Errata) 336 */ 337 338 #define S_BCM1480_HSP_RX_NPC_CMD_CEILING 0 339 #define M_BCM1480_HSP_RX_NPC_CMD_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_NPC_CMD_CEILING) 340 #define V_BCM1480_HSP_RX_NPC_CMD_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_CEILING) 341 #define G_BCM1480_HSP_RX_NPC_CMD_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_CEILING,M_BCM1480_HSP_RX_NPC_CMD_CEILING) 342 343 #define S_BCM1480_HSP_RX_NPC_CMD_FLOOR 16 344 #define M_BCM1480_HSP_RX_NPC_CMD_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_NPC_CMD_FLOOR) 345 #define V_BCM1480_HSP_RX_NPC_CMD_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_FLOOR) 346 #define G_BCM1480_HSP_RX_NPC_CMD_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_FLOOR,M_BCM1480_HSP_RX_NPC_CMD_FLOOR) 347 348 /* 349 * RX HT RAM Allocation Register 1 (Table 351 + Errata) 350 */ 351 352 #define S_BCM1480_HSP_RX_PC_CMD_CEILING 0 353 #define M_BCM1480_HSP_RX_PC_CMD_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PC_CMD_CEILING) 354 #define V_BCM1480_HSP_RX_PC_CMD_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_CMD_CEILING) 355 #define G_BCM1480_HSP_RX_PC_CMD_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_CMD_CEILING,M_BCM1480_HSP_RX_PC_CMD_CEILING) 356 357 #define S_BCM1480_HSP_RX_PC_CMD_FLOOR 16 358 #define M_BCM1480_HSP_RX_PC_CMD_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PC_CMD_FLOOR) 359 #define V_BCM1480_HSP_RX_PC_CMD_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_CMD_FLOOR) 360 #define G_BCM1480_HSP_RX_PC_CMD_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_CMD_FLOOR,M_BCM1480_HSP_RX_PC_CMD_FLOOR) 361 362 #define S_BCM1480_HSP_RX_PRB_CEILING 32 363 #define M_BCM1480_HSP_RX_PRB_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PRB_CEILING) 364 #define V_BCM1480_HSP_RX_PRB_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PRB_CEILING) 365 #define G_BCM1480_HSP_RX_PRB_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PRB_CEILING,M_BCM1480_HSP_RX_PRB_CEILING) 366 367 #define S_BCM1480_HSP_RX_PRB_FLOOR 48 368 #define M_BCM1480_HSP_RX_PRB_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PRB_FLOOR) 369 #define V_BCM1480_HSP_RX_PRB_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PRB_FLOOR) 370 #define G_BCM1480_HSP_RX_PRB_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PRB_FLOOR,M_BCM1480_HSP_RX_PRB_FLOOR) 371 372 /* 373 * RX HT RAM Allocation Register 2 (Table 352 + Errata) 374 */ 375 376 #define S_BCM1480_HSP_RX_ACK_CEILING 0 377 #define M_BCM1480_HSP_RX_ACK_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ACK_CEILING) 378 #define V_BCM1480_HSP_RX_ACK_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ACK_CEILING) 379 #define G_BCM1480_HSP_RX_ACK_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_ACK_CEILING,M_BCM1480_HSP_RX_ACK_CEILING) 380 381 #define S_BCM1480_HSP_RX_ACK_FLOOR 16 382 #define M_BCM1480_HSP_RX_ACK_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ACK_FLOOR) 383 #define V_BCM1480_HSP_RX_ACK_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ACK_FLOOR) 384 #define G_BCM1480_HSP_RX_ACK_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_ACK_FLOOR,M_BCM1480_HSP_RX_ACK_FLOOR) 385 386 #define S_BCM1480_HSP_RX_WB_CEILING 32 387 #define M_BCM1480_HSP_RX_WB_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_WB_CEILING) 388 #define V_BCM1480_HSP_RX_WB_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_WB_CEILING) 389 #define G_BCM1480_HSP_RX_WB_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_WB_CEILING,M_BCM1480_HSP_RX_WB_CEILING) 390 391 #define S_BCM1480_HSP_RX_WB_FLOOR 48 392 #define M_BCM1480_HSP_RX_WB_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_WB_FLOOR) 393 #define V_BCM1480_HSP_RX_WB_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_WB_FLOOR) 394 #define G_BCM1480_HSP_RX_WB_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_WB_FLOOR,M_BCM1480_HSP_RX_WB_FLOOR) 395 396 /* 397 * RX HT RAM Allocation Register 3 (Table 353 + Errata) 398 */ 399 400 #define S_BCM1480_HSP_RX_CFILL_CEILING 0 401 #define M_BCM1480_HSP_RX_CFILL_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_CFILL_CEILING) 402 #define V_BCM1480_HSP_RX_CFILL_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CFILL_CEILING) 403 #define G_BCM1480_HSP_RX_CFILL_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_CFILL_CEILING,M_BCM1480_HSP_RX_CFILL_CEILING) 404 405 #define S_BCM1480_HSP_RX_CFILL_FLOOR 16 406 #define M_BCM1480_HSP_RX_CFILL_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_CFILL_FLOOR) 407 #define V_BCM1480_HSP_RX_CFILL_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CFILL_FLOOR) 408 #define G_BCM1480_HSP_RX_CFILL_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_CFILL_FLOOR,M_BCM1480_HSP_RX_CFILL_FLOOR) 409 410 #define S_BCM1480_HSP_RX_CRD_CEILING 32 411 #define M_BCM1480_HSP_RX_CRD_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_CRD_CEILING) 412 #define V_BCM1480_HSP_RX_CRD_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CRD_CEILING) 413 #define G_BCM1480_HSP_RX_CRD_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_CRD_CEILING,M_BCM1480_HSP_RX_CRD_CEILING) 414 415 #define S_BCM1480_HSP_RX_CRD_FLOOR 48 416 #define M_BCM1480_HSP_RX_CRD_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_CRD_FLOOR) 417 #define V_BCM1480_HSP_RX_CRD_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CRD_FLOOR) 418 #define G_BCM1480_HSP_RX_CRD_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_CRD_FLOOR,M_BCM1480_HSP_RX_CRD_FLOOR) 419 420 /* 421 * RX HT RAM Allocation Register 4 (Table 354 + Errata) 422 */ 423 424 #define S_BCM1480_HSP_RX_NPC_DAT_CEILING 0 425 #define M_BCM1480_HSP_RX_NPC_DAT_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_NPC_DAT_CEILING) 426 #define V_BCM1480_HSP_RX_NPC_DAT_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_CEILING) 427 #define G_BCM1480_HSP_RX_NPC_DAT_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_CEILING,M_BCM1480_HSP_RX_NPC_DAT_CEILING) 428 429 #define S_BCM1480_HSP_RX_NPC_DAT_FLOOR 16 430 #define M_BCM1480_HSP_RX_NPC_DAT_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_NPC_DAT_FLOOR) 431 #define V_BCM1480_HSP_RX_NPC_DAT_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_FLOOR) 432 #define G_BCM1480_HSP_RX_NPC_DAT_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_FLOOR,M_BCM1480_HSP_RX_NPC_DAT_FLOOR) 433 434 #define S_BCM1480_HSP_RX_RSP_DAT_CEILING 32 435 #define M_BCM1480_HSP_RX_RSP_DAT_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RSP_DAT_CEILING) 436 #define V_BCM1480_HSP_RX_RSP_DAT_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_CEILING) 437 #define G_BCM1480_HSP_RX_RSP_DAT_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_CEILING,M_BCM1480_HSP_RX_RSP_DAT_CEILING) 438 439 #define S_BCM1480_HSP_RX_RSP_DAT_FLOOR 48 440 #define M_BCM1480_HSP_RX_RSP_DAT_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RSP_DAT_FLOOR) 441 #define V_BCM1480_HSP_RX_RSP_DAT_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_FLOOR) 442 #define G_BCM1480_HSP_RX_RSP_DAT_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_FLOOR,M_BCM1480_HSP_RX_RSP_DAT_FLOOR) 443 444 /* 445 * RX HT RAM Allocation Register 5 (Table 355 + Errata) 446 */ 447 448 #define S_BCM1480_HSP_RX_PC_DAT_CEILING 0 449 #define M_BCM1480_HSP_RX_PC_DAT_CEILING _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PC_DAT_CEILING) 450 #define V_BCM1480_HSP_RX_PC_DAT_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_DAT_CEILING) 451 #define G_BCM1480_HSP_RX_PC_DAT_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_DAT_CEILING,M_BCM1480_HSP_RX_PC_DAT_CEILING) 452 453 #define S_BCM1480_HSP_RX_PC_DAT_FLOOR 16 454 #define M_BCM1480_HSP_RX_PC_DAT_FLOOR _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PC_DAT_FLOOR) 455 #define V_BCM1480_HSP_RX_PC_DAT_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_DAT_FLOOR) 456 #define G_BCM1480_HSP_RX_PC_DAT_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_DAT_FLOOR,M_BCM1480_HSP_RX_PC_DAT_FLOOR) 457 458 /* ... */ 459 460 /* 461 * TX Packet Buffer Allocation Registers (Table 356) 462 */ 463 464 #define S_BCM1480_HSP_TX_RAMCEILING_0 0 465 #define M_BCM1480_HSP_TX_RAMCEILING_0 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RAMCEILING_0) 466 #define V_BCM1480_HSP_TX_RAMCEILING_0(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RAMCEILING_0) 467 #define G_BCM1480_HSP_TX_RAMCEILING_0(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_RAMCEILING_0,M_BCM1480_HSP_TX_RAMCEILING_0) 468 469 #define S_BCM1480_HSP_TX_RAMFLOOR_0 16 470 #define M_BCM1480_HSP_TX_RAMFLOOR_0 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RAMFLOOR_0) 471 #define V_BCM1480_HSP_TX_RAMFLOOR_0(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RAMFLOOR_0) 472 #define G_BCM1480_HSP_TX_RAMFLOOR_0(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_RAMFLOOR_0,M_BCM1480_HSP_TX_RAMFLOOR_0) 473 474 #define S_BCM1480_HSP_TX_RAMCEILING_1 32 475 #define M_BCM1480_HSP_TX_RAMCEILING_1 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RAMCEILING_1) 476 #define V_BCM1480_HSP_TX_RAMCEILING_1(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RAMCEILING_1) 477 #define G_BCM1480_HSP_TX_RAMCEILING_1(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_RAMCEILING_1,M_BCM1480_HSP_TX_RAMCEILING_1) 478 479 #define S_BCM1480_HSP_TX_RAMFLOOR_1 48 480 #define M_BCM1480_HSP_TX_RAMFLOOR_1 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RAMFLOOR_1) 481 #define V_BCM1480_HSP_TX_RAMFLOOR_1(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RAMFLOOR_1) 482 #define G_BCM1480_HSP_TX_RAMFLOOR_1(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_RAMFLOOR_1,M_BCM1480_HSP_TX_RAMFLOOR_1) 483 484 /* 485 * TX Non-Posted Command (NPC) Allocation Register (Table 357) 486 */ 487 488 #define S_BCM1480_HSP_TX_NPC_CEILING 0 489 #define M_BCM1480_HSP_TX_NPC_CEILING _SB_MAKEMASK(8,S_BCM1480_HSP_TX_NPC_CEILING) 490 #define V_BCM1480_HSP_TX_NPC_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NPC_CEILING) 491 #define G_BCM1480_HSP_TX_NPC_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_NPC_CEILING,M_BCM1480_HSP_TX_NPC_CEILING) 492 493 #define S_BCM1480_HSP_TX_NPC_FLOOR 16 494 #define M_BCM1480_HSP_TX_NPC_FLOOR _SB_MAKEMASK(8,S_BCM1480_HSP_TX_NPC_FLOOR) 495 #define V_BCM1480_HSP_TX_NPC_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NPC_FLOOR) 496 #define G_BCM1480_HSP_TX_NPC_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_NPC_FLOOR,M_BCM1480_HSP_TX_NPC_FLOOR) 497 498 /* 499 * TX Response (RSP) Allocation Register (Table 358) 500 */ 501 502 #define S_BCM1480_HSP_TX_RSP_CEILING 0 503 #define M_BCM1480_HSP_TX_RSP_CEILING _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RSP_CEILING) 504 #define V_BCM1480_HSP_TX_RSP_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RSP_CEILING) 505 #define G_BCM1480_HSP_TX_RSP_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_RSP_CEILING,M_BCM1480_HSP_TX_RSP_CEILING) 506 507 #define S_BCM1480_HSP_TX_RSP_FLOOR 16 508 #define M_BCM1480_HSP_TX_RSP_FLOOR _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RSP_FLOOR) 509 #define V_BCM1480_HSP_TX_RSP_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RSP_FLOOR) 510 #define G_BCM1480_HSP_TX_RSP_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_RSP_FLOOR,M_BCM1480_HSP_TX_RSP_FLOOR) 511 512 /* 513 * TX Posted Command (PC) Allocation Register (Table 359) 514 */ 515 516 #define S_BCM1480_HSP_TX_PC_CEILING 0 517 #define M_BCM1480_HSP_TX_PC_CEILING _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PC_CEILING) 518 #define V_BCM1480_HSP_TX_PC_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PC_CEILING) 519 #define G_BCM1480_HSP_TX_PC_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PC_CEILING,M_BCM1480_HSP_TX_PC_CEILING) 520 521 #define S_BCM1480_HSP_TX_PC_FLOOR 16 522 #define M_BCM1480_HSP_TX_PC_FLOOR _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PC_FLOOR) 523 #define V_BCM1480_HSP_TX_PC_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PC_FLOOR) 524 #define G_BCM1480_HSP_TX_PC_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PC_FLOOR,M_BCM1480_HSP_TX_PC_FLOOR) 525 526 /* 527 * TX Probe (PC) and Acknowledgement (ACK) Allocation Register (Table 360) 528 */ 529 530 #define S_BCM1480_HSP_TX_PRB_CEILING 0 531 #define M_BCM1480_HSP_TX_PRB_CEILING _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PRB_CEILING) 532 #define V_BCM1480_HSP_TX_PRB_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PRB_CEILING) 533 #define G_BCM1480_HSP_TX_PRB_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PRB_CEILING,M_BCM1480_HSP_TX_PRB_CEILING) 534 535 #define S_BCM1480_HSP_TX_PRB_FLOOR 16 536 #define M_BCM1480_HSP_TX_PRB_FLOOR _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PRB_FLOOR) 537 #define V_BCM1480_HSP_TX_PRB_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PRB_FLOOR) 538 #define G_BCM1480_HSP_TX_PRB_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PRB_FLOOR,M_BCM1480_HSP_TX_PRB_FLOOR) 539 540 #define S_BCM1480_HSP_TX_ACK_CEILING 32 541 #define M_BCM1480_HSP_TX_ACK_CEILING _SB_MAKEMASK(8,S_BCM1480_HSP_TX_ACK_CEILING) 542 #define V_BCM1480_HSP_TX_ACK_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_ACK_CEILING) 543 #define G_BCM1480_HSP_TX_ACK_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_ACK_CEILING,M_BCM1480_HSP_TX_ACK_CEILING) 544 545 #define S_BCM1480_HSP_TX_ACK_FLOOR 48 546 #define M_BCM1480_HSP_TX_ACK_FLOOR _SB_MAKEMASK(8,S_BCM1480_HSP_TX_ACK_FLOOR) 547 #define V_BCM1480_HSP_TX_ACK_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_ACK_FLOOR) 548 #define G_BCM1480_HSP_TX_ACK_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_ACK_FLOOR,M_BCM1480_HSP_TX_ACK_FLOOR) 549 550 /* 551 * TX Writeback (WB) and Coherent Fill (CFILL) Allocation Register (Table 361) 552 */ 553 554 #define S_BCM1480_HSP_TX_WB_CEILING 0 555 #define M_BCM1480_HSP_TX_WB_CEILING _SB_MAKEMASK(8,S_BCM1480_HSP_TX_WB_CEILING) 556 #define V_BCM1480_HSP_TX_WB_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_WB_CEILING) 557 #define G_BCM1480_HSP_TX_WB_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_WB_CEILING,M_BCM1480_HSP_TX_WB_CEILING) 558 559 #define S_BCM1480_HSP_TX_WB_FLOOR 16 560 #define M_BCM1480_HSP_TX_WB_FLOOR _SB_MAKEMASK(8,S_BCM1480_HSP_TX_WB_FLOOR) 561 #define V_BCM1480_HSP_TX_WB_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_WB_FLOOR) 562 #define G_BCM1480_HSP_TX_WB_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_WB_FLOOR,M_BCM1480_HSP_TX_WB_FLOOR) 563 564 #define S_BCM1480_HSP_TX_CFILL_CEILING 32 565 #define M_BCM1480_HSP_TX_CFILL_CEILING _SB_MAKEMASK(8,S_BCM1480_HSP_TX_CFILL_CEILING) 566 #define V_BCM1480_HSP_TX_CFILL_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CFILL_CEILING) 567 #define G_BCM1480_HSP_TX_CFILL_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_CFILL_CEILING,M_BCM1480_HSP_TX_CFILL_CEILING) 568 569 #define S_BCM1480_HSP_TX_CFILL_FLOOR 48 570 #define M_BCM1480_HSP_TX_CFILL_FLOOR _SB_MAKEMASK(8,S_BCM1480_HSP_TX_CFILL_FLOOR) 571 #define V_BCM1480_HSP_TX_CFILL_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CFILL_FLOOR) 572 #define G_BCM1480_HSP_TX_CFILL_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_CFILL_FLOOR,M_BCM1480_HSP_TX_CFILL_FLOOR) 573 574 /* 575 * TX Coherent Read (CRD) Allocation Register (Table 362) 576 */ 577 578 #define S_BCM1480_HSP_TX_CRD_CEILING 0 579 #define M_BCM1480_HSP_TX_CRD_CEILING _SB_MAKEMASK(8,S_BCM1480_HSP_TX_CRD_CEILING) 580 #define V_BCM1480_HSP_TX_CRD_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CRD_CEILING) 581 #define G_BCM1480_HSP_TX_CRD_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_CRD_CEILING,M_BCM1480_HSP_TX_CRD_CEILING) 582 583 #define S_BCM1480_HSP_TX_CRD_FLOOR 16 584 #define M_BCM1480_HSP_TX_CRD_FLOOR _SB_MAKEMASK(8,S_BCM1480_HSP_TX_CRD_FLOOR) 585 #define V_BCM1480_HSP_TX_CRD_FLOOR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CRD_FLOOR) 586 #define G_BCM1480_HSP_TX_CRD_FLOOR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_CRD_FLOOR,M_BCM1480_HSP_TX_CRD_FLOOR) 587 588 /* 589 * RX SPI4 Config Register 1 (Table 363) 590 */ 591 592 #define S_BCM1480_HSP_RX_CALENDAR_LEN 0 593 #define M_BCM1480_HSP_RX_CALENDAR_LEN _SB_MAKEMASK(8,S_BCM1480_HSP_RX_CALENDAR_LEN) 594 #define V_BCM1480_HSP_RX_CALENDAR_LEN(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CALENDAR_LEN) 595 #define G_BCM1480_HSP_RX_CALENDAR_LEN(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_CALENDAR_LEN,M_BCM1480_HSP_RX_CALENDAR_LEN) 596 597 #define S_BCM1480_HSP_RX_CALENDAR_M 16 598 #define M_BCM1480_HSP_RX_CALENDAR_M _SB_MAKEMASK(8,S_BCM1480_HSP_RX_CALENDAR_M) 599 #define V_BCM1480_HSP_RX_CALENDAR_M(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CALENDAR_M) 600 #define G_BCM1480_HSP_RX_CALENDAR_M(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_CALENDAR_M,M_BCM1480_HSP_RX_CALENDAR_M) 601 602 #define S_BCM1480_HSP_RX_ALPHA 40 603 #define M_BCM1480_HSP_RX_ALPHA _SB_MAKEMASK(12,S_BCM1480_HSP_RX_ALPHA) 604 #define V_BCM1480_HSP_RX_ALPHA(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALPHA) 605 #define G_BCM1480_HSP_RX_ALPHA(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALPHA,M_BCM1480_HSP_RX_ALPHA) 606 607 /* 608 * RX SPI4 Calendar registers (Table 364) 609 * Use these macros for both the _0 and _1 registers. The arg 'c' is the calendar location 610 */ 611 612 #define S_BCM1480_HSP_RX_CALENDAR_X(c) (((c)&7)*8) 613 #define M_BCM1480_HSP_RX_CALENDAR_X(c) _SB_MAKEMASK(12,S_BCM1480_HSP_RX_CALENDAR_X(c)) 614 #define V_BCM1480_HSP_RX_CALENDAR_X(c,x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CALENDAR_X(c)) 615 #define G_BCM1480_HSP_RX_CALENDAR_X(c,x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_CALENDAR_X(c),M_BCM1480_HSP_RX_CALENDAR_X(c)) 616 617 /* 618 * RX SPI4 Watermark registers (Table 365) 619 */ 620 621 #define S_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN 0 622 #define M_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN) 623 #define V_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN) 624 #define G_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN,M_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN) 625 626 #define S_BCM1480_HSP_RX_ALMOSTFULL_EVEN 16 627 #define M_BCM1480_HSP_RX_ALMOSTFULL_EVEN _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ALMOSTFULL_EVEN) 628 #define V_BCM1480_HSP_RX_ALMOSTFULL_EVEN(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALMOSTFULL_EVEN) 629 #define G_BCM1480_HSP_RX_ALMOSTFULL_EVEN(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALMOSTFULL_EVEN,M_BCM1480_HSP_RX_ALMOSTFULL_EVEN) 630 631 #define S_BCM1480_HSP_RX_ALMOSTEMPTY_ODD 32 632 #define M_BCM1480_HSP_RX_ALMOSTEMPTY_ODD _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ALMOSTEMPTY_ODD) 633 #define V_BCM1480_HSP_RX_ALMOSTEMPTY_ODD(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALMOSTEMPTY_ODD) 634 #define G_BCM1480_HSP_RX_ALMOSTEMPTY_ODD(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALMOSTEMPTY_ODD,M_BCM1480_HSP_RX_ALMOSTEMPTY_ODD) 635 636 #define S_BCM1480_HSP_RX_ALMOSTFULL_ODD 48 637 #define M_BCM1480_HSP_RX_ALMOSTFULL_ODD _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ALMOSTFULL_ODD) 638 #define V_BCM1480_HSP_RX_ALMOSTFULL_ODD(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALMOSTFULL_ODD) 639 #define G_BCM1480_HSP_RX_ALMOSTFULL_ODD(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALMOSTFULL_ODD,M_BCM1480_HSP_RX_ALMOSTFULL_ODD) 640 641 /* 642 * TX SPI4 Configuration Register 1 (Table 366) 643 */ 644 645 646 #define S_BCM1480_HSP_TX_CALENDAR_LEN 0 647 #define M_BCM1480_HSP_TX_CALENDAR_LEN _SB_MAKEMASK(8,S_BCM1480_HSP_TX_CALENDAR_LEN) 648 #define V_BCM1480_HSP_TX_CALENDAR_LEN(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CALENDAR_LEN) 649 #define G_BCM1480_HSP_TX_CALENDAR_LEN(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_CALENDAR_LEN,M_BCM1480_HSP_TX_CALENDAR_LEN) 650 651 #define S_BCM1480_HSP_TX_CALENDAR_M 16 652 #define M_BCM1480_HSP_TX_CALENDAR_M _SB_MAKEMASK(8,S_BCM1480_HSP_TX_CALENDAR_M) 653 #define V_BCM1480_HSP_TX_CALENDAR_M(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CALENDAR_M) 654 #define G_BCM1480_HSP_TX_CALENDAR_M(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_CALENDAR_M,M_BCM1480_HSP_TX_CALENDAR_M) 655 656 #define S_BCM1480_HSP_TX_MAXBURST1 24 657 #define M_BCM1480_HSP_TX_MAXBURST1 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_MAXBURST1) 658 #define V_BCM1480_HSP_TX_MAXBURST1(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_MAXBURST1) 659 #define G_BCM1480_HSP_TX_MAXBURST1(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_MAXBURST1,M_BCM1480_HSP_TX_MAXBURST1) 660 661 #define S_BCM1480_HSP_TX_MAXBURST2 32 662 #define M_BCM1480_HSP_TX_MAXBURST2 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_MAXBURST2) 663 #define V_BCM1480_HSP_TX_MAXBURST2(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_MAXBURST2) 664 #define G_BCM1480_HSP_TX_MAXBURST2(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_MAXBURST2,M_BCM1480_HSP_TX_MAXBURST2) 665 666 667 #define S_BCM1480_HSP_TX_ALPHA 40 668 #define M_BCM1480_HSP_TX_ALPHA _SB_MAKEMASK(12,S_BCM1480_HSP_TX_ALPHA) 669 #define V_BCM1480_HSP_TX_ALPHA(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_ALPHA) 670 #define G_BCM1480_HSP_TX_ALPHA(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_ALPHA,M_BCM1480_HSP_TX_ALPHA) 671 672 #define S_BCM1480_HSP_TX_ACTIVE_CHANNELS 56 673 #define M_BCM1480_HSP_TX_ACTIVE_CHANNELS _SB_MAKEMASK(8,S_BCM1480_HSP_TX_ACTIVE_CHANNELS) 674 #define V_BCM1480_HSP_TX_ACTIVE_CHANNELS(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_ACTIVE_CHANNELS) 675 #define G_BCM1480_HSP_TX_ACTIVE_CHANNELS(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_ACTIVE_CHANNELS,M_BCM1480_HSP_TX_ACTIVE_CHANNELS) 676 677 678 /* 679 * TX SPI4 Calendar registers (Table 367) 680 * Use these macros for both the _0 and _1 registers. The arg 'c' is the calendar location 681 */ 682 683 #define S_BCM1480_HSP_TX_CALENDAR_X(c) (((c)&7)*8) 684 #define M_BCM1480_HSP_TX_CALENDAR_X(c) _SB_MAKEMASK(12,S_BCM1480_HSP_TX_CALENDAR_X(c)) 685 #define V_BCM1480_HSP_TX_CALENDAR_X(c,x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CALENDAR_X(c)) 686 #define G_BCM1480_HSP_TX_CALENDAR_X(c,x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_CALENDAR_X(c),M_BCM1480_HSP_TX_CALENDAR_X(c)) 687 688 /* 689 * TX Packet Buffer Allocation Physical Unit Count Registers (Table 368) 690 */ 691 692 #define S_BCM1480_HSP_RX_PHITCNT_0 0 693 #define M_BCM1480_HSP_RX_PHITCNT_0 _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PHITCNT_0) 694 #define V_BCM1480_HSP_RX_PHITCNT_0(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PHITCNT_0) 695 #define G_BCM1480_HSP_RX_PHITCNT_0(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PHITCNT_0,M_BCM1480_HSP_RX_PHITCNT_0) 696 697 #define S_BCM1480_HSP_RX_PHITCNT_1 16 698 #define M_BCM1480_HSP_RX_PHITCNT_1 _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PHITCNT_1) 699 #define V_BCM1480_HSP_RX_PHITCNT_1(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PHITCNT_1) 700 #define G_BCM1480_HSP_RX_PHITCNT_1(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PHITCNT_1,M_BCM1480_HSP_RX_PHITCNT_1) 701 702 #define S_BCM1480_HSP_RX_PHITCNT_2 32 703 #define M_BCM1480_HSP_RX_PHITCNT_2 _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PHITCNT_2) 704 #define V_BCM1480_HSP_RX_PHITCNT_2(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PHITCNT_2) 705 #define G_BCM1480_HSP_RX_PHITCNT_2(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PHITCNT_2,M_BCM1480_HSP_RX_PHITCNT_2) 706 707 #define S_BCM1480_HSP_RX_PHITCNT_3 48 708 #define M_BCM1480_HSP_RX_PHITCNT_3 _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PHITCNT_3) 709 #define V_BCM1480_HSP_RX_PHITCNT_3(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PHITCNT_3) 710 #define G_BCM1480_HSP_RX_PHITCNT_3(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PHITCNT_3,M_BCM1480_HSP_RX_PHITCNT_3) 711 712 /* 713 * TX HT I/O Physical Unit Count Register (Table 369) 714 */ 715 716 #define S_BCM1480_HSP_RX_NPC_CMD_PHITCNT 0 717 #define M_BCM1480_HSP_RX_NPC_CMD_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_RX_NPC_CMD_PHITCNT) 718 #define V_BCM1480_HSP_RX_NPC_CMD_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_PHITCNT) 719 #define G_BCM1480_HSP_RX_NPC_CMD_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_PHITCNT,M_BCM1480_HSP_RX_NPC_CMD_PHITCNT) 720 721 #define S_BCM1480_HSP_RX_NPC_DAT_PHITCNT 8 722 #define M_BCM1480_HSP_RX_NPC_DAT_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_RX_NPC_DAT_PHITCNT) 723 #define V_BCM1480_HSP_RX_NPC_DAT_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_PHITCNT) 724 #define G_BCM1480_HSP_RX_NPC_DAT_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_PHITCNT,M_BCM1480_HSP_RX_NPC_DAT_PHITCNT) 725 726 #define S_BCM1480_HSP_RX_RSP_DAT_PHITCNT 24 727 #define M_BCM1480_HSP_RX_RSP_DAT_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_RX_RSP_DAT_PHITCNT) 728 #define V_BCM1480_HSP_RX_RSP_DAT_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_PHITCNT) 729 #define G_BCM1480_HSP_RX_RSP_DAT_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_PHITCNT,M_BCM1480_HSP_RX_RSP_DAT_PHITCNT) 730 731 #define S_BCM1480_HSP_RX_PC_CMD_PHITCNT 32 732 #define M_BCM1480_HSP_RX_PC_CMD_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_RX_PC_CMD_PHITCNT) 733 #define V_BCM1480_HSP_RX_PC_CMD_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_CMD_PHITCNT) 734 #define G_BCM1480_HSP_RX_PC_CMD_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_CMD_PHITCNT,M_BCM1480_HSP_RX_PC_CMD_PHITCNT) 735 736 #define S_BCM1480_HSP_RX_PC_DAT_PHITCNT 48 737 #define M_BCM1480_HSP_RX_PC_DAT_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_RX_PC_DAT_PHITCNT) 738 #define V_BCM1480_HSP_RX_PC_DAT_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_DAT_PHITCNT) 739 #define G_BCM1480_HSP_RX_PC_DAT_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_DAT_PHITCNT,M_BCM1480_HSP_RX_PC_DAT_PHITCNT) 740 741 /* 742 * TX HTCC Buffer Allocation Registers (Table 370) 743 */ 744 745 #define S_BCM1480_HSP_TX_HTCC_PRB_PHITCNT 0 746 #define M_BCM1480_HSP_TX_HTCC_PRB_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_PRB_PHITCNT) 747 #define V_BCM1480_HSP_TX_HTCC_PRB_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_PRB_PHITCNT) 748 #define G_BCM1480_HSP_TX_HTCC_PRB_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_PRB_PHITCNT,M_BCM1480_HSP_TX_HTCC_PRB_PHITCNT) 749 750 #define S_BCM1480_HSP_TX_HTCC_ACK_PHITCNT 8 751 #define M_BCM1480_HSP_TX_HTCC_ACK_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_ACK_PHITCNT) 752 #define V_BCM1480_HSP_TX_HTCC_ACK_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_ACK_PHITCNT) 753 #define G_BCM1480_HSP_TX_HTCC_ACK_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_ACK_PHITCNT,M_BCM1480_HSP_TX_HTCC_ACK_PHITCNT) 754 755 #define S_BCM1480_HSP_TX_HTCC_WB_PHITCNT 24 756 #define M_BCM1480_HSP_TX_HTCC_WB_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_WB_PHITCNT) 757 #define V_BCM1480_HSP_TX_HTCC_WB_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_WB_PHITCNT) 758 #define G_BCM1480_HSP_TX_HTCC_WB_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_WB_PHITCNT,M_BCM1480_HSP_TX_HTCC_WB_PHITCNT) 759 760 #define S_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT 32 761 #define M_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT) 762 #define V_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT) 763 #define G_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT,M_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT) 764 765 #define S_BCM1480_HSP_TX_HTCC_CRD_PHITCNT 40 766 #define M_BCM1480_HSP_TX_HTCC_CRD_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_CRD_PHITCNT) 767 #define V_BCM1480_HSP_TX_HTCC_CRD_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_CRD_PHITCNT) 768 #define G_BCM1480_HSP_TX_HTCC_CRD_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_CRD_PHITCNT,M_BCM1480_HSP_TX_HTCC_CRD_PHITCNT) 769 770 /* 771 * TX Packet Buffer Allocation Registers (Table 371) 772 */ 773 774 #define S_BCM1480_HSP_TX_PHITCNT_0 0 775 #define M_BCM1480_HSP_TX_PHITCNT_0 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PHITCNT_0) 776 #define V_BCM1480_HSP_TX_PHITCNT_0(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PHITCNT_0) 777 #define G_BCM1480_HSP_TX_PHITCNT_0(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PHITCNT_0,M_BCM1480_HSP_TX_PHITCNT_0) 778 779 #define S_BCM1480_HSP_TX_PHITCNT_1 16 780 #define M_BCM1480_HSP_TX_PHITCNT_1 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PHITCNT_1) 781 #define V_BCM1480_HSP_TX_PHITCNT_1(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PHITCNT_1) 782 #define G_BCM1480_HSP_TX_PHITCNT_1(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PHITCNT_1,M_BCM1480_HSP_TX_RAMPHITCNT_1) 783 784 #define S_BCM1480_HSP_TX_PHITCNT_2 32 785 #define M_BCM1480_HSP_TX_PHITCNT_2 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PHITCNT_2) 786 #define V_BCM1480_HSP_TX_PHITCNT_2(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PHITCNT_2) 787 #define G_BCM1480_HSP_TX_PHITCNT_2(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PHITCNT_2,M_BCM1480_HSP_TX_PHITCNT_2) 788 789 #define S_BCM1480_HSP_TX_PHITCNT_3 48 790 #define M_BCM1480_HSP_TX_PHITCNT_3 _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PHITCNT_3) 791 #define V_BCM1480_HSP_TX_PHITCNT_3(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PHITCNT_3) 792 #define G_BCM1480_HSP_TX_PHITCNT_3(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PHITCNT_3,M_BCM1480_HSP_TX_RAMPHITCNT_3) 793 794 /* 795 * TX Non-Posted Command (NPC) Allocation Register (Table 372) 796 */ 797 798 #define S_BCM1480_HSP_TX_NPC_PHITCNT 0 799 #define M_BCM1480_HSP_TX_NPC_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_TX_NPC_PHITCNT) 800 #define V_BCM1480_HSP_TX_NPC_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NPC_PHITCNT) 801 #define G_BCM1480_HSP_TX_NPC_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_NPC_PHITCNT,M_BCM1480_HSP_TX_NPC_PHITCNT) 802 803 #define S_BCM1480_HSP_TX_RSP_PHITCNT 24 804 #define M_BCM1480_HSP_TX_RSP_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RSP_PHITCNT) 805 #define V_BCM1480_HSP_TX_RSP_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RSP_PHITCNT) 806 #define G_BCM1480_HSP_TX_RSP_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_RSP_PHITCNT,M_BCM1480_HSP_TX_RSP_PHITCNT) 807 808 #define S_BCM1480_HSP_TX_PC_PHITCNT 48 809 #define M_BCM1480_HSP_TX_PC_PHITCNT _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PC_PHITCNT) 810 #define V_BCM1480_HSP_TX_PC_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PC_PHITCNT) 811 #define G_BCM1480_HSP_TX_PC_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_PC_PHITCNT,M_BCM1480_HSP_TX_PC_PHITCNT) 812 813 #define S_BCM1480_HSP_TX_NEXT_ADDR_EVEN 0 814 #define M_BCM1480_HSP_TX_NEXT_ADDR_EVEN _SB_MAKEMASK(32,S_BCM1480_HSP_TX_NEXT_ADDR_EVEN) 815 #define V_BCM1480_HSP_TX_NEXT_ADDR_EVEN(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NEXT_ADDR_EVEN) 816 #define G_BCM1480_HSP_TX_NEXT_ADDR_EVEN(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_NEXT_ADDR_EVEN,M_BCM1480_HSP_TX_NEXT_ADDR_EVEN) 817 818 #define S_BCM1480_HSP_TX_NEXT_ADDR_ODD 32 819 #define M_BCM1480_HSP_TX_NEXT_ADDR_ODD _SB_MAKEMASK(32,S_BCM1480_HSP_TX_NEXT_ADDR_ODD) 820 #define V_BCM1480_HSP_TX_NEXT_ADDR_ODD(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NEXT_ADDR_ODD) 821 #define G_BCM1480_HSP_TX_NEXT_ADDR_ODD(x) _SB_GETVALUE(x,S_BCM1480_HSP_TX_NEXT_ADDR_ODD,M_BCM1480_HSP_TX_NEXT_ADDR_ODD) 822 823 /* 824 * TX HTCC Physical Unot Count (Table 373) 825 */ 826 827 /* See definitions for table 370. */ 828 829 /* ********************************************************************* 830 * Managability/Testability registers 831 * BROADCOM USE ONLY 832 ********************************************************************* */ 833 834 /* 835 * RX PLL Config (Table 374) 836 * BROADCOM USE ONLY 837 */ 838 839 #define S_BCM1480_HSP_RXPLL_FREQF_SEL 0 840 #define M_BCM1480_HSP_RXPLL_FREQF_SEL _SB_MAKEMASK(4,S_BCM1480_HSP_RXPLL_FREQF_SEL) 841 #define V_BCM1480_HSP_RXPLL_FREQF_SEL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_FREQF_SEL) 842 #define G_BCM1480_HSP_RXPLL_FREQF_SEL(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_FREQF_SEL,M_BCM1480_HSP_RXPLL_FREQF_SEL) 843 844 #define S_BCM1480_HSP_RXPLL_FDBK_SEL 4 845 #define M_BCM1480_HSP_RXPLL_FDBK_SEL _SB_MAKEMASK(4,S_BCM1480_HSP_RXPLL_FDBK_SEL) 846 #define V_BCM1480_HSP_RXPLL_FDBK_SEL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_FDBK_SEL) 847 #define G_BCM1480_HSP_RXPLL_FDBK_SEL(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_FDBK_SEL,M_BCM1480_HSP_RXPLL_FDBK_SEL) 848 849 #define S_BCM1480_HSP_RXPLL_VCO_RANGE 8 850 #define M_BCM1480_HSP_RXPLL_VCO_RANGE _SB_MAKEMASK(2,S_BCM1480_HSP_RXPLL_VCO_RANGE) 851 #define V_BCM1480_HSP_RXPLL_VCO_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_VCO_RANGE) 852 #define G_BCM1480_HSP_RXPLL_VCO_RANGE(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_VCO_RANGE,M_BCM1480_HSP_RXPLL_VCO_RANGE) 853 854 #define M_BCM1480_HSP_RXPLL_DIV4 _SB_MAKEMASK1(10) 855 #define M_BCM1480_HSP_RXPLL_PLLOVERRIDE _SB_MAKEMASK1(12) 856 #define M_BCM1480_HSP_RXPLL_VCOOVERRIDE _SB_MAKEMASK1(13) 857 858 #define S_BCM1480_HSP_RXPLL_RX_PLLTEST 14 859 #define M_BCM1480_HSP_RXPLL_RX_PLLTEST _SB_MAKEMASK(2,S_BCM1480_HSP_RXPLL_RX_PLLTEST) 860 #define V_BCM1480_HSP_RXPLL_RX_PLLTEST(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_RX_PLLTEST) 861 #define G_BCM1480_HSP_RXPLL_RX_PLLTEST(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_RX_PLLTEST,M_BCM1480_HSP_RXPLL_RX_PLLTEST) 862 863 #define S_BCM1480_HSP_RXPLL_RX_PLLCTRL 16 864 #define M_BCM1480_HSP_RXPLL_RX_PLLCTRL _SB_MAKEMASK(6,S_BCM1480_HSP_RXPLL_RX_PLLCTRL) 865 #define V_BCM1480_HSP_RXPLL_RX_PLLCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_RX_PLLCTRL) 866 #define G_BCM1480_HSP_RXPLL_RX_PLLCTRL(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_RX_PLLCTRL,M_BCM1480_HSP_RXPLL_RX_PLLCTRL) 867 868 869 /* 870 * TX PLL Config (Table 375) 871 * BROADCOM USE ONLY 872 */ 873 874 #define S_BCM1480_HSP_TXPLL_FREQF_SEL 0 875 #define M_BCM1480_HSP_TXPLL_FREQF_SEL _SB_MAKEMASK(4,S_BCM1480_HSP_TXPLL_FREQF_SEL) 876 #define V_BCM1480_HSP_TXPLL_FREQF_SEL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXPLL_FREQF_SEL) 877 #define G_BCM1480_HSP_TXPLL_FREQF_SEL(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXPLL_FREQF_SEL,M_BCM1480_HSP_TXPLL_FREQF_SEL) 878 879 #define S_BCM1480_HSP_TXPLL_FDBK_SEL 4 880 #define M_BCM1480_HSP_TXPLL_FDBK_SEL _SB_MAKEMASK(4,S_BCM1480_HSP_TXPLL_FDBK_SEL) 881 #define V_BCM1480_HSP_TXPLL_FDBK_SEL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXPLL_FDBK_SEL) 882 #define G_BCM1480_HSP_TXPLL_FDBK_SEL(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXPLL_FDBK_SEL,M_BCM1480_HSP_TXPLL_FDBK_SEL) 883 884 #define S_BCM1480_HSP_TXPLL_VCO_RANGE 8 885 #define M_BCM1480_HSP_TXPLL_VCO_RANGE _SB_MAKEMASK(2,S_BCM1480_HSP_TXPLL_VCO_RANGE) 886 #define V_BCM1480_HSP_TXPLL_VCO_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXPLL_VCO_RANGE) 887 #define G_BCM1480_HSP_TXPLL_VCO_RANGE(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXPLL_VCO_RANGE,M_BCM1480_HSP_TXPLL_VCO_RANGE) 888 889 #define M_BCM1480_HSP_TXPLL_DIV4 _SB_MAKEMASK1(10) 890 #define M_BCM1480_HSP_TXPLL_ESTOREDEPTH8 _SB_MAKEMASK1(11) 891 #define M_BCM1480_HSP_TXPLL_PLLOVERRIDE _SB_MAKEMASK1(12) 892 #define M_BCM1480_HSP_TXPLL_VCOOVERRIDE _SB_MAKEMASK1(13) 893 894 #define S_BCM1480_HSP_TXPLL_TX_PLLTEST 14 895 #define M_BCM1480_HSP_TXPLL_TX_PLLTEST _SB_MAKEMASK(2,S_BCM1480_HSP_TXPLL_TX_PLLTEST) 896 #define V_BCM1480_HSP_TXPLL_TX_PLLTEST(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXPLL_TX_PLLTEST) 897 #define G_BCM1480_HSP_TXPLL_TX_PLLTEST(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXPLL_TX_PLLTEST,M_BCM1480_HSP_TXPLL_TX_PLLTEST) 898 899 #define S_BCM1480_HSP_TXPLL_TX_PLLCTRL 16 900 #define M_BCM1480_HSP_TXPLL_TX_PLLCTRL _SB_MAKEMASK(6,S_BCM1480_HSP_TXPLL_TX_PLLCTRL) 901 #define V_BCM1480_HSP_TXPLL_TX_PLLCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXPLL_TX_PLLCTRL) 902 #define G_BCM1480_HSP_TXPLL_TX_PLLCTRL(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXPLL_TX_PLLCTRL,M_BCM1480_HSP_TXPLL_TX_PLLCTRL) 903 904 /* 905 * RX and TX calibration registers (Table 376) 906 * BROADCOM USE ONLY 907 */ 908 909 #define M_BCM1480_HSP_CAL_STARTCAL2 _SB_MAKEMASK1(0) 910 #define M_BCM1480_HSP_CAL_PDTEST _SB_MAKEMASK1(1) 911 #define M_BCM1480_HSP_CAL_CALFIN _SB_MAKEMASK1(2) 912 #define M_BCM1480_HSP_CAL_S100M66M _SB_MAKEMASK1(3) 913 #define M_BCM1480_HSP_CAL_NO_CALIB _SB_MAKEMASK1(4) 914 915 #define S_BCM1480_HSP_CAL_BMODE 5 916 #define M_BCM1480_HSP_CAL_BMODE _SB_MAKEMASK(2,S_BCM1480_HSP_CAL_BMODE) 917 #define V_BCM1480_HSP_CAL_BMODE(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_CAL_BMODE) 918 #define G_BCM1480_HSP_CAL_BMODE(x) _SB_GETVALUE(x,S_BCM1480_HSP_CAL_BMODE,M_BCM1480_HSP_CAL_BMODE) 919 920 #define S_BCM1480_HSP_CAL_CALSETP 8 921 #define M_BCM1480_HSP_CAL_CALSETP _SB_MAKEMASK(4,S_BCM1480_HSP_CAL_CALSETP) 922 #define V_BCM1480_HSP_CAL_CALSETP(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_CAL_CALSETP) 923 #define G_BCM1480_HSP_CAL_CALSETP(x) _SB_GETVALUE(x,S_BCM1480_HSP_CAL_CALSETP,M_BCM1480_HSP_CAL_CALSETP) 924 925 #define S_BCM1480_HSP_CAL_CALSETN 12 926 #define M_BCM1480_HSP_CAL_CALSETN _SB_MAKEMASK(4,S_BCM1480_HSP_CAL_CALSETN) 927 #define V_BCM1480_HSP_CAL_CALSETN(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_CAL_CALSETN) 928 #define G_BCM1480_HSP_CAL_CALSETN(x) _SB_GETVALUE(x,S_BCM1480_HSP_CAL_CALSETN,M_BCM1480_HSP_CAL_CALSETN) 929 930 #define S_BCM1480_HSP_CAL_CALPSTAT 16 931 #define M_BCM1480_HSP_CAL_CALPSTAT _SB_MAKEMASK(4,S_BCM1480_HSP_CAL_CALPSTAT) 932 #define V_BCM1480_HSP_CAL_CALPSTAT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_CAL_CALPSTAT) 933 #define G_BCM1480_HSP_CAL_CALPSTAT(x) _SB_GETVALUE(x,S_BCM1480_HSP_CAL_CALPSTAT,M_BCM1480_HSP_CAL_CALPSTAT) 934 935 #define S_BCM1480_HSP_CAL_CALNSTAT 20 936 #define M_BCM1480_HSP_CAL_CALNSTAT _SB_MAKEMASK(4,S_BCM1480_HSP_CAL_CALNSTAT) 937 #define V_BCM1480_HSP_CAL_CALNSTAT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_CAL_CALNSTAT) 938 #define G_BCM1480_HSP_CAL_CALNSTAT(x) _SB_GETVALUE(x,S_BCM1480_HSP_CAL_CALNSTAT,M_BCM1480_HSP_CAL_CALNSTAT) 939 940 941 /* 942 * RX Testability (Table 377) 943 * BROADCOM USE ONLY 944 */ 945 946 947 #define S_BCM1480_HSP_RXTST_EWRAP 1 948 #define M_BCM1480_HSP_RXTST_EWRAP _SB_MAKEMASK(2,S_BCM1480_HSP_RXTST_EWRAP) 949 #define V_BCM1480_HSP_RXTST_EWRAP(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXTST_EWRAP) 950 #define G_BCM1480_HSP_RXTST_EWRAP(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXTST_EWRAP,M_BCM1480_HSP_RXTST_EWRAP) 951 952 #define M_BCM1480_HSP_RXTST_RXDLL_FREEZE _SB_MAKEMASK1(4) 953 #define M_BCM1480_HSP_RXTST_TX_PLL_BYPASS _SB_MAKEMASK1(5) 954 #define M_BCM1480_HSP_RXTST_RX_PLL_BYPASS _SB_MAKEMASK1(6) 955 #define M_BCM1480_HSP_RXTST_DLL_CHRESET_ENABLE _SB_MAKEMASK1(7) 956 957 #define S_BCM1480_HSP_RXTST_RX_ICNTRL 8 958 #define M_BCM1480_HSP_RXTST_RX_ICNTRL _SB_MAKEMASK(12,S_BCM1480_HSP_RXTST_RX_ICNTRL) 959 #define V_BCM1480_HSP_RXTST_RX_ICNTRL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXTST_RX_ICNTRL) 960 #define G_BCM1480_HSP_RXTST_RX_ICNTRL(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXTST_RX_ICNTRL,M_BCM1480_HSP_RXTST_RX_ICNTRL) 961 962 #define S_BCM1480_HSP_RXTST_RX_RCNTRL 20 963 #define M_BCM1480_HSP_RXTST_RX_RCNTRL _SB_MAKEMASK(3,S_BCM1480_HSP_RXTST_RX_RCNTRL) 964 #define V_BCM1480_HSP_RXTST_RX_RCNTRL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXTST_RX_RCNTRL) 965 #define G_BCM1480_HSP_RXTST_RX_RCNTRL(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXTST_RX_RCNTRL,M_BCM1480_HSP_RXTST_RX_RCNTRL) 966 967 #define S_BCM1480_HSP_RXTST_RX_GCNTRL 24 968 #define M_BCM1480_HSP_RXTST_RX_GCNTRL _SB_MAKEMASK(3,S_BCM1480_HSP_RXTST_RX_GCNTRL) 969 #define V_BCM1480_HSP_RXTST_RX_GCNTRL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXTST_RX_GCNTRL) 970 #define G_BCM1480_HSP_RXTST_RX_GCNTRL(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXTST_RX_GCNTRL,M_BCM1480_HSP_RXTST_RX_GCNTRL) 971 972 #define S_BCM1480_HSP_RXTST_RX_OORCNTRL 28 973 #define M_BCM1480_HSP_RXTST_RX_OORCNTRL _SB_MAKEMASK(2,S_BCM1480_HSP_RXTST_RX_OORCNTRL) 974 #define V_BCM1480_HSP_RXTST_RX_OORCNTRL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXTST_RX_OORCNTRL) 975 #define G_BCM1480_HSP_RXTST_RX_OORCNTRL(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXTST_RX_OORCNTRL,M_BCM1480_HSP_RXTST_RX_OORCNTRL) 976 977 #define S_BCM1480_HSP_RXTST_RX_CNTRL 32 978 #define M_BCM1480_HSP_RXTST_RX_CNTRL _SB_MAKEMASK(3,S_BCM1480_HSP_RXTST_RX_CNTRL) 979 #define V_BCM1480_HSP_RXTST_RX_CNTRL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXTST_RX_CNTRL) 980 #define G_BCM1480_HSP_RXTST_RX_CNTRL(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXTST_RX_CNTRL,M_BCM1480_HSP_RXTST_RX_CNTRL) 981 982 #define S_BCM1480_HSP_RXTST_RX_LPBK_PHASE_SEL_RXA 35 983 #define M_BCM1480_HSP_RXTST_RX_LPBK_PHASE_SEL_RXA _SB_MAKEMASK(3,S_BCM1480_HSP_RXTST_RX_LPBK_PHASE_SEL_RXA) 984 #define V_BCM1480_HSP_RXTST_RX_LPBK_PHASE_SEL_RXA(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXTST_RX_LPBK_PHASE_SEL_RXA) 985 #define G_BCM1480_HSP_RXTST_RX_LPBK_PHASE_SEL_RXA(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXTST_RX_LPBK_PHASE_SEL_RXA,M_BCM1480_HSP_RXTST_RX_LPBK_PHASE_SEL_RXA) 986 987 #define M_BCM1480_HSP_RXTST_DIP4_CHECK_DISABLE _SB_MAKEMASK1(38) 988 #define M_BCM1480_HSP_RXTST_EBUF_WREN _SB_MAKEMASK1(40) 989 #define M_BCM1480_HSP_RXTST_DIGITAL_LOOPBACK _SB_MAKEMASK1(41) 990 #define M_BCM1480_HSP_RXTST_EBUF_BURST_MODE _SB_MAKEMASK1(42) 991 #define M_BCM1480_HSP_RXTST_RESET_STOP_STREAM _SB_MAKEMASK1(43) 992 993 #define S_BCM1480_HSP_RXTST_RX_BIAS 44 994 #define M_BCM1480_HSP_RXTST_RX_BIAS _SB_MAKEMASK(2,S_BCM1480_HSP_RXTST_RX_BIAS) 995 #define V_BCM1480_HSP_RXTST_RX_BIAS(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXTST_RX_BIAS) 996 #define G_BCM1480_HSP_RXTST_RX_BIAS(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXTST_RX_BIAS,M_BCM1480_HSP_RXTST_RX_BIAS) 997 998 /* 999 * TX Testability (Table 378) 1000 * BROADCOM USE ONLY 1001 */ 1002 1003 #define S_BCM1480_HSP_TXTST_CTL 0 1004 #define M_BCM1480_HSP_TXTST_CTL _SB_MAKEMASK(3,S_BCM1480_HSP_TXTST_CTL) 1005 #define V_BCM1480_HSP_TXTST_CTL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXTST_CTL) 1006 #define G_BCM1480_HSP_TXTST_CTL(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXTST_CTL,M_BCM1480_HSP_TXTST_CTL) 1007 1008 #define S_BCM1480_HSP_TXTST_BIAS 4 1009 #define M_BCM1480_HSP_TXTST_BIAS _SB_MAKEMASK(4,S_BCM1480_HSP_TXTST_BIAS) 1010 #define V_BCM1480_HSP_TXTST_BIAS(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXTST_BIAS) 1011 #define G_BCM1480_HSP_TXTST_BIAS(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXTST_BIAS,M_BCM1480_HSP_TXTST_BIAS) 1012 1013 #define S_BCM1480_HSP_TXTST_VCOM_CTL 8 1014 #define M_BCM1480_HSP_TXTST_VCOM_CTL _SB_MAKEMASK(4,S_BCM1480_HSP_TXTST_VCOM_CTL) 1015 #define V_BCM1480_HSP_TXTST_VCOM_CTL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXTST_VCOM_CTL) 1016 #define G_BCM1480_HSP_TXTST_VCOM_CTL(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXTST_VCOM_CTL,M_BCM1480_HSP_TXTST_VCOM_CTL) 1017 1018 #define S_BCM1480_HSP_TXTST_MUX_CTL 12 1019 #define M_BCM1480_HSP_TXTST_MUX_CTL _SB_MAKEMASK(4,S_BCM1480_HSP_TXTST_MUX_CTL) 1020 #define V_BCM1480_HSP_TXTST_MUX_CTL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXTST_MUX_CTL) 1021 #define G_BCM1480_HSP_TXTST_MUX_CTL(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXTST_MUX_CTL,M_BCM1480_HSP_TXTST_MUX_CTL) 1022 1023 #define S_BCM1480_HSP_TXTST_SLEWP_CTL 16 1024 #define M_BCM1480_HSP_TXTST_SLEWP_CTL _SB_MAKEMASK(2,S_BCM1480_HSP_TXTST_SLEWP_CTL) 1025 #define V_BCM1480_HSP_TXTST_SLEWP_CTL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXTST_SLEWP_CTL) 1026 #define G_BCM1480_HSP_TXTST_SLEWP_CTL(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXTST_SLEWP_CTL,M_BCM1480_HSP_TXTST_SLEWP_CTL) 1027 1028 #define S_BCM1480_HSP_TXTST_SLEWN_CTL 18 1029 #define M_BCM1480_HSP_TXTST_SLEWN_CTL _SB_MAKEMASK(2,S_BCM1480_HSP_TXTST_SLEWN_CTL) 1030 #define V_BCM1480_HSP_TXTST_SLEWN_CTL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXTST_SLEWN_CTL) 1031 #define G_BCM1480_HSP_TXTST_SLEWN_CTL(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXTST_SLEWN_CTL,M_BCM1480_HSP_TXTST_SLEWN_CTL) 1032 1033 #define S_BCM1480_HSP_TXTST_CURR_CTL 20 1034 #define M_BCM1480_HSP_TXTST_CURR_CTL _SB_MAKEMASK(2,S_BCM1480_HSP_TXTST_CURR_CTL) 1035 #define V_BCM1480_HSP_TXTST_CURR_CTL(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXTST_CURR_CTL) 1036 #define G_BCM1480_HSP_TXTST_CURR_CTL(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXTST_CURR_CTL,M_BCM1480_HSP_TXTST_CURR_CTL) 1037 1038 /* 1039 * XXX TBD: TABLES 379, 380, 381 1040 * BROADCOM USE ONLY 1041 */ 1042 1043 /* 1044 * RX RAM Visibility (Table 382, 383) 1045 * BROADCOM USE ONLY 1046 */ 1047 1048 #define S_BCM1480_HSP_RXVIS_RAM 0 1049 #define M_BCM1480_HSP_RXVIS_RAM _SB_MAKEMASK(3,S_BCM1480_HSP_RXVIS_RAM) 1050 #define V_BCM1480_HSP_RXVIS_RAM(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXVIS_RAM) 1051 #define G_BCM1480_HSP_RXVIS_RAM(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXVIS_RAM,M_BCM1480_HSP_RXVIS_RAM) 1052 1053 #define K_BCM1480_HSP_RXVIS_RAM_ERAM 0 1054 #define K_BCM1480_HSP_RXVIS_RAM_HRAM 1 1055 #define K_BCM1480_HSP_RXVIS_RAM_DRAM_0_63 3 1056 #define K_BCM1480_HSP_RXVIS_RAM_DRAM_64_127 4 1057 #define K_BCM1480_HSP_RXVIS_RAM_DRAM_128_151 5 1058 1059 #define S_BCM1480_HSP_RXVIS_RAM_ADDR 16 1060 #define M_BCM1480_HSP_RXVIS_RAM_ADDR _SB_MAKEMASK(16,S_BCM1480_HSP_RXVIS_RAM_ADDR) 1061 #define V_BCM1480_HSP_RXVIS_RAM_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXVIS_RAM_ADDR) 1062 #define G_BCM1480_HSP_RXVIS_RAM_ADDR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXVIS_RAM_ADDR,M_BCM1480_HSP_RXVIS_RAM_ADDR) 1063 1064 1065 /* 1066 * RX RF RAM Visibility (Table 384, 385) 1067 * BROADCOM USE ONLY 1068 */ 1069 1070 #define S_BCM1480_HSP_RXRFVIS_RAM 0 1071 #define M_BCM1480_HSP_RXRFVIS_RAM _SB_MAKEMASK(4,S_BCM1480_HSP_RXRFVIS_RAM) 1072 #define V_BCM1480_HSP_RXRFVIS_RAM(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXRFVIS_RAM) 1073 #define G_BCM1480_HSP_RXRFVIS_RAM(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXRFVIS_RAM,M_BCM1480_HSP_RXRFVIS_RAM) 1074 1075 #define K_BCM1480_HSP_RXRFVIS_RAM_REASS_0_63 0 1076 #define K_BCM1480_HSP_RXRFVIS_RAM_REASS_64_127 1 1077 #define K_BCM1480_HSP_RXRFVIS_RAM_REASS_META 2 1078 #define K_BCM1480_HSP_RXRFVIS_RAM_PL12_RF 3 1079 #define K_BCM1480_HSP_RXRFVIS_RAM_PL12_FLOPS 4 1080 #define K_BCM1480_HSP_RXRFVIS_RAM_HEADPTRARRAY 5 1081 #define K_BCM1480_HSP_RXRFVIS_RAM_TAILPTRARRAY 6 1082 #define K_BCM1480_HSP_RXRFVIS_RAM_PRECABVAL 7 1083 #define K_BCM1480_HSP_RXRFVIS_RAM_PHITCNTARRAY 8 1084 1085 #define S_BCM1480_HSP_RXRFVIS_RAM_ADDR 8 1086 #define M_BCM1480_HSP_RXRFVIS_RAM_ADDR _SB_MAKEMASK(8,S_BCM1480_HSP_RXRFVIS_RAM_ADDR) 1087 #define V_BCM1480_HSP_RXRFVIS_RAM_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RXRFVIS_RAM_ADDR) 1088 #define G_BCM1480_HSP_RXRFVIS_RAM_ADDR(x) _SB_GETVALUE(x,S_BCM1480_HSP_RXRFVIS_RAM_ADDR,M_BCM1480_HSP_RXRFVIS_RAM_ADDR) 1089 1090 1091 /* 1092 * XXX TBD: Tables 386, 387, 388, 389 1093 * BROADCOM USE ONLY 1094 */ 1095 1096 /* 1097 * TX RAM Visibility (Table 390, 391) 1098 * BROADCOM USE ONLY 1099 */ 1100 1101 #define S_BCM1480_HSP_TXVIS_RAM 0 1102 #define M_BCM1480_HSP_TXVIS_RAM _SB_MAKEMASK(3,S_BCM1480_HSP_TXVIS_RAM) 1103 #define V_BCM1480_HSP_TXVIS_RAM(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXVIS_RAM) 1104 #define G_BCM1480_HSP_TXVIS_RAM(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXVIS_RAM,M_BCM1480_HSP_TXVIS_RAM) 1105 1106 #define K_BCM1480_HSP_TXVIS_RAM_DRAM_0_63 0 1107 #define K_BCM1480_HSP_TXVIS_RAM_DRAM_64_127 1 1108 #define K_BCM1480_HSP_TXVIS_RAM_DRAM_128_151 2 1109 1110 #define S_BCM1480_HSP_TXVIS_RAM_ADDR 16 1111 #define M_BCM1480_HSP_TXVIS_RAM_ADDR _SB_MAKEMASK(16,S_BCM1480_HSP_TXVIS_RAM_ADDR) 1112 #define V_BCM1480_HSP_TXVIS_RAM_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXVIS_RAM_ADDR) 1113 #define G_BCM1480_HSP_TXVIS_RAM_ADDR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXVIS_RAM_ADDR,M_BCM1480_HSP_TXVIS_RAM_ADDR) 1114 1115 1116 /* 1117 * TX RF RAM Visibility (Table 392,393) 1118 * BROADCOM USE ONLY 1119 */ 1120 1121 #define S_BCM1480_HSP_TXRFVIS_RAM 0 1122 #define M_BCM1480_HSP_TXRFVIS_RAM _SB_MAKEMASK(4,S_BCM1480_HSP_TXRFVIS_RAM) 1123 #define V_BCM1480_HSP_TXRFVIS_RAM(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXRFVIS_RAM) 1124 #define G_BCM1480_HSP_TXRFVIS_RAM(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXRFVIS_RAM,M_BCM1480_HSP_TXRFVIS_RAM) 1125 1126 #define K_BCM1480_HSP_TXRFVIS_RAM_HEADPTRARRAY 0 1127 #define K_BCM1480_HSP_TXRFVIS_RAM_TAILPTRARRAY 1 1128 #define K_BCM1480_HSP_TXRFVIS_RAM_RFEVENDATA_0_63 2 1129 #define K_BCM1480_HSP_TXRFVIS_RAM_RFEVENDATA_64_71 3 1130 #define K_BCM1480_HSP_TXRFVIS_RAM_RFEVENMETADATA 4 1131 #define K_BCM1480_HSP_TXRFVIS_RAM_RFODDDATA_0_63 5 1132 #define K_BCM1480_HSP_TXRFVIS_RAM_RFODDDATA_64_71 6 1133 #define K_BCM1480_HSP_TXRFVIS_RAM_RFODDMETADATA 7 1134 #define K_BCM1480_HSP_TXRFVIS_RAM_PHITCNTARRAY 8 1135 #define K_BCM1480_HSP_TXRFVIS_RAM_PUSHPOP 9 1136 #define K_BCM1480_HSP_TXRFVIS_RAM_IVCOK 10 1137 1138 #define S_BCM1480_HSP_TXRFVIS_RAM_ADDR 8 1139 #define M_BCM1480_HSP_TXRFVIS_RAM_ADDR _SB_MAKEMASK(8,S_BCM1480_HSP_TXRFVIS_RAM_ADDR) 1140 #define V_BCM1480_HSP_TXRFVIS_RAM_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_TXRFVIS_RAM_ADDR) 1141 #define G_BCM1480_HSP_TXRFVIS_RAM_ADDR(x) _SB_GETVALUE(x,S_BCM1480_HSP_TXRFVIS_RAM_ADDR,M_BCM1480_HSP_TXRFVIS_RAM_ADDR) 1142 1143 1144 #endif /* _BCM1480_HSP_H */ 1145