1 /* ********************************************************************* 2 * BCM1280/BCM1480 Board Support Package 3 * 4 * HT Device constants File: bcm1480_ht.h 5 * 6 * This module contains constants and macros to describe 7 * the HT interface on the BCM1280/BCM1480. 8 * 9 * BCM1480 specification level: 1X55_1X80-UM100-R (12/18/03) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49 #ifndef _BCM1480_HT_H 50 #define _BCM1480_HT_H 51 52 #include "sb1250_defs.h" 53 54 55 /* 56 * The following definitions refer to PCI Configuration Space of the 57 * HyperTransport Device Host Bridge (HTD). All registers are 32 bits. 58 */ 59 60 /* 61 * HT Interface Device Configuration Header (Table 130) 62 * The first 64 bytes are a standard Type 0 header. Only 63 * device-specific extensions are defined here. 64 */ 65 66 #define R_BCM1480_HTD_ERRORINT 0x0084 67 #define R_BCM1480_HTD_SPECCMDSTAT 0x0088 68 #define R_BCM1480_HTD_SUBSYSSET 0x008C 69 #define R_BCM1480_HTD_TGTDONE 0x0090 70 #define R_BCM1480_HTD_VENDORIDSET 0x009C 71 #define R_BCM1480_HTD_CLASSREVSET 0x00A0 72 #define R_BCM1480_HTD_ISOCBAR 0x00A4 73 #define R_BCM1480_HTD_ISOCBARMASK 0x00A8 74 #define R_BCM1480_HTD_MAPBASE 0x00B0 /* 0xB0 through 0xEC - map table */ 75 #define HTD_MAPENTRIES 16 /* 64 bytes, 16 entries */ 76 #define R_BCM1480_HTD_MAP(n) (R_BCM1480_HTD_MAPBASE + (n)*4) 77 #define R_BCM1480_HTD_INTBUSCTRL 0x00F0 78 #define R_BCM1480_HTD_PORTSCTRL 0x00F4 79 80 81 /* 82 * HT Device Error and Interrupt Register (Table 133) 83 */ 84 85 #define M_BCM1480_HTD_INT_BUS_ERR _SB_MAKEMASK1_32(0) 86 #define M_BCM1480_HTD_PORT0_DOWN_ERR _SB_MAKEMASK1_32(8) 87 #define M_BCM1480_HTD_PORT1_DOWN_ERR _SB_MAKEMASK1_32(9) 88 #define M_BCM1480_HTD_PORT2_DOWN_ERR _SB_MAKEMASK1_32(10) 89 #define M_BCM1480_HTD_INT_BUS_DOWN_ERR _SB_MAKEMASK1_32(12) 90 #define M_BCM1480_HTD_INT_BUS_ERR_INT_EN _SB_MAKEMASK1_32(16) 91 #define M_BCM1480_HTD_PORT0_DOWN_INT_EN _SB_MAKEMASK1_32(24) 92 #define M_BCM1480_HTD_PORT1_DOWN_INT_EN _SB_MAKEMASK1_32(25) 93 #define M_BCM1480_HTD_PORT2_DOWN_INT_EN _SB_MAKEMASK1_32(26) 94 #define M_BCM1480_HTD_INT_BUS_DOWN_INT_EN _SB_MAKEMASK1_32(28) 95 96 /* 97 * HT Device Specific Command and Status Register (Table 134) 98 */ 99 100 #define M_BCM1480_HTD_CMD_LOW_RANGE_EN _SB_MAKEMASK1_32(0) 101 #define M_BCM1480_HTD_CMD_LOW_RANGE_SPLIT _SB_MAKEMASK1_32(1) 102 #define M_BCM1480_HTD_CMD_FULL_BAR_EN _SB_MAKEMASK1_32(2) 103 #define M_BCM1480_HTD_CMD_FULL_BAR_SPLIT _SB_MAKEMASK1_32(3) 104 #define M_BCM1480_HTD_CMD_MSTR_ABORT_MODE _SB_MAKEMASK1_32(5) 105 106 /* 107 * HT Device Target Done Register (Table 135) 108 */ 109 110 #define S_BCM1480_HTD_TGT_DONE_COUNTER 0 111 #define M_BCM1480_HTD_TGT_DONE_COUNTER _SB_MAKEMASK_32(8,S_BCM1480_HTD_TGT_DONE_COUNTER) 112 #define V_BCM1480_HTD_TGT_DONE_COUNTER(x) _SB_MAKEVALUE_32(x,S_BCM1480_HTD_TGT_DONE_COUNTER) 113 #define G_BCM1480_HTD_TGT_DONE_COUNTER(x) _SB_GETVALUE_32(x,S_BCM1480_HTD_TGT_DONE_COUNTER,M_BCM1480_HTD_TGT_DONE_COUNTER) 114 115 /* 116 * HT Device Isochronous BAR Register (Table 136) 117 */ 118 119 #define M_BCM1480_HTD_ISOC_BAR_EN _SB_MAKEMASK1_32(0) 120 121 #define S_BCM1480_HTD_ISOC_BAR 1 122 #define M_BCM1480_HTD_ISOC_BAR _SB_MAKEMASK_32(31,S_BCM1480_HTD_ISOC_BAR) 123 #define V_BCM1480_HTD_ISOC_BAR(x) _SB_MAKEVALUE_32(x,S_BCM1480_HTD_ISOC_BAR) 124 #define G_BCM1480_HTD_ISOC_BAR(x) _SB_GETVALUE_32(x,S_BCM1480_HTD_ISOC_BAR,M_BCM1480_HTD_ISOC_BAR) 125 126 /* 127 * HT Device Isochronous Ignore Mask Register (Table 137) 128 */ 129 130 #define S_BCM1480_HTD_ISOC_IGN_MASK 1 131 #define M_BCM1480_HTD_ISOC_IGN_MASK _SB_MAKEMASK_32(31,S_BCM1480_HTD_ISOC_IGN_MASK) 132 #define V_BCM1480_HTD_ISOC_IGN_MASK(x) _SB_MAKEVALUE_32(x,S_BCM1480_HTD_ISOC_IGN_MASK) 133 #define G_BCM1480_HTD_ISOC_IGN_MASK(x) _SB_GETVALUE_32(x,S_BCM1480_HTD_ISOCBAR,M_BCM1480_HTD_ISOCBAR) 134 135 /* 136 * HT Device BAR0 Map Table Entry (Table 138) 137 */ 138 139 #define M_BCM1480_HTD_BAR0MAP_ENABLE _SB_MAKEMASK1_32(0) 140 #define M_BCM1480_HTD_BAR0MAP_L2CA _SB_MAKEMASK1_32(2) 141 #define M_BCM1480_HTD_BAR0MAP_ENDIAN _SB_MAKEMASK1_32(3) 142 143 #define S_BCM1480_HTD_BAR0MAP_ADDR 12 144 #define M_BCM1480_HTD_BAR0MAP_ADDR _SB_MAKEMASK_32(20,S_BCM1480_HTD_BAR0MAP_ADDR) 145 #define V_BCM1480_HTD_BAR0MAP_ADDR(x) _SB_MAKEVALUE_32(x,S_BCM1480_HTD_BAR0MAP_ADDR) 146 #define G_BCM1480_HTD_BAR0MAP_ADDR(x) _SB_GETVALUE_32(x,S_BCM1480_HTD_BAR0MAP_ADDR,M_BCM1480_HTD_BAR0MAP_ADDR) 147 148 /* 149 * HT Device Internal Bus Control and Status Register (Table 139) 150 */ 151 152 #define M_BCM1480_HTD_INTBUS_WARM_R _SB_MAKEMASK1_32(2) 153 #define M_BCM1480_HTD_INTBUS_RESET _SB_MAKEMASK1_32(3) 154 #define M_BCM1480_HTD_INTBUS_WARM_R_STATUS _SB_MAKEMASK1_32(4) 155 #define M_BCM1480_HTD_INTBUS_RESET_STATUS _SB_MAKEMASK1_32(5) 156 #define M_BCM1480_HTD_INTBUS_DET_SERR _SB_MAKEMASK1_32(8) 157 158 /* 159 * HT Device Ports Control and Status Register (Table 140) 160 */ 161 162 #define S_BCM1480_HTD_PORTCTRL_PORT0 0 163 #define M_BCM1480_HTD_PORTCTRL_PORT0 _SB_MAKEMASK_32(8,S_BCM1480_HTD_PORTCTRL_PORT0) 164 #define V_BCM1480_HTD_PORTCTRL_PORT0(x) _SB_MAKEVALUE_32(x,S_BCM1480_HTD_PORTCTRL_PORT0) 165 #define G_BCM1480_HTD_PORTCTRL_PORT0(x) _SB_GETVALUE_32(x,S_BCM1480_HTD_PORTCTRL_PORT0,M_BCM1480_HTD_PORTCTRL_PORT0) 166 167 #define S_BCM1480_HTD_PORTCTRL_PORT1 8 168 #define M_BCM1480_HTD_PORTCTRL_PORT1 _SB_MAKEMASK_32(8,S_BCM1480_HTD_PORTCTRL_PORT1) 169 #define V_BCM1480_HTD_PORTCTRL_PORT1(x) _SB_MAKEVALUE_32(x,S_BCM1480_HTD_PORTCTRL_PORT1) 170 #define G_BCM1480_HTD_PORTCTRL_PORT1(x) _SB_GETVALUE_32(x,S_BCM1480_HTD_PORTCTRL_PORT1,M_BCM1480_HTD_PORTCTRL_PORT1) 171 172 #define S_BCM1480_HTD_PORTCTRL_PORT2 16 173 #define M_BCM1480_HTD_PORTCTRL_PORT2 _SB_MAKEMASK_32(8,S_BCM1480_HTD_PORTCTRL_PORT2) 174 #define V_BCM1480_HTD_PORTCTRL_PORT2(x) _SB_MAKEVALUE_32(x,S_BCM1480_HTD_PORTCTRL_PORT2) 175 #define G_BCM1480_HTD_PORTCTRL_PORT2(x) _SB_GETVALUE_32(x,S_BCM1480_HTD_PORTCTRL_PORT2,M_BCM1480_HTD_PORTCTRL_PORT2) 176 177 #define S_BCM1480_HTD_PORTCTRL_PORTX(p) ((p)*8) 178 #define M_BCM1480_HTD_PORTCTRL_PORTX(p) _SB_MAKEMASK_32(8,S_BCM1480_HTD_PORTCTRL_PORTX(p)) 179 #define V_BCM1480_HTD_PORTCTRL_PORTX(p,x) _SB_MAKEVALUE_32(x,S_BCM1480_HTD_PORTCTRL_PORTX(p)) 180 #define G_BCM1480_HTD_PORTCTRL_PORTX(p,x) _SB_GETVALUE_32(x,S_BCM1480_HTD_PORTCTRL_PORTX(p),M_BCM1480_HTD_PORTCTRL_PORTX(p)) 181 182 /* The following fields are per port */ 183 #define M_BCM1480_HTD_PORT_ACTIVE _SB_MAKEMASK1_32(0) 184 #define M_BCM1480_HTD_PORT_IS_PRIMARY _SB_MAKEMASK1_32(1) 185 #define M_BCM1480_HTD_PORT_LINK_WARM_R _SB_MAKEMASK1_32(2) 186 #define M_BCM1480_HTD_PORT_LINK_RESET _SB_MAKEMASK1_32(3) 187 #define M_BCM1480_HTD_PORT_LINKWARMR_STATUS _SB_MAKEMASK1_32(4) 188 #define M_BCM1480_HTD_PORT_LINKRESET_STATUS _SB_MAKEMASK1_32(5) 189 190 191 /* 192 * HT Internal Bridge HTB Configuration Header (Tables 141 193 * and 163). The first 64 bytes are a standard Type 1 header. 194 * Only device-specific extensions are defined here. 195 * Note that Primary (Table 141) and Secondary (Table 163) formats 196 * are identical except for the HT Link Capability registers. 197 */ 198 199 #define R_BCM1480_HTB_LINKCAP 0x0040 200 #define R_BCM1480_HTB_LINKCTRL 0x0044 201 #define R_BCM1480_HTB_LINKFREQERR 0x0048 202 #define R_BCM1480_HTB_ERRHNDL 0x0050 203 #define R_BCM1480_HTB_SWITCHCAP 0x005C 204 #define R_BCM1480_HTB_SWITCHINFO 0x0064 205 #define R_BCM1480_HTB_VCSETCAP 0x0074 206 207 #define R_BCM1480_HTB_SPECBRCTRL 0x0088 208 #define R_BCM1480_HTB_SPECLINKFREQ 0x0090 209 #define R_BCM1480_HTB_VENDORIDSET 0x009C 210 #define R_BCM1480_HTB_NODEROUTING0 0x00B0 211 #define R_BCM1480_HTB_NODEROUTING1 0x00B4 212 213 214 /* 215 * HT Bridge Specific Bridge Link Control Register (Tables 156 and 178) 216 */ 217 218 #define M_BCM1480_HTB_LINKCTRL_CRCFLEN _SB_MAKEMASK1_32(1) 219 #define M_BCM1480_HTB_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4) 220 #define S_BCM1480_HTB_LINKCTRL_CRCERR 8 221 #define M_BCM1480_HTB_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_BCM1480_HTB_LINKCTRL_CRCERR) 222 223 /* 224 * HT Bridge Specific Bridge Link Frequency / Error Register (Tables 158 and 180) 225 */ 226 #define M_BCM1480_HTB_LINKFQERR_PROTERR _SB_MAKEMASK1_32(12) 227 #define M_BCM1480_HTB_LINKFQERR_OVFLERR _SB_MAKEMASK1_32(13) 228 #define M_BCM1480_HTB_LINKFQERR_EOCERR _SB_MAKEMASK1_32(14) 229 230 231 /* 232 * HT Bridge Specific Bridge Error Handling Register (Tables 161 and 182) 233 */ 234 #define M_BCM1480_HTB_ERRHNDL_PROFLEN _SB_MAKEMASK1_32(16) 235 #define M_BCM1480_HTB_ERRHNDL_OVFFLEN _SB_MAKEMASK1_32(17) 236 #define M_BCM1480_HTB_ERRHNDL_CHNFAIL _SB_MAKEMASK1_32(24) 237 #define M_BCM1480_HTB_ERRHNDL_RSPERR _SB_MAKEMASK1_32(25) 238 239 240 241 242 /* 243 * HT Bridge Specific Bridge Control Register (Tables 160 and 181) 244 */ 245 246 #define M_BCM1480_HTB_SPBRCTRL_SOUTH _SB_MAKEMASK1_32(0) 247 #define M_BCM1480_HTB_SPBRCTRL_NO_INTR_FORWARD _SB_MAKEMASK1_32(8) 248 249 /* 250 * HT Bridge Specific Link Frequency Control Register (Table 160) 251 */ 252 253 #define S_BCM1480_HTB_SPLINKFREQ_PLLFREQ 0 254 #define M_BCM1480_HTB_SPLINKFREQ_PLLFREQ _SB_MAKEMASK_32(5,S_BCM1480_HTB_SPLINKFREQ_PLLFREQ) 255 #define V_BCM1480_HTB_SPLINKFREQ_PLLFREQ(x) _SB_MAKEVALUE_32(x,S_BCM1480_HTB_SPLINKFREQ_PLLFREQ) 256 #define G_BCM1480_HTB_SPLINKFREQ_PLLFREQ(x) _SB_GETVALUE_32(x,S_BCM1480_HTB_SPLINKFREQ_PLLFREQ,M_BCM1480_HTB_SPLINKFREQ_PLLFREQ) 257 258 #define M_BCM1480_HTB_SPLINKFREQ_PLLDIV4 _SB_MAKEMASK1_32(5) 259 #define M_BCM1480_HTB_SPLINKFREQ_PLLCOMPAT _SB_MAKEMASK1_32(6) 260 #define M_BCM1480_HTB_SPLINKFREQ_SEQSTEP _SB_MAKEMASK1_32(7) 261 262 #define S_BCM1480_HTB_SPLINKFREQ_FREQCAPSET 16 263 #define M_BCM1480_HTB_SPLINKFREQ_FREQCAPSET _SB_MAKEMASK_32(16,S_BCM1480_HTB_SPLINKFREQ_FREQCAPSET) 264 #define V_BCM1480_HTB_SPLINKFREQ_FREQCAPSET(x) _SB_MAKEVALUE_32(x,S_BCM1480_HTB_SPLINKFREQ_FREQCAPSET) 265 #define G_BCM1480_HTB_SPLINKFREQ_FREQCAPSET(x) _SB_GETVALUE_32(x,S_BCM1480_HTB_SPLINKFREQ_FREQCAPSET,M_BCM1480_HTB_SPLINKFREQ_FREQCAPSET) 266 267 /* 268 * HT Bridge Node Routing Registers (Table 161) 269 */ 270 271 #define S_BCM1480_HTB_NODEROUTE(n) (4*(n)) 272 #define M_BCM1480_HTB_NODEROUTE(n) _SB_MAKEMASK_32(4,S_BCM1480_HTB_NODEROUTE(n)) 273 #define V_BCM1480_HTB_NODEROUTE(x,n) _SB_MAKEVALUE_32(x,S_BCM1480_HTB_NODEROUTE(n)) 274 #define G_BCM1480_HTB_NODEROUTE(x,n) _SB_GETVALUE_32(x,S_BCM1480_HTB_NODEROUTE(n),M_BCM1480_HTB_NODEROUTE(n)) 275 276 /* The following fields are per nibble */ 277 #define M_BCM1480_HTB_ROUTE_IS_ON_SEC_FOR_IO _SB_MAKEMASK1_32(0) 278 #define M_BCM1480_HTB_ROUTE_OVERRIDE_FOR_IO _SB_MAKEMASK1_32(1) 279 #define M_BCM1480_HTB_ROUTE_IS_ON_SEC_FOR_CC _SB_MAKEMASK1_32(2) 280 #define M_BCM1480_HTB_ROUTE_OVERRIDE_FOR_CC _SB_MAKEMASK1_32(3) 281 282 283 /* 284 * HT Bridge Switch Info Register Bits (Table 164) 285 */ 286 #define M_BCM1480_HTB_SWITCHINFO_HIDEPORT _SB_MAKEMASK1_32(23) 287 288 #endif /* _BCM1480_HT_H */ 289