1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * DMA definitions File: sb1250_dma.h 5 * 6 * This module contains constants and macros useful for 7 * programming the SB1250's DMA controllers, both the data mover 8 * and the Ethernet DMA. 9 * 10 * SB1250 specification level: User's manual 1/02/02 11 * 12 * Author: Mitch Lichtenberg (mpl@broadcom.com) 13 * 14 ********************************************************************* 15 * 16 * Copyright 2000,2001 17 * Broadcom Corporation. All rights reserved. 18 * 19 * This software is furnished under license and may be used and 20 * copied only in accordance with the following terms and 21 * conditions. Subject to these conditions, you may download, 22 * copy, install, use, modify and distribute modified or unmodified 23 * copies of this software in source and/or binary form. No title 24 * or ownership is transferred hereby. 25 * 26 * 1) Any source code used, modified or distributed must reproduce 27 * and retain this copyright notice and list of conditions as 28 * they appear in the source file. 29 * 30 * 2) No right is granted to use any trade name, trademark, or 31 * logo of Broadcom Corporation. Neither the "Broadcom 32 * Corporation" name nor any trademark or logo of Broadcom 33 * Corporation may be used to endorse or promote products 34 * derived from this software without the prior written 35 * permission of Broadcom Corporation. 36 * 37 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 38 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 39 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 40 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 41 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 42 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 44 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 45 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 46 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 47 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 48 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 ********************************************************************* */ 51 52 53 #ifndef _SB1250_DMA_H 54 #define _SB1250_DMA_H 55 56 57 #include "sb1250_defs.h" 58 59 /* ********************************************************************* 60 * DMA Registers 61 ********************************************************************* */ 62 63 /* 64 * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) 65 * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 66 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 67 * Registers: DMA_CONFIG0_SER_x_RX 68 * Registers: DMA_CONFIG0_SER_x_TX 69 */ 70 71 72 #define M_DMA_DROP _SB_MAKEMASK1(0) 73 74 #define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1) 75 #define M_DMA_RESERVED1 _SB_MAKEMASK1(2) 76 77 #define S_DMA_DESC_TYPE _SB_MAKE64(1) 78 #define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE) 79 #define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) 80 #define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) 81 82 #define K_DMA_DESC_TYPE_RING_AL 0 83 #define K_DMA_DESC_TYPE_CHAIN_AL 1 84 85 #if SIBYTE_HDR_FEATURE(112x, PASS3) 86 #define K_DMA_DESC_TYPE_RING_UAL_WI 2 87 #define K_DMA_DESC_TYPE_RING_UAL_RMW 3 88 #endif 89 90 #define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) 91 #define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) 92 #define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5) 93 #define M_DMA_TBX_EN _SB_MAKEMASK1(6) 94 #define M_DMA_TDX_EN _SB_MAKEMASK1(7) 95 96 #define S_DMA_INT_PKTCNT _SB_MAKE64(8) 97 #define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT) 98 #define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT) 99 #define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT) 100 101 #define S_DMA_RINGSZ _SB_MAKE64(16) 102 #define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ) 103 #define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ) 104 #define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ) 105 106 #define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) 107 #define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK) 108 #define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK) 109 #define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK) 110 111 #define S_DMA_LOW_WATERMARK _SB_MAKE64(48) 112 #define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK) 113 #define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK) 114 #define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK) 115 116 /* 117 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) 118 * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 119 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 120 * Registers: DMA_CONFIG1_SER_x_RX 121 * Registers: DMA_CONFIG1_SER_x_TX 122 */ 123 124 #define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0) 125 #define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1) 126 #define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2) 127 #define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3) 128 #define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) 129 #define M_DMA_L2CA _SB_MAKEMASK1(5) 130 131 #if SIBYTE_HDR_FEATURE(112x, PASS3) 132 #define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) 133 #define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) 134 #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) 135 #endif 136 137 #define M_DMA_MBZ1 _SB_MAKEMASK(6,15) 138 139 #define S_DMA_HDR_SIZE _SB_MAKE64(21) 140 #define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE) 141 #define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE) 142 #define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE) 143 144 #define M_DMA_MBZ2 _SB_MAKEMASK(5,32) 145 146 #define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) 147 #define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE) 148 #define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE) 149 #define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE) 150 151 #define S_DMA_INT_TIMEOUT _SB_MAKE64(48) 152 #define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT) 153 #define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT) 154 #define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT) 155 156 /* 157 * Ethernet and Serial DMA Descriptor base address (Table 7-6) 158 */ 159 160 #define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0) 161 162 163 /* 164 * ASIC Mode Base Address (Table 7-7) 165 */ 166 167 #define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0) 168 169 /* 170 * DMA Descriptor Count Registers (Table 7-8) 171 */ 172 173 /* No bitfields */ 174 175 176 /* 177 * Current Descriptor Address Register (Table 7-11) 178 */ 179 180 #define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) 181 #define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR) 182 #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) 183 #define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) 184 185 #if SIBYTE_HDR_FEATURE(112x, PASS3) 186 #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) 187 #endif 188 189 /* 190 * Receive Packet Drop Registers 191 */ 192 #if SIBYTE_HDR_FEATURE(112x, PASS3) 193 #define S_DMA_OODLOST_RX _SB_MAKE64(0) 194 #define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) 195 #define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) 196 197 #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) 198 #define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) 199 #define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) 200 #endif 201 202 /* ********************************************************************* 203 * DMA Descriptors 204 ********************************************************************* */ 205 206 /* 207 * Descriptor doubleword "A" (Table 7-12) 208 */ 209 210 #define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) 211 #define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET) 212 #define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET) 213 #define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET) 214 215 /* Note: Don't shift the address over, just mask it with the mask below */ 216 #define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) 217 #define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR) 218 219 #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) 220 221 #if SIBYTE_HDR_FEATURE(112x, PASS3) 222 #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) 223 #define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) 224 #endif 225 226 #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) 227 #define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) 228 #define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) 229 #define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) 230 231 #if SIBYTE_HDR_FEATURE(112x, PASS3) 232 #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) 233 #define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) 234 #define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) 235 #endif 236 237 #define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) 238 #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) 239 240 #define S_DMA_DSCRA_STATUS _SB_MAKE64(51) 241 #define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS) 242 #define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS) 243 #define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS) 244 245 /* 246 * Descriptor doubleword "B" (Table 7-13) 247 */ 248 249 250 #define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) 251 #define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS) 252 #define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) 253 #define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) 254 255 #if SIBYTE_HDR_FEATURE(112x, PASS3) 256 #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) 257 #define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) 258 #define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) 259 #define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) 260 #endif 261 262 #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) 263 264 /* Note: Don't shift the address over, just mask it with the mask below */ 265 #define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) 266 #define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR) 267 268 #define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) 269 #define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE) 270 #define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE) 271 #define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE) 272 273 #define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) 274 275 #if SIBYTE_HDR_FEATURE(112x, PASS3) 276 #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) 277 #define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) 278 #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) 279 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) 280 #endif 281 282 #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) 283 #define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) 284 #define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE) 285 #define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE) 286 287 /* 288 * from pass2 some bits in dscr_b are also used for rx status 289 */ 290 #define S_DMA_DSCRB_STATUS _SB_MAKE64(0) 291 #define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS) 292 #define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) 293 #define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) 294 295 /* 296 * Ethernet Descriptor Status Bits (Table 7-15) 297 */ 298 299 #define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) 300 #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) 301 302 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 303 /* Note: BADTCPCS is actually in DSCR_B options field */ 304 #define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) 305 #endif /* 1250 PASS2 || 112x PASS1 */ 306 307 #if SIBYTE_HDR_FEATURE(112x, PASS3) 308 #define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) 309 #define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) 310 #endif 311 312 #define S_DMA_ETHRX_RXCH 53 313 #define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) 314 #define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH) 315 #define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH) 316 317 #define S_DMA_ETHRX_PKTTYPE 55 318 #define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE) 319 #define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE) 320 #define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE) 321 322 #define K_DMA_ETHRX_PKTTYPE_IPV4 0 323 #define K_DMA_ETHRX_PKTTYPE_ARPV4 1 324 #define K_DMA_ETHRX_PKTTYPE_802 2 325 #define K_DMA_ETHRX_PKTTYPE_OTHER 3 326 #define K_DMA_ETHRX_PKTTYPE_USER0 4 327 #define K_DMA_ETHRX_PKTTYPE_USER1 5 328 #define K_DMA_ETHRX_PKTTYPE_USER2 6 329 #define K_DMA_ETHRX_PKTTYPE_USER3 7 330 331 #define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58) 332 #define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59) 333 #define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60) 334 #define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61) 335 #define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62) 336 #define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63) 337 338 /* 339 * Ethernet Transmit Status Bits (Table 7-16) 340 */ 341 342 #define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) 343 344 /* 345 * Ethernet Transmit Options (Table 7-17) 346 */ 347 348 #define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00) 349 #define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01) 350 #define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02) 351 #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03) 352 #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04) 353 #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05) 354 #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6) 355 #define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07) 356 #define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08) 357 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09) 358 #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A) 359 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B) 360 #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C) 361 #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D) 362 #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E) 363 #define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F) 364 365 /* 366 * Serial Receive Options (Table 7-18) 367 */ 368 #define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56) 369 #define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57) 370 #define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58) 371 #define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59) 372 #define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60) 373 #define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61) 374 #define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62) 375 #define M_DMA_SERRX_SOP _SB_MAKEMASK1(63) 376 377 /* 378 * Serial Transmit Status Bits (Table 7-20) 379 */ 380 381 #define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63) 382 383 /* 384 * Serial Transmit Options (Table 7-21) 385 */ 386 387 #define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0) 388 #define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1) 389 #define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2) 390 #define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3) 391 392 393 /* ********************************************************************* 394 * Data Mover Registers 395 ********************************************************************* */ 396 397 /* 398 * Data Mover Descriptor Base Address Register (Table 7-22) 399 * Register: DM_DSCR_BASE_0 400 * Register: DM_DSCR_BASE_1 401 * Register: DM_DSCR_BASE_2 402 * Register: DM_DSCR_BASE_3 403 */ 404 405 #define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0) 406 407 /* Note: Just mask the base address and then OR it in. */ 408 #define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) 409 #define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR) 410 411 #define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) 412 #define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ) 413 #define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ) 414 #define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ) 415 416 #define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) 417 #define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY) 418 #define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY) 419 #define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY) 420 421 #define K_DM_DSCR_BASE_PRIORITY_1 0 422 #define K_DM_DSCR_BASE_PRIORITY_2 1 423 #define K_DM_DSCR_BASE_PRIORITY_4 2 424 #define K_DM_DSCR_BASE_PRIORITY_8 3 425 #define K_DM_DSCR_BASE_PRIORITY_16 4 426 427 #define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59) 428 #define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60) 429 #define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */ 430 #define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */ 431 #define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) 432 #define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) 433 434 /* 435 * Data Mover Descriptor Count Register (Table 7-25) 436 */ 437 438 /* no bitfields */ 439 440 /* 441 * Data Mover Current Descriptor Address (Table 7-24) 442 * Register: DM_CUR_DSCR_ADDR_0 443 * Register: DM_CUR_DSCR_ADDR_1 444 * Register: DM_CUR_DSCR_ADDR_2 445 * Register: DM_CUR_DSCR_ADDR_3 446 */ 447 448 #define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) 449 #define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR) 450 451 #define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) 452 #define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT) 453 #define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT) 454 #define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\ 455 M_DM_CUR_DSCR_DSCR_COUNT) 456 457 458 #if SIBYTE_HDR_FEATURE(112x, PASS1) 459 /* 460 * Data Mover Channel Partial Result Registers 461 * Register: DM_PARTIAL_0 462 * Register: DM_PARTIAL_1 463 * Register: DM_PARTIAL_2 464 * Register: DM_PARTIAL_3 465 */ 466 #define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) 467 #define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL) 468 #define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL) 469 #define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\ 470 M_DM_PARTIAL_CRC_PARTIAL) 471 472 #define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) 473 #define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL) 474 #define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL) 475 #define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\ 476 M_DM_PARTIAL_TCPCS_PARTIAL) 477 478 #define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) 479 #endif /* 112x PASS1 */ 480 481 482 #if SIBYTE_HDR_FEATURE(112x, PASS1) 483 /* 484 * Data Mover CRC Definition Registers 485 * Register: CRC_DEF_0 486 * Register: CRC_DEF_1 487 */ 488 #define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) 489 #define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT) 490 #define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT) 491 #define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\ 492 M_CRC_DEF_CRC_INIT) 493 494 #define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) 495 #define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY) 496 #define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) 497 #define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ 498 M_CRC_DEF_CRC_POLY) 499 #endif /* 112x PASS1 */ 500 501 502 #if SIBYTE_HDR_FEATURE(112x, PASS1) 503 /* 504 * Data Mover CRC/Checksum Definition Registers 505 * Register: CTCP_DEF_0 506 * Register: CTCP_DEF_1 507 */ 508 #define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) 509 #define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR) 510 #define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR) 511 #define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\ 512 M_CTCP_DEF_CRC_TXOR) 513 514 #define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) 515 #define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT) 516 #define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT) 517 #define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\ 518 M_CTCP_DEF_TCPCS_INIT) 519 520 #define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) 521 #define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH) 522 #define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH) 523 #define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\ 524 M_CTCP_DEF_CRC_WIDTH) 525 526 #define K_CTCP_DEF_CRC_WIDTH_4 0 527 #define K_CTCP_DEF_CRC_WIDTH_2 1 528 #define K_CTCP_DEF_CRC_WIDTH_1 2 529 530 #define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) 531 #endif /* 112x PASS1 */ 532 533 534 /* 535 * Data Mover Descriptor Doubleword "A" (Table 7-26) 536 */ 537 538 #define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) 539 #define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR) 540 541 #define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) 542 #define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) 543 #define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42) 544 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 545 #define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43) 546 #endif /* up to 1250 PASS1 */ 547 548 #define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) 549 #define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST) 550 #define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST) 551 #define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST) 552 553 #define K_DM_DSCRA_DIR_DEST_INCR 0 554 #define K_DM_DSCRA_DIR_DEST_DECR 1 555 #define K_DM_DSCRA_DIR_DEST_CONST 2 556 557 #define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST) 558 #define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST) 559 #define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST) 560 561 #define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) 562 #define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC) 563 #define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC) 564 #define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC) 565 566 #define K_DM_DSCRA_DIR_SRC_INCR 0 567 #define K_DM_DSCRA_DIR_SRC_DECR 1 568 #define K_DM_DSCRA_DIR_SRC_CONST 2 569 570 #define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC) 571 #define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC) 572 #define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC) 573 574 575 #define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) 576 #define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49) 577 #define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) 578 #define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) 579 580 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 581 #define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) 582 #define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) 583 #endif /* 1250 PASS2 || 112x PASS1 */ 584 585 #if SIBYTE_HDR_FEATURE(112x, PASS1) 586 #define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) 587 #define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) 588 #define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) 589 #define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57) 590 #define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58) 591 #define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) 592 #define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) 593 #define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) 594 #endif /* 112x PASS1 */ 595 596 #define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) 597 598 /* 599 * Data Mover Descriptor Doubleword "B" (Table 7-25) 600 */ 601 602 #define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) 603 #define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR) 604 605 #define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) 606 #define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH) 607 #define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH) 608 #define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH) 609 610 611 #endif 612