1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Generic Bus Constants File: sb1250_genbus.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the SB1250's Generic Bus interface 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions as 27 * they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. Neither the "Broadcom 31 * Corporation" name nor any trademark or logo of Broadcom 32 * Corporation may be used to endorse or promote products 33 * derived from this software without the prior written 34 * permission of Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 52 #ifndef _SB1250_GENBUS_H 53 #define _SB1250_GENBUS_H 54 55 #include "sb1250_defs.h" 56 57 /* 58 * Generic Bus Region Configuration Registers (Table 11-4) 59 */ 60 61 #define S_IO_RDY_ACTIVE 0 62 #define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) 63 64 #define S_IO_ENA_RDY 1 65 #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) 66 67 #define S_IO_WIDTH_SEL 2 68 #define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) 69 #define K_IO_WIDTH_SEL_1 0 70 #define K_IO_WIDTH_SEL_2 1 71 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 72 #define K_IO_WIDTH_SEL_1L 2 73 #endif /* 1250 PASS2 || 112x PASS1 */ 74 #define K_IO_WIDTH_SEL_4 3 75 #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) 76 #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) 77 78 #define S_IO_PARITY_ENA 4 79 #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) 80 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 81 #define S_IO_BURST_EN 5 82 #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) 83 #endif /* 1250 PASS2 || 112x PASS1 */ 84 #define S_IO_PARITY_ODD 6 85 #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) 86 #define S_IO_NONMUX 7 87 #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) 88 89 #define S_IO_TIMEOUT 8 90 #define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) 91 #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) 92 #define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) 93 94 /* 95 * Generic Bus Region Size register (Table 11-5) 96 */ 97 98 #define S_IO_MULT_SIZE 0 99 #define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) 100 #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) 101 #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) 102 103 #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ 104 105 /* 106 * Generic Bus Region Address (Table 11-6) 107 */ 108 109 #define S_IO_START_ADDR 0 110 #define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) 111 #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) 112 #define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) 113 114 #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ 115 116 /* 117 * Generic Bus Region 0 Timing Registers (Table 11-7) 118 */ 119 120 #define S_IO_ALE_WIDTH 0 121 #define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) 122 #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) 123 #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) 124 125 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 126 #define M_IO_EARLY_CS _SB_MAKEMASK1(3) 127 #endif /* 1250 PASS2 || 112x PASS1 */ 128 129 #define S_IO_ALE_TO_CS 4 130 #define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) 131 #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) 132 #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) 133 134 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 135 #define S_IO_BURST_WIDTH _SB_MAKE64(6) 136 #define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) 137 #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) 138 #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) 139 #endif /* 1250 PASS2 || 112x PASS1 */ 140 141 #define S_IO_CS_WIDTH 8 142 #define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) 143 #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) 144 #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) 145 146 #define S_IO_RDY_SMPLE 13 147 #define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) 148 #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) 149 #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) 150 151 152 /* 153 * Generic Bus Timing 1 Registers (Table 11-8) 154 */ 155 156 #define S_IO_ALE_TO_WRITE 0 157 #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) 158 #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) 159 #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) 160 161 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 162 #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) 163 #endif /* 1250 PASS2 || 112x PASS1 */ 164 165 #define S_IO_WRITE_WIDTH 4 166 #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) 167 #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) 168 #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) 169 170 #define S_IO_IDLE_CYCLE 8 171 #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) 172 #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) 173 #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) 174 175 #define S_IO_OE_TO_CS 12 176 #define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) 177 #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) 178 #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) 179 180 #define S_IO_CS_TO_OE 14 181 #define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) 182 #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) 183 #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) 184 185 /* 186 * Generic Bus Interrupt Status Register (Table 11-9) 187 */ 188 189 #define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) 190 #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) 191 #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) 192 #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) 193 #define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) 194 #define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) 195 #define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) 196 #define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) 197 #define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) 198 199 #define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) 200 #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) 201 #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) 202 #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) 203 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 204 #define M_IO_COH_ERR _SB_MAKEMASK1(14) 205 #endif /* 1250 PASS2 || 112x PASS1 */ 206 207 /* 208 * PCMCIA configuration register (Table 12-6) 209 */ 210 211 #define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) 212 #define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) 213 #define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) 214 #define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) 215 #define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) 216 #define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) 217 #define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) 218 #define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) 219 #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) 220 #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) 221 222 /* 223 * PCMCIA status register (Table 12-7) 224 */ 225 226 #define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) 227 #define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) 228 #define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) 229 #define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) 230 #define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) 231 #define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) 232 #define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) 233 #define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) 234 #define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) 235 #define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) 236 #define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) 237 238 /* 239 * GPIO Interrupt Type Register (table 13-3) 240 */ 241 242 #define K_GPIO_INTR_DISABLE 0 243 #define K_GPIO_INTR_EDGE 1 244 #define K_GPIO_INTR_LEVEL 2 245 #define K_GPIO_INTR_SPLIT 3 246 247 #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) 248 #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) 249 #define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) 250 #define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) 251 252 #define S_GPIO_INTR_TYPE0 0 253 #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) 254 #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) 255 #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) 256 257 #define S_GPIO_INTR_TYPE2 2 258 #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) 259 #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) 260 #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) 261 262 #define S_GPIO_INTR_TYPE4 4 263 #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) 264 #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) 265 #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) 266 267 #define S_GPIO_INTR_TYPE6 6 268 #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) 269 #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) 270 #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) 271 272 #define S_GPIO_INTR_TYPE8 8 273 #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) 274 #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) 275 #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) 276 277 #define S_GPIO_INTR_TYPE10 10 278 #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) 279 #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) 280 #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) 281 282 #define S_GPIO_INTR_TYPE12 12 283 #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) 284 #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) 285 #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) 286 287 #define S_GPIO_INTR_TYPE14 14 288 #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) 289 #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) 290 #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) 291 292 293 #endif 294