1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * MAC constants and macros File: sb1250_mac.h 5 * 6 * This module contains constants and macros for the SB1250's 7 * ethernet controllers. 8 * 9 * SB1250 specification level: 0.2 plus errata as of 4/10/2001 10 * 11 * Author: Mitch Lichtenberg (mitch@sibyte.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions as 27 * they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. Neither the "Broadcom 31 * Corporation" name nor any trademark or logo of Broadcom 32 * Corporation may be used to endorse or promote products 33 * derived from this software without the prior written 34 * permission of Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 52 #ifndef _SB1250_MAC_H 53 #define _SB1250_MAC_H 54 55 #include "sb1250_defs.h" 56 57 /* ********************************************************************* 58 * Ethernet MAC Registers 59 ********************************************************************* */ 60 61 /* 62 * MAC Configuration Register (Table 9-13) 63 * Register: MAC_CFG_0 64 * Register: MAC_CFG_1 65 * Register: MAC_CFG_2 66 */ 67 68 69 /* Updated to spec 0.2 */ 70 71 #define M_MAC_RESERVED0 _SB_MAKEMASK1(0) 72 #define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) 73 #define M_MAC_RETRY_EN _SB_MAKEMASK1(2) 74 #define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) 75 #define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) 76 #define M_MAC_BURST_EN _SB_MAKEMASK1(5) 77 78 #define S_MAC_TX_PAUSE _SB_MAKE64(6) 79 #define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) 80 #define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) 81 82 #define K_MAC_TX_PAUSE_CNT_512 0 83 #define K_MAC_TX_PAUSE_CNT_1K 1 84 #define K_MAC_TX_PAUSE_CNT_2K 2 85 #define K_MAC_TX_PAUSE_CNT_4K 3 86 #define K_MAC_TX_PAUSE_CNT_8K 4 87 #define K_MAC_TX_PAUSE_CNT_16K 5 88 #define K_MAC_TX_PAUSE_CNT_32K 6 89 #define K_MAC_TX_PAUSE_CNT_64K 7 90 91 #define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) 92 #define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) 93 #define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) 94 #define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) 95 #define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) 96 #define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) 97 #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) 98 #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) 99 100 #define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) 101 102 #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 103 #define M_MAC_RESERVED2 _SB_MAKEMASK1(18) 104 #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) 105 #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) 106 #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) 107 #define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) 108 #define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) 109 #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) 110 #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) 111 112 #define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) 113 114 #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) 115 #define M_MAC_HDX_EN _SB_MAKEMASK1(33) 116 117 #define S_MAC_SPEED_SEL _SB_MAKE64(34) 118 #define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) 119 #define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) 120 #define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) 121 122 #define K_MAC_SPEED_SEL_10MBPS 0 123 #define K_MAC_SPEED_SEL_100MBPS 1 124 #define K_MAC_SPEED_SEL_1000MBPS 2 125 #define K_MAC_SPEED_SEL_RESERVED 3 126 127 #define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) 128 #define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) 129 #define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) 130 #define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) 131 132 #define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) 133 #define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) 134 #define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) 135 #define M_MAC_SS_EN _SB_MAKEMASK1(39) 136 137 #define S_MAC_BYPASS_CFG _SB_MAKE64(40) 138 #define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) 139 #define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) 140 #define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) 141 142 #define K_MAC_BYPASS_GMII 0 143 #define K_MAC_BYPASS_ENCODED 1 144 #define K_MAC_BYPASS_SOP 2 145 #define K_MAC_BYPASS_EOP 3 146 147 #define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) 148 #define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) 149 150 #define M_MAC_RESERVED4 _SB_MAKEMASK(2,44) 151 152 #define S_MAC_BYPASS_IFG _SB_MAKE64(46) 153 #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) 154 #define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) 155 #define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) 156 157 #define K_MAC_FC_CMD_DISABLED 0 158 #define K_MAC_FC_CMD_ENABLED 1 159 #define K_MAC_FC_CMD_ENAB_FALSECARR 2 160 161 #define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) 162 #define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) 163 #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) 164 165 #define M_MAC_FC_SEL _SB_MAKEMASK1(54) 166 167 #define S_MAC_FC_CMD _SB_MAKE64(55) 168 #define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) 169 #define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) 170 #define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) 171 172 #define S_MAC_RX_CH_SEL _SB_MAKE64(57) 173 #define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) 174 #define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) 175 #define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) 176 177 178 /* 179 * MAC Enable Registers 180 * Register: MAC_ENABLE_0 181 * Register: MAC_ENABLE_1 182 * Register: MAC_ENABLE_2 183 */ 184 185 #define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) 186 #define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) 187 #define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) 188 #define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) 189 190 #define M_MAC_PORT_RESET _SB_MAKEMASK1(8) 191 192 #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) 193 #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) 194 #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) 195 #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) 196 197 /* 198 * MAC DMA Control Register 199 * Register: MAC_TXD_CTL_0 200 * Register: MAC_TXD_CTL_1 201 * Register: MAC_TXD_CTL_2 202 */ 203 204 #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) 205 #define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) 206 #define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) 207 #define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) 208 209 #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) 210 #define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) 211 #define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) 212 #define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) 213 214 /* 215 * MAC Fifo Threshhold registers (Table 9-14) 216 * Register: MAC_THRSH_CFG_0 217 * Register: MAC_THRSH_CFG_1 218 * Register: MAC_THRSH_CFG_2 219 */ 220 221 #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) 222 #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) 223 #define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) 224 #define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) 225 226 #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) 227 #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) 228 #define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) 229 #define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) 230 231 #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) 232 #define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) 233 #define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) 234 #define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) 235 236 #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) 237 #define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) 238 #define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) 239 #define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) 240 241 #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) 242 #define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) 243 #define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) 244 #define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) 245 246 #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) 247 #define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) 248 #define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) 249 #define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) 250 251 /* 252 * MAC Frame Configuration Registers (Table 9-15) 253 * Register: MAC_FRAME_CFG_0 254 * Register: MAC_FRAME_CFG_1 255 * Register: MAC_FRAME_CFG_2 256 */ 257 258 #define S_MAC_IFG_RX _SB_MAKE64(0) 259 #define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) 260 #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) 261 #define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) 262 263 #define S_MAC_IFG_TX _SB_MAKE64(6) 264 #define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) 265 #define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) 266 #define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) 267 268 #define S_MAC_IFG_THRSH _SB_MAKE64(12) 269 #define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) 270 #define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) 271 #define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) 272 273 #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) 274 #define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) 275 #define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) 276 #define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) 277 278 #define S_MAC_LFSR_SEED _SB_MAKE64(22) 279 #define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) 280 #define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) 281 #define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) 282 283 #define S_MAC_SLOT_SIZE _SB_MAKE64(30) 284 #define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) 285 #define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) 286 #define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) 287 288 #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) 289 #define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) 290 #define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) 291 #define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) 292 293 #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) 294 #define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) 295 #define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) 296 #define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) 297 298 /* 299 * These constants are used to configure the fields within the Frame 300 * Configuration Register. 301 */ 302 303 #define K_MAC_IFG_RX_10 _SB_MAKE64(18) 304 #define K_MAC_IFG_RX_100 _SB_MAKE64(18) 305 #define K_MAC_IFG_RX_1000 _SB_MAKE64(6) 306 307 #define K_MAC_IFG_TX_10 _SB_MAKE64(20) 308 #define K_MAC_IFG_TX_100 _SB_MAKE64(20) 309 #define K_MAC_IFG_TX_1000 _SB_MAKE64(8) 310 311 #define K_MAC_IFG_THRSH_10 _SB_MAKE64(12) 312 #define K_MAC_IFG_THRSH_100 _SB_MAKE64(12) 313 #define K_MAC_IFG_THRSH_1000 _SB_MAKE64(4) 314 315 #define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) 316 #define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) 317 #define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) 318 319 #define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) 320 #define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) 321 #define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) 322 323 #define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) 324 #define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) 325 #define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) 326 327 #define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) 328 #define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) 329 #define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) 330 331 #define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) 332 #define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) 333 #define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) 334 335 #define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) 336 #define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) 337 338 #define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) 339 #define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) 340 341 /* 342 * MAC VLAN Tag Registers (Table 9-16) 343 * Register: MAC_VLANTAG_0 344 * Register: MAC_VLANTAG_1 345 * Register: MAC_VLANTAG_2 346 */ 347 348 /* No bit fields: lower 32 bits of register are the tags */ 349 350 /* 351 * MAC Status Registers (Table 9-17) 352 * Also used for the MAC Interrupt Mask Register (Table 9-18) 353 * Register: MAC_STATUS_0 354 * Register: MAC_STATUS_1 355 * Register: MAC_STATUS_2 356 * Register: MAC_INT_MASK_0 357 * Register: MAC_INT_MASK_1 358 * Register: MAC_INT_MASK_2 359 */ 360 361 /* 362 * Use these constants to shift the appropriate channel 363 * into the CH0 position so the same tests can be used 364 * on each channel. 365 */ 366 367 #define S_MAC_RX_CH0 _SB_MAKE64(0) 368 #define S_MAC_RX_CH1 _SB_MAKE64(8) 369 #define S_MAC_TX_CH0 _SB_MAKE64(16) 370 #define S_MAC_TX_CH1 _SB_MAKE64(24) 371 372 #define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ 373 #define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ 374 375 /* 376 * These are the same as RX channel 0. The idea here 377 * is that you'll use one of the "S_" things above 378 * and pass just the six bits to a DMA-channel-specific ISR 379 */ 380 #define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) 381 #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) 382 #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) 383 #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) 384 #define M_MAC_INT_HWM _SB_MAKEMASK1(3) 385 #define M_MAC_INT_LWM _SB_MAKEMASK1(4) 386 #define M_MAC_INT_DSCR _SB_MAKEMASK1(5) 387 #define M_MAC_INT_ERR _SB_MAKEMASK1(6) 388 #define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ 389 390 391 #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) 392 #define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) 393 #define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) 394 #define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) 395 #define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) 396 #define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) 397 #define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) 398 399 #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 400 #define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) 401 #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) 402 #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) 403 404 /* 405 * MAC Fifo Pointer Registers (Table 9-19) [Debug register] 406 * Register: MAC_FIFO_PTRS_0 407 * Register: MAC_FIFO_PTRS_1 408 * Register: MAC_FIFO_PTRS_2 409 */ 410 411 #define S_MAC_TX_WRPTR _SB_MAKE64(0) 412 #define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) 413 #define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) 414 #define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) 415 416 #define S_MAC_TX_RDPTR _SB_MAKE64(8) 417 #define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) 418 #define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) 419 #define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) 420 421 #define S_MAC_RX_WRPTR _SB_MAKE64(16) 422 #define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) 423 #define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) 424 #define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) 425 426 #define S_MAC_RX_RDPTR _SB_MAKE64(24) 427 #define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) 428 #define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) 429 #define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) 430 431 /* 432 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] 433 * Register: MAC_EOPCNT_0 434 * Register: MAC_EOPCNT_1 435 * Register: MAC_EOPCNT_2 436 */ 437 438 #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) 439 #define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) 440 #define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) 441 #define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) 442 443 #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) 444 #define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) 445 #define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) 446 #define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) 447 448 /* 449 * MAC Recieve Address Filter Exact Match Registers (Table 9-21) 450 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 451 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 452 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 453 */ 454 455 /* No bitfields */ 456 457 /* 458 * MAC Recieve Address Filter Hash Match Registers (Table 9-22) 459 * Registers: MAC_HASH0_0 through MAC_HASH7_0 460 * Registers: MAC_HASH0_1 through MAC_HASH7_1 461 * Registers: MAC_HASH0_2 through MAC_HASH7_2 462 */ 463 464 /* No bitfields */ 465 466 /* 467 * MAC Transmit Source Address Registers (Table 9-23) 468 * Register: MAC_ETHERNET_ADDR_0 469 * Register: MAC_ETHERNET_ADDR_1 470 * Register: MAC_ETHERNET_ADDR_2 471 */ 472 473 /* No bitfields */ 474 475 /* 476 * MAC Packet Type Configuration Register 477 * Register: MAC_TYPE_CFG_0 478 * Register: MAC_TYPE_CFG_1 479 * Register: MAC_TYPE_CFG_2 480 */ 481 482 #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) 483 484 #define S_TYPECFG_TYPE0 _SB_MAKE64(0) 485 #define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) 486 #define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) 487 #define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) 488 489 #define S_TYPECFG_TYPE1 _SB_MAKE64(0) 490 #define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) 491 #define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) 492 #define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) 493 494 #define S_TYPECFG_TYPE2 _SB_MAKE64(0) 495 #define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) 496 #define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) 497 #define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) 498 499 #define S_TYPECFG_TYPE3 _SB_MAKE64(0) 500 #define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) 501 #define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) 502 #define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) 503 504 /* 505 * MAC Receive Address Filter Control Registers (Table 9-24) 506 * Register: MAC_ADFILTER_CFG_0 507 * Register: MAC_ADFILTER_CFG_1 508 * Register: MAC_ADFILTER_CFG_2 509 */ 510 511 #define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) 512 #define M_MAC_UCAST_EN _SB_MAKEMASK1(1) 513 #define M_MAC_UCAST_INV _SB_MAKEMASK1(2) 514 #define M_MAC_MCAST_EN _SB_MAKEMASK1(3) 515 #define M_MAC_MCAST_INV _SB_MAKEMASK1(4) 516 #define M_MAC_BCAST_EN _SB_MAKEMASK1(5) 517 #define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) 518 519 #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 520 #define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) 521 #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) 522 #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) 523 524 /* 525 * MAC Receive Channel Select Registers (Table 9-25) 526 */ 527 528 /* no bitfields */ 529 530 /* 531 * MAC MII Management Interface Registers (Table 9-26) 532 * Register: MAC_MDIO_0 533 * Register: MAC_MDIO_1 534 * Register: MAC_MDIO_2 535 */ 536 537 #define S_MAC_MDC 0 538 #define S_MAC_MDIO_DIR 1 539 #define S_MAC_MDIO_OUT 2 540 #define S_MAC_GENC 3 541 #define S_MAC_MDIO_IN 4 542 543 #define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) 544 #define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) 545 #define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) 546 #define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) 547 #define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) 548 #define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) 549 550 #endif 551