1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Memory Controller constants File: sb1250_mc.h 5 * 6 * This module contains constants and macros useful for 7 * programming the memory controller. 8 * 9 * SB1250 specification level: 0.2 10 * 11 * Author: Mitch Lichtenberg (mitch@sibyte.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions as 27 * they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. Neither the "Broadcom 31 * Corporation" name nor any trademark or logo of Broadcom 32 * Corporation may be used to endorse or promote products 33 * derived from this software without the prior written 34 * permission of Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 52 #ifndef _SB1250_MC_H 53 #define _SB1250_MC_H 54 55 #include "sb1250_defs.h" 56 57 /* 58 * Memory Channel Config Register (table 6-14) 59 */ 60 61 #define S_MC_RESERVED0 0 62 #define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) 63 64 #define S_MC_CHANNEL_SEL 8 65 #define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) 66 #define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) 67 #define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) 68 69 #define S_MC_BANK0_MAP 16 70 #define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) 71 #define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) 72 #define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) 73 74 #define K_MC_BANK0_MAP_DEFAULT 0x00 75 #define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) 76 77 #define S_MC_BANK1_MAP 20 78 #define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) 79 #define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) 80 #define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) 81 82 #define K_MC_BANK1_MAP_DEFAULT 0x08 83 #define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) 84 85 #define S_MC_BANK2_MAP 24 86 #define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) 87 #define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) 88 #define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) 89 90 #define K_MC_BANK2_MAP_DEFAULT 0x09 91 #define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) 92 93 #define S_MC_BANK3_MAP 28 94 #define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) 95 #define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) 96 #define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) 97 98 #define K_MC_BANK3_MAP_DEFAULT 0x0C 99 #define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) 100 101 #define M_MC_RESERVED1 _SB_MAKEMASK(8,32) 102 103 #define S_MC_QUEUE_SIZE 40 104 #define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) 105 #define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) 106 #define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) 107 #define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) 108 109 #define S_MC_AGE_LIMIT 44 110 #define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) 111 #define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) 112 #define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) 113 #define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) 114 115 #define S_MC_WR_LIMIT 48 116 #define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) 117 #define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) 118 #define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) 119 #define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) 120 121 #define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) 122 123 #define M_MC_RESERVED2 _SB_MAKEMASK(3,53) 124 125 #define S_MC_CS_MODE 56 126 #define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) 127 #define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) 128 #define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) 129 130 #define K_MC_CS_MODE_MSB_CS 0 131 #define K_MC_CS_MODE_INTLV_CS 15 132 #define K_MC_CS_MODE_MIXED_CS_10 12 133 #define K_MC_CS_MODE_MIXED_CS_30 6 134 #define K_MC_CS_MODE_MIXED_CS_32 3 135 136 #define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) 137 #define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) 138 #define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) 139 #define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) 140 #define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) 141 142 #define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) 143 #define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) 144 #define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) 145 #define M_MC_DEBUG _SB_MAKEMASK1(63) 146 147 #define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | \ 148 V_MC_AGE_LIMIT_DEFAULT | \ 149 V_MC_BANK0_MAP_DEFAULT | \ 150 V_MC_BANK1_MAP_DEFAULT | \ 151 V_MC_BANK2_MAP_DEFAULT | \ 152 V_MC_BANK3_MAP_DEFAULT | \ 153 V_MC_CHANNEL_SEL(0) | \ 154 M_MC_IOB1HIGHPRIORITY | \ 155 V_MC_QUEUE_SIZE_DEFAULT 156 157 158 /* 159 * Memory clock config register (Table 6-15) 160 * 161 * Note: this field has been updated to be consistent with the errata to 0.2 162 */ 163 164 #define S_MC_CLK_RATIO 0 165 #define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) 166 #define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) 167 #define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) 168 169 #define K_MC_CLK_RATIO_2X 4 170 #define K_MC_CLK_RATIO_25X 5 171 #define K_MC_CLK_RATIO_3X 6 172 #define K_MC_CLK_RATIO_35X 7 173 #define K_MC_CLK_RATIO_4X 8 174 #define K_MC_CLK_RATIO_45X 9 175 176 #define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) 177 #define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) 178 #define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) 179 #define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) 180 #define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) 181 #define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) 182 #define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X 183 184 #define S_MC_REF_RATE 8 185 #define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) 186 #define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) 187 #define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) 188 189 #define K_MC_REF_RATE_100MHz 0x62 190 #define K_MC_REF_RATE_133MHz 0x81 191 #define K_MC_REF_RATE_200MHz 0xC4 192 193 #define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) 194 #define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) 195 #define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) 196 #define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz 197 198 #define S_MC_CLOCK_DRIVE 16 199 #define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) 200 #define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) 201 #define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) 202 #define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) 203 204 #define S_MC_DATA_DRIVE 20 205 #define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) 206 #define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) 207 #define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) 208 #define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) 209 210 #define S_MC_ADDR_DRIVE 24 211 #define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) 212 #define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) 213 #define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) 214 #define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) 215 216 #define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) 217 218 #define S_MC_DQI_SKEW 32 219 #define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) 220 #define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) 221 #define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) 222 #define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) 223 224 #define S_MC_DQO_SKEW 40 225 #define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) 226 #define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) 227 #define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) 228 #define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) 229 230 #define S_MC_ADDR_SKEW 48 231 #define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) 232 #define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) 233 #define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) 234 #define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) 235 236 #define S_MC_DLL_DEFAULT 56 237 #define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) 238 #define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) 239 #define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) 240 #define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) 241 242 #define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ 243 V_MC_ADDR_SKEW_DEFAULT | \ 244 V_MC_DQO_SKEW_DEFAULT | \ 245 V_MC_DQI_SKEW_DEFAULT | \ 246 V_MC_ADDR_DRIVE_DEFAULT | \ 247 V_MC_DATA_DRIVE_DEFAULT | \ 248 V_MC_CLOCK_DRIVE_DEFAULT | \ 249 V_MC_REF_RATE_DEFAULT 250 251 252 253 /* 254 * DRAM Command Register (Table 6-13) 255 */ 256 257 #define S_MC_COMMAND 0 258 #define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) 259 #define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) 260 #define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) 261 262 #define K_MC_COMMAND_EMRS 0 263 #define K_MC_COMMAND_MRS 1 264 #define K_MC_COMMAND_PRE 2 265 #define K_MC_COMMAND_AR 3 266 #define K_MC_COMMAND_SETRFSH 4 267 #define K_MC_COMMAND_CLRRFSH 5 268 #define K_MC_COMMAND_SETPWRDN 6 269 #define K_MC_COMMAND_CLRPWRDN 7 270 271 #define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) 272 #define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) 273 #define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) 274 #define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) 275 #define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) 276 #define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) 277 #define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) 278 #define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) 279 280 #define M_MC_CS0 _SB_MAKEMASK1(4) 281 #define M_MC_CS1 _SB_MAKEMASK1(5) 282 #define M_MC_CS2 _SB_MAKEMASK1(6) 283 #define M_MC_CS3 _SB_MAKEMASK1(7) 284 285 /* 286 * DRAM Mode Register (Table 6-14) 287 */ 288 289 #define S_MC_EMODE 0 290 #define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) 291 #define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) 292 #define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) 293 #define V_MC_EMODE_DEFAULT V_MC_EMODE(0) 294 295 #define S_MC_MODE 16 296 #define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) 297 #define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) 298 #define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) 299 #define V_MC_MODE_DEFAULT V_MC_MODE(0x22) 300 301 #define S_MC_DRAM_TYPE 32 302 #define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) 303 #define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) 304 #define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) 305 306 #define K_MC_DRAM_TYPE_JEDEC 0 307 #define K_MC_DRAM_TYPE_FCRAM 1 308 #define K_MC_DRAM_TYPE_SGRAM 2 309 310 #define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) 311 #define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) 312 #define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) 313 314 #define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) 315 316 317 318 319 /* 320 * SDRAM Timing Register (Table 6-15) 321 */ 322 323 #define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) 324 #define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) 325 #define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(60) 326 327 #define S_MC_tFIFO 56 328 #define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) 329 #define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) 330 #define K_MC_tFIFO_DEFAULT 1 331 #define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) 332 333 #define S_MC_tRFC 52 334 #define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) 335 #define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) 336 #define K_MC_tRFC_DEFAULT 12 337 #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) 338 339 #define S_MC_tCwCr 40 340 #define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) 341 #define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) 342 #define K_MC_tCwCr_DEFAULT 4 343 #define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) 344 345 #define S_MC_tRCr 28 346 #define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) 347 #define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) 348 #define K_MC_tRCr_DEFAULT 9 349 #define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) 350 351 #define S_MC_tRCw 24 352 #define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) 353 #define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) 354 #define K_MC_tRCw_DEFAULT 10 355 #define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) 356 357 #define S_MC_tRRD 20 358 #define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) 359 #define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) 360 #define K_MC_tRRD_DEFAULT 2 361 #define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) 362 363 #define S_MC_tRP 16 364 #define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) 365 #define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) 366 #define K_MC_tRP_DEFAULT 4 367 #define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) 368 369 #define S_MC_tCwD 8 370 #define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) 371 #define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) 372 #define K_MC_tCwD_DEFAULT 1 373 #define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) 374 375 #define M_tCrDh _SB_MAKEMASK1(7) 376 377 #define S_MC_tCrD 4 378 #define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) 379 #define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) 380 #define K_MC_tCrD_DEFAULT 2 381 #define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) 382 383 #define S_MC_tRCD 0 384 #define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) 385 #define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) 386 #define K_MC_tRCD_DEFAULT 3 387 #define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) 388 389 #define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ 390 V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ 391 V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ 392 V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ 393 V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ 394 V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ 395 V_MC_tRP(K_MC_tRP_DEFAULT) | \ 396 V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ 397 V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ 398 V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ 399 M_MC_r2rIDLE_TWOCYCLES 400 401 /* 402 * Errata says these are not the default 403 * M_MC_w2rIDLE_TWOCYCLES | \ 404 * M_MC_r2wIDLE_TWOCYCLES | \ 405 */ 406 407 408 /* 409 * Chip Select Start Address Register (Table 6-17) 410 */ 411 412 #define S_MC_CS0_START 0 413 #define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) 414 #define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) 415 #define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) 416 417 #define S_MC_CS1_START 16 418 #define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) 419 #define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) 420 #define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) 421 422 #define S_MC_CS2_START 32 423 #define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) 424 #define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) 425 #define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) 426 427 #define S_MC_CS3_START 48 428 #define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) 429 #define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) 430 #define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) 431 432 /* 433 * Chip Select End Address Register (Table 6-18) 434 */ 435 436 #define S_MC_CS0_END 0 437 #define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) 438 #define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) 439 #define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) 440 441 #define S_MC_CS1_END 16 442 #define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) 443 #define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) 444 #define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) 445 446 #define S_MC_CS2_END 32 447 #define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) 448 #define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) 449 #define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) 450 451 #define S_MC_CS3_END 48 452 #define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) 453 #define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) 454 #define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) 455 456 /* 457 * Chip Select Interleave Register (Table 6-19) 458 */ 459 460 #define S_MC_INTLV_RESERVED 0 461 #define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) 462 463 #define S_MC_INTERLEAVE 7 464 #define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) 465 #define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) 466 467 #define S_MC_INTLV_MBZ 25 468 #define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) 469 470 /* 471 * Row Address Bits Register (Table 6-20) 472 */ 473 474 #define S_MC_RAS_RESERVED 0 475 #define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) 476 477 #define S_MC_RAS_SELECT 12 478 #define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) 479 #define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) 480 481 #define S_MC_RAS_MBZ 37 482 #define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) 483 484 485 /* 486 * Column Address Bits Register (Table 6-21) 487 */ 488 489 #define S_MC_CAS_RESERVED 0 490 #define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) 491 492 #define S_MC_CAS_SELECT 5 493 #define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) 494 #define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) 495 496 #define S_MC_CAS_MBZ 23 497 #define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) 498 499 500 /* 501 * Bank Address Address Bits Register (Table 6-22) 502 */ 503 504 #define S_MC_BA_RESERVED 0 505 #define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) 506 507 #define S_MC_BA_SELECT 5 508 #define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) 509 #define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) 510 511 #define S_MC_BA_MBZ 25 512 #define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) 513 514 /* 515 * Chip Select Attribute Register (Table 6-23) 516 */ 517 518 #define K_MC_CS_ATTR_CLOSED 0 519 #define K_MC_CS_ATTR_CASCHECK 1 520 #define K_MC_CS_ATTR_HINT 2 521 #define K_MC_CS_ATTR_OPEN 3 522 523 #define S_MC_CS0_PAGE 0 524 #define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) 525 #define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) 526 #define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) 527 528 #define S_MC_CS1_PAGE 16 529 #define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) 530 #define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) 531 #define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) 532 533 #define S_MC_CS2_PAGE 32 534 #define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) 535 #define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) 536 #define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) 537 538 #define S_MC_CS3_PAGE 48 539 #define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) 540 #define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) 541 #define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) 542 543 /* 544 * ECC Test ECC Register (Table 6-25) 545 */ 546 547 #define S_MC_ECC_INVERT 0 548 #define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) 549 550 551 #endif 552