1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * SCD Constants and Macros File: sb1250_scd.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module on the 1250. 8 * 9 * SB1250 specification level: 0.2 plus errata as of 11/7/2000 10 * 11 * Author: Mitch Lichtenberg (mitch@sibyte.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions as 27 * they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. Neither the "Broadcom 31 * Corporation" name nor any trademark or logo of Broadcom 32 * Corporation may be used to endorse or promote products 33 * derived from this software without the prior written 34 * permission of Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 #ifndef _SB1250_SCD_H 52 #define _SB1250_SCD_H 53 54 #include "sb1250_defs.h" 55 56 /* ********************************************************************* 57 * System control/debug registers 58 ********************************************************************* */ 59 60 /* 61 * System Revision Register (Table 4-1) 62 */ 63 64 #define M_SYS_RESERVED _SB_MAKEMASK(8,0) 65 66 #define S_SYS_REVISION _SB_MAKE64(8) 67 #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 68 #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 69 #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 70 71 #define K_SYS_REVISION_PASS1 1 72 #define K_SYS_REVISION_PASS2 3 73 #define K_SYS_REVISION_PASS3 4 /* XXX Unknown */ 74 75 #define S_SYS_PART _SB_MAKE64(16) 76 #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 77 #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 78 #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 79 80 #define K_SYS_PART_SB1250 0x1250 81 #define K_SYS_PART_SB1125 0x1125 82 83 #define S_SYS_WID _SB_MAKE64(32) 84 #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 85 #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 86 #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 87 88 /* 89 * System Config Register (Table 4-2) 90 * Register: SCD_SYSTEM_CFG 91 */ 92 93 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 94 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 95 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 96 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 97 98 #define S_SYS_PLL_DIV _SB_MAKE64(7) 99 #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 100 #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 101 #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 102 103 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 104 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 105 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) 106 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) 107 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 108 109 #define S_SYS_BOOT_MODE _SB_MAKE64(17) 110 #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 111 #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 112 #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 113 #define K_SYS_BOOT_MODE_ROM32 0 114 #define K_SYS_BOOT_MODE_ROM8 1 115 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 116 #define K_SYS_BOOT_MODE_SMBUS_BIG 3 117 118 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) 119 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) 120 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) 121 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 122 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) 123 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) 124 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 125 126 #define S_SYS_CONFIG 26 127 #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 128 #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 129 #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 130 131 /* The following bits are writeable by JTAG only. */ 132 133 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) 134 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 135 136 #define S_SYS_CLKCOUNT 34 137 #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 138 #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 139 #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 140 141 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 142 143 #define S_SYS_PLL_IREF 43 144 #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 145 146 #define S_SYS_PLL_VCO 45 147 #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 148 149 #define S_SYS_PLL_VREG 47 150 #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 151 152 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 153 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 154 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) 155 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) 156 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) 157 158 /* End of bits writable by JTAG only. */ 159 160 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) 161 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) 162 163 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) 164 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) 165 166 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) 167 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) 168 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) 169 170 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) 171 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) 172 173 /* 174 * Mailbox Registers (Table 4-3) 175 * Registers: SCD_MBOX_CPU_x 176 */ 177 178 #define S_MBOX_INT_3 0 179 #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 180 #define S_MBOX_INT_2 16 181 #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 182 #define S_MBOX_INT_1 32 183 #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 184 #define S_MBOX_INT_0 48 185 #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 186 187 /* 188 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 189 * Registers: SCD_WDOG_INIT_CNT_x 190 */ 191 192 #define V_SCD_WDOG_FREQ 1000000 193 194 #define S_SCD_WDOG_INIT 0 195 #define M_SCD_WDOG_INIT _SB_MAKEMASK(13,S_SCD_WDOG_INIT) 196 197 #define S_SCD_WDOG_CNT 0 198 #define M_SCD_WDOG_CNT _SB_MAKEMASK(13,S_SCD_WDOG_CNT) 199 200 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 201 202 /* 203 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) 204 */ 205 206 #define V_SCD_TIMER_FREQ 1000000 207 208 #define S_SCD_TIMER_INIT 0 209 #define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) 210 #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 211 #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 212 213 #define S_SCD_TIMER_CNT 0 214 #define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) 215 #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 216 #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 217 218 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 219 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 220 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE 221 222 /* 223 * System Performance Counters 224 */ 225 226 #define S_SPC_CFG_SRC0 0 227 #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 228 #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 229 #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 230 231 #define S_SPC_CFG_SRC1 8 232 #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 233 #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 234 #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 235 236 #define S_SPC_CFG_SRC2 16 237 #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 238 #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 239 #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 240 241 #define S_SPC_CFG_SRC3 24 242 #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 243 #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 244 #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 245 246 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 247 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 248 249 250 /* 251 * Bus Watcher 252 */ 253 254 #define S_SCD_BERR_TID 8 255 #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 256 #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 257 #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 258 259 #define S_SCD_BERR_RID 18 260 #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 261 #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 262 #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 263 264 #define S_SCD_BERR_DCODE 22 265 #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 266 #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 267 #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 268 269 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 270 271 272 #define S_SCD_L2ECC_CORR_D 0 273 #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 274 #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 275 #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 276 277 #define S_SCD_L2ECC_BAD_D 8 278 #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 279 #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 280 #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 281 282 #define S_SCD_L2ECC_CORR_T 16 283 #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 284 #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 285 #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 286 287 #define S_SCD_L2ECC_BAD_T 24 288 #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 289 #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 290 #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 291 292 #define S_SCD_MEM_ECC_CORR 0 293 #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 294 #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 295 #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 296 297 #define S_SCD_MEM_ECC_BAD 16 298 #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 299 #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 300 #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 301 302 #define S_SCD_MEM_BUSERR 24 303 #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 304 #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 305 #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 306 307 308 /* 309 * Address Trap Registers 310 */ 311 312 #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 313 #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 314 315 #define S_ATRAP_CFG_CNT 0 316 #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 317 #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 318 #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 319 320 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 321 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 322 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) 323 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 324 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 325 326 #define S_ATRAP_CFG_AGENTID 8 327 #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 328 #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 329 #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 330 331 #define K_BUS_AGENT_CPU0 0 332 #define K_BUS_AGENT_CPU1 1 333 #define K_BUS_AGENT_IOB0 2 334 #define K_BUS_AGENT_IOB1 3 335 #define K_BUS_AGENT_SCD 4 336 #define K_BUS_AGENT_RESERVED 5 337 #define K_BUS_AGENT_L2C 6 338 #define K_BUS_AGENT_MC 7 339 340 #define S_ATRAP_CFG_CATTR 12 341 #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 342 #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 343 #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 344 345 #define K_ATRAP_CFG_CATTR_IGNORE 0 346 #define K_ATRAP_CFG_CATTR_UNC 1 347 #define K_ATRAP_CFG_CATTR_CACHEABLE 2 348 #define K_ATRAP_CFG_CATTR_NONCOH 3 349 #define K_ATRAP_CFG_CATTR_COHERENT 4 350 #define K_ATRAP_CFG_CATTR_NOTUNC 5 351 #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 352 #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 353 354 /* 355 * Trace Buffer Config register 356 */ 357 358 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 359 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 360 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 361 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) 362 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) 363 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 364 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 365 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 366 367 #define S_SCD_TRACE_CFG_CUR_ADDR 10 368 #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 369 #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 370 #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 371 372 /* 373 * Trace Event registers 374 */ 375 376 #define S_SCD_TREVT_ADDR_MATCH 0 377 #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 378 #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 379 #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 380 381 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 382 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 383 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) 384 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) 385 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) 386 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) 387 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 388 389 #define S_SCD_TREVT_REQID 12 390 #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 391 #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 392 #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 393 394 #define S_SCD_TREVT_RESPID 16 395 #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 396 #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 397 #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 398 399 #define S_SCD_TREVT_DATAID 20 400 #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 401 #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 402 #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 403 404 #define S_SCD_TREVT_COUNT 24 405 #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 406 #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 407 #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 408 409 /* 410 * Trace Sequence registers 411 */ 412 413 #define S_SCD_TRSEQ_EVENT4 0 414 #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 415 #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 416 #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 417 418 #define S_SCD_TRSEQ_EVENT3 4 419 #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 420 #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 421 #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 422 423 #define S_SCD_TRSEQ_EVENT2 8 424 #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 425 #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 426 #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 427 428 #define S_SCD_TRSEQ_EVENT1 12 429 #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 430 #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 431 #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 432 433 #define K_SCD_TRSEQ_E0 0 434 #define K_SCD_TRSEQ_E1 1 435 #define K_SCD_TRSEQ_E2 2 436 #define K_SCD_TRSEQ_E3 3 437 #define K_SCD_TRSEQ_E0_E1 4 438 #define K_SCD_TRSEQ_E1_E2 5 439 #define K_SCD_TRSEQ_E2_E3 6 440 #define K_SCD_TRSEQ_E0_E1_E2 7 441 #define K_SCD_TRSEQ_E0_E1_E2_E3 8 442 #define K_SCD_TRSEQ_E0E1 9 443 #define K_SCD_TRSEQ_E0E1E2 10 444 #define K_SCD_TRSEQ_E0E1E2E3 11 445 #define K_SCD_TRSEQ_E0E1_E2 12 446 #define K_SCD_TRSEQ_E0E1_E2E3 13 447 #define K_SCD_TRSEQ_E0E1_E2_E3 14 448 #define K_SCD_TRSEQ_IGNORED 15 449 450 #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ 451 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ 452 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ 453 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 454 455 #define S_SCD_TRSEQ_FUNCTION 16 456 #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 457 #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 458 #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 459 460 #define K_SCD_TRSEQ_FUNC_NOP 0 461 #define K_SCD_TRSEQ_FUNC_START 1 462 #define K_SCD_TRSEQ_FUNC_STOP 2 463 #define K_SCD_TRSEQ_FUNC_FREEZE 3 464 465 #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) 466 #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) 467 #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) 468 #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) 469 470 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) 471 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) 472 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 473 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 474 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 475 476 #endif 477