1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * SCD Constants and Macros File: sb1250_scd.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module on the 1250. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions as 27 * they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. Neither the "Broadcom 31 * Corporation" name nor any trademark or logo of Broadcom 32 * Corporation may be used to endorse or promote products 33 * derived from this software without the prior written 34 * permission of Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 #ifndef _SB1250_SCD_H 52 #define _SB1250_SCD_H 53 54 #include "sb1250_defs.h" 55 56 /* ********************************************************************* 57 * System control/debug registers 58 ********************************************************************* */ 59 60 /* 61 * System Revision Register (Table 4-1) 62 */ 63 64 #define M_SYS_RESERVED _SB_MAKEMASK(8,0) 65 66 #define S_SYS_REVISION _SB_MAKE64(8) 67 #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 68 #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 69 #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 70 71 #if SIBYTE_HDR_FEATURE_CHIP(1250) 72 #define K_SYS_REVISION_BCM1250_PASS1 1 73 #define K_SYS_REVISION_BCM1250_PASS2 3 74 #define K_SYS_REVISION_BCM1250_PASS2_2 16 75 #define K_SYS_REVISION_BCM1250_PASS3 32 76 77 /* XXX: discourage people from using these constants. */ 78 #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 79 #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 80 #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 81 #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 82 #endif /* 1250 */ 83 84 #if SIBYTE_HDR_FEATURE_CHIP(112x) 85 #define K_SYS_REVISION_BCM112x_PASS1 32 86 #endif /* 112x */ 87 88 /* XXX: discourage people from using these constants. */ 89 #define S_SYS_PART _SB_MAKE64(16) 90 #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 91 #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 92 #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 93 94 /* XXX: discourage people from using these constants. */ 95 #define K_SYS_PART_SB1250 0x1250 96 #define K_SYS_PART_BCM1120 0x1121 97 #define K_SYS_PART_BCM1125 0x1123 98 #define K_SYS_PART_BCM1125H 0x1124 99 100 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 101 #define S_SYS_SOC_TYPE _SB_MAKE64(16) 102 #define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) 103 #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) 104 #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) 105 106 #define K_SYS_SOC_TYPE_BCM1250 0x0 107 #define K_SYS_SOC_TYPE_BCM1120 0x1 108 #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ 109 #define K_SYS_SOC_TYPE_BCM1125 0x3 110 #define K_SYS_SOC_TYPE_BCM1125H 0x4 111 #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ 112 113 /* 114 * Calculate correct SOC type given a copy of system revision register. 115 * 116 * (For the assembler version, sysrev and dest may be the same register. 117 * Also, it clobbers AT.) 118 */ 119 #ifdef __ASSEMBLER__ 120 #define SYS_SOC_TYPE(dest, sysrev) \ 121 .set push ; \ 122 .set reorder ; \ 123 dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ 124 andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ 125 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ 126 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ 127 b 992f ; \ 128 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ 129 992: \ 130 .set pop 131 #else 132 #define SYS_SOC_TYPE(sysrev) \ 133 ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ 134 || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ 135 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) 136 #endif 137 138 #define S_SYS_WID _SB_MAKE64(32) 139 #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 140 #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 141 #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 142 143 /* 144 * System Config Register (Table 4-2) 145 * Register: SCD_SYSTEM_CFG 146 */ 147 148 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 149 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 150 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 151 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 152 153 #define S_SYS_PLL_DIV _SB_MAKE64(7) 154 #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 155 #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 156 #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 157 158 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 159 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 160 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) 161 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) 162 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 163 164 #define S_SYS_BOOT_MODE _SB_MAKE64(17) 165 #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 166 #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 167 #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 168 #define K_SYS_BOOT_MODE_ROM32 0 169 #define K_SYS_BOOT_MODE_ROM8 1 170 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 171 #define K_SYS_BOOT_MODE_SMBUS_BIG 3 172 173 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) 174 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) 175 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) 176 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 177 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) 178 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) 179 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 180 181 #define S_SYS_CONFIG 26 182 #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 183 #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 184 #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 185 186 /* The following bits are writeable by JTAG only. */ 187 188 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) 189 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 190 191 #define S_SYS_CLKCOUNT 34 192 #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 193 #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 194 #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 195 196 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 197 198 #define S_SYS_PLL_IREF 43 199 #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 200 201 #define S_SYS_PLL_VCO 45 202 #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 203 204 #define S_SYS_PLL_VREG 47 205 #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 206 207 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 208 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 209 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) 210 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) 211 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) 212 213 /* End of bits writable by JTAG only. */ 214 215 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) 216 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) 217 218 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) 219 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) 220 221 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) 222 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) 223 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) 224 225 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) 226 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) 227 228 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 229 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) 230 #endif /* 1250 PASS2 || 112x PASS1 */ 231 232 233 /* 234 * Mailbox Registers (Table 4-3) 235 * Registers: SCD_MBOX_CPU_x 236 */ 237 238 #define S_MBOX_INT_3 0 239 #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 240 #define S_MBOX_INT_2 16 241 #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 242 #define S_MBOX_INT_1 32 243 #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 244 #define S_MBOX_INT_0 48 245 #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 246 247 /* 248 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 249 * Registers: SCD_WDOG_INIT_CNT_x 250 */ 251 252 #define V_SCD_WDOG_FREQ 1000000 253 254 #define S_SCD_WDOG_INIT 0 255 #define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) 256 257 #define S_SCD_WDOG_CNT 0 258 #define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) 259 260 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 261 262 /* 263 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) 264 */ 265 266 #define V_SCD_TIMER_FREQ 1000000 267 268 #define S_SCD_TIMER_INIT 0 269 #define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) 270 #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 271 #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 272 273 #define S_SCD_TIMER_CNT 0 274 #define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) 275 #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 276 #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 277 278 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 279 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 280 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE 281 282 /* 283 * System Performance Counters 284 */ 285 286 #define S_SPC_CFG_SRC0 0 287 #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 288 #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 289 #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 290 291 #define S_SPC_CFG_SRC1 8 292 #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 293 #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 294 #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 295 296 #define S_SPC_CFG_SRC2 16 297 #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 298 #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 299 #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 300 301 #define S_SPC_CFG_SRC3 24 302 #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 303 #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 304 #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 305 306 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 307 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 308 309 310 /* 311 * Bus Watcher 312 */ 313 314 #define S_SCD_BERR_TID 8 315 #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 316 #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 317 #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 318 319 #define S_SCD_BERR_RID 18 320 #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 321 #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 322 #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 323 324 #define S_SCD_BERR_DCODE 22 325 #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 326 #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 327 #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 328 329 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 330 331 332 #define S_SCD_L2ECC_CORR_D 0 333 #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 334 #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 335 #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 336 337 #define S_SCD_L2ECC_BAD_D 8 338 #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 339 #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 340 #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 341 342 #define S_SCD_L2ECC_CORR_T 16 343 #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 344 #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 345 #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 346 347 #define S_SCD_L2ECC_BAD_T 24 348 #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 349 #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 350 #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 351 352 #define S_SCD_MEM_ECC_CORR 0 353 #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 354 #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 355 #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 356 357 #define S_SCD_MEM_ECC_BAD 8 358 #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 359 #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 360 #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 361 362 #define S_SCD_MEM_BUSERR 16 363 #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 364 #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 365 #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 366 367 368 /* 369 * Address Trap Registers 370 */ 371 372 #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 373 #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 374 375 #define S_ATRAP_CFG_CNT 0 376 #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 377 #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 378 #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 379 380 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 381 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 382 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) 383 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 384 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 385 386 #define S_ATRAP_CFG_AGENTID 8 387 #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 388 #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 389 #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 390 391 #define K_BUS_AGENT_CPU0 0 392 #define K_BUS_AGENT_CPU1 1 393 #define K_BUS_AGENT_IOB0 2 394 #define K_BUS_AGENT_IOB1 3 395 #define K_BUS_AGENT_SCD 4 396 #define K_BUS_AGENT_RESERVED 5 397 #define K_BUS_AGENT_L2C 6 398 #define K_BUS_AGENT_MC 7 399 400 #define S_ATRAP_CFG_CATTR 12 401 #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 402 #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 403 #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 404 405 #define K_ATRAP_CFG_CATTR_IGNORE 0 406 #define K_ATRAP_CFG_CATTR_UNC 1 407 #define K_ATRAP_CFG_CATTR_CACHEABLE 2 408 #define K_ATRAP_CFG_CATTR_NONCOH 3 409 #define K_ATRAP_CFG_CATTR_COHERENT 4 410 #define K_ATRAP_CFG_CATTR_NOTUNC 5 411 #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 412 #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 413 414 /* 415 * Trace Buffer Config register 416 */ 417 418 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 419 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 420 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 421 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) 422 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) 423 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 424 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 425 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 426 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 427 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 428 #endif /* 1250 PASS2 || 112x PASS1 */ 429 430 #define S_SCD_TRACE_CFG_CUR_ADDR 10 431 #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 432 #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 433 #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 434 435 /* 436 * Trace Event registers 437 */ 438 439 #define S_SCD_TREVT_ADDR_MATCH 0 440 #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 441 #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 442 #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 443 444 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 445 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 446 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) 447 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) 448 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) 449 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) 450 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 451 452 #define S_SCD_TREVT_REQID 12 453 #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 454 #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 455 #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 456 457 #define S_SCD_TREVT_RESPID 16 458 #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 459 #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 460 #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 461 462 #define S_SCD_TREVT_DATAID 20 463 #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 464 #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 465 #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 466 467 #define S_SCD_TREVT_COUNT 24 468 #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 469 #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 470 #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 471 472 /* 473 * Trace Sequence registers 474 */ 475 476 #define S_SCD_TRSEQ_EVENT4 0 477 #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 478 #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 479 #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 480 481 #define S_SCD_TRSEQ_EVENT3 4 482 #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 483 #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 484 #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 485 486 #define S_SCD_TRSEQ_EVENT2 8 487 #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 488 #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 489 #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 490 491 #define S_SCD_TRSEQ_EVENT1 12 492 #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 493 #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 494 #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 495 496 #define K_SCD_TRSEQ_E0 0 497 #define K_SCD_TRSEQ_E1 1 498 #define K_SCD_TRSEQ_E2 2 499 #define K_SCD_TRSEQ_E3 3 500 #define K_SCD_TRSEQ_E0_E1 4 501 #define K_SCD_TRSEQ_E1_E2 5 502 #define K_SCD_TRSEQ_E2_E3 6 503 #define K_SCD_TRSEQ_E0_E1_E2 7 504 #define K_SCD_TRSEQ_E0_E1_E2_E3 8 505 #define K_SCD_TRSEQ_E0E1 9 506 #define K_SCD_TRSEQ_E0E1E2 10 507 #define K_SCD_TRSEQ_E0E1E2E3 11 508 #define K_SCD_TRSEQ_E0E1_E2 12 509 #define K_SCD_TRSEQ_E0E1_E2E3 13 510 #define K_SCD_TRSEQ_E0E1_E2_E3 14 511 #define K_SCD_TRSEQ_IGNORED 15 512 513 #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ 514 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ 515 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ 516 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 517 518 #define S_SCD_TRSEQ_FUNCTION 16 519 #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 520 #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 521 #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 522 523 #define K_SCD_TRSEQ_FUNC_NOP 0 524 #define K_SCD_TRSEQ_FUNC_START 1 525 #define K_SCD_TRSEQ_FUNC_STOP 2 526 #define K_SCD_TRSEQ_FUNC_FREEZE 3 527 528 #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) 529 #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) 530 #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) 531 #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) 532 533 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) 534 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) 535 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 536 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 537 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 538 539 #endif 540